Semiconductor structure, preparation method thereof and storage array structure

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure, a preparation method thereof and a memory array structure.The semiconductor structure comprises a substrate, a first transistor and a second transistor, the first transistor and the second transistor are located on the substrate, and the first transistor comprises a first semiconductor layer, a first grid electrode, a read bit line and a read word line; the first semiconductor layer comprises a first end and a second end which are opposite in the first direction, the read bit line is in electric contact with the first end, and the read word line is in electric contact with the second end; the second transistor comprises a second semiconductor layer, a second grid electrode, a writing bit line and a writing word line, the second semiconductor layer comprises a third end and a fourth end which are opposite in the second direction, the first grid electrode is in electric contact with the third end, and the writing bit line is in electric contact with the fourth end; the first direction intersects with the second direction; wherein orthographic projections of at least two of the read bit line, the read word line and the write bit line on the substrate are overlapped.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the semiconductor field, and in particular to a semiconductor structure and a preparation method thereof, and a storage array structure. Background Art

[0002] The DRAM memory cells in computers are made of a single transistor and a single capacitor, a so-called 1T1C design. When writing to this memory cell, the transistor is turned on and charge is pushed into or removed from the capacitor; when reading, the charge (if any) is extracted and measured. The system is super fast, cheap, and consumes very little power, but it has some disadvantages.

[0003] First, the capacitor consumes charge when it is read, so reading means writing that bit back to memory. Even if it is not read, the charge will eventually leak out of the capacitor through the transistor. All cells need to be refreshed regularly to maintain the data. In current DRAM chips, this operation is done every 64ms. But there are difficulties in making capacitors and making transistors with ultra-low leakage, so it is difficult to make good capacitors in a manufacturing process built for logic circuits.

[0004] For the above reasons, a new type of embedded capacitor-free DRAM, referred to as 2T0C structure, is applied. 2T0C embedded DRAM consists of two transistors. The bit is stored in the capacitor of the right transistor and is placed there by the left device. The charge on the gate of the right device means that current can flow through it, so reading and writing are controlled only by the transistor. How to improve the integration of semiconductor structures in the process of preparing the 2T0C structure is a problem that technicians in this field currently need to consider. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, and a storage array structure, which are at least beneficial to improving the integration of the semiconductor structure.

[0006] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a substrate; a first transistor located on the substrate, the first transistor including a first semiconductor layer, a first gate, a read bit line and a read word line, the first semiconductor layer including a first end and a second end opposite to each other along a first direction, the read bit line is electrically in contact with the first end, and the read word line is electrically in contact with the second end; a second transistor, the second transistor is located on one side of the first semiconductor layer along a second direction; the second transistor includes a second semiconductor layer, a second gate, a write bit line and a write word line, the second gate is located on one side of the second semiconductor layer along the first direction, and the write word line is electrically in contact with one side of the second gate along a third direction; the second semiconductor layer includes a third end and a fourth end opposite to each other along the second direction, the first gate is electrically in contact with the third end, and the write bit line is electrically in contact with the fourth end; the first direction, the second direction and the third direction intersect each other; wherein at least two of the read bit line, the read word line and the write bit line overlap in the orthographic projection of the substrate.

[0007] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a storage array structure, including: a semiconductor structure as described in any of the above embodiments, a plurality of the semiconductor structures are arranged in an array along the third direction and along the first direction, the read bit line is electrically connected to the first ends of the plurality of first semiconductor layers arranged along the third direction, and the read word line is electrically connected to the second ends of the plurality of first semiconductor layers arranged along the third direction; the second transistor is located on one side of the first semiconductor layer of the corresponding first transistor along the second direction; the write word line is electrically connected to the plurality of second gates arranged along the first direction, and the write bit line is electrically connected to the fourth ends of the plurality of second semiconductor layers arranged along the third direction; at least two of the read bit lines have overlapping orthographic projections on the substrate; and / or, at least two of the read word lines have overlapping orthographic projections on the substrate; and / or, at least two of the write bit lines have overlapping orthographic projections on the substrate.

[0008] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for preparing a semiconductor structure, comprising: providing a substrate; forming a first transistor, the first transistor being located on the substrate, the first transistor comprising a first semiconductor layer, a first gate, a read bit line and a read word line, the first semiconductor layer comprising a first end and a second end opposite to each other along a first direction, the read bit line being electrically in contact with the first end, and the read word line being electrically in contact with the second end; forming a second transistor, the second transistor being located on one side of the first semiconductor layer along a second direction; the second transistor comprising a second semiconductor layer, a second gate, a write bit line and a write word line, the second gate being located on one side of the second semiconductor layer along the first direction, and the write word line being electrically in contact with one side of the second gate along a third direction; the second semiconductor layer comprising a third end and a fourth end opposite to each other along the second direction, the first gate being electrically in contact with the third end, and the write bit line being electrically in contact with the fourth end; the first direction, the second direction and the third direction intersect each other; wherein at least two of the read bit line, the read word line and the write bit line overlap in their orthographic projections on the substrate.

[0009] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0010] In the semiconductor structure provided by the embodiment of the present disclosure, the first semiconductor layer includes a first end and a second end opposite to each other, and the second semiconductor layer includes a third end and a fourth end opposite to each other along a second direction, and the first direction intersects with the second direction. By designing the first semiconductor layer and the second semiconductor layer, the extension directions of the first transistor and the second transistor are different. Based on this, the read bit line electrically connected to the first end, the read word line electrically connected to the second end, and the write bit line electrically connected to the fourth end can be arranged in sequence along the surface perpendicular to the substrate, and the extension directions of the read bit line, the read word line, and the write bit line are also consistent, thereby saving the projection area and improving the integration. In addition, at least two of the read bit line, the read word line, and the write bit line overlap in the positive projection of the substrate, thereby further projecting the area and improving the integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0012] Figure 1A schematic diagram of a first structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0013] Figure 2 A second structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0014] Figure 3 A third structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0015] Figure 4 for Figure 3 Schematic diagram of the cross-sectional structure along the A1-A2 section;

[0016] Figure 5 for Figure 3 Schematic diagram of the cross-sectional structure along the B1-B2 section;

[0017] Figure 6 A fourth structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0018] Figure 7 for Figure 6 Schematic diagram of the cross-sectional structure along the C1-C2 section;

[0019] Figure 8 A first structural schematic diagram of a storage array structure provided by an embodiment of the present disclosure;

[0020] Fig. 9 for Figure 8 The corresponding top view;

[0021] Fig.10 for Figure 8 or Fig. 9 Schematic diagram of the cross-sectional structure along the A1-A2 section;

[0022] Fig.11 for Figure 8 or Fig. 9 Schematic diagram of the cross-sectional structure along the C1-C2 section;

[0023] Fig.12 for Fig. 9 Schematic diagram of the cross-sectional structure along the D1-D2 section;

[0024] Fig.13 A second structural schematic diagram of a storage array structure provided in an embodiment of the present disclosure;

[0025] Fig.14 for Fig.13 Schematic diagram of the cross-sectional structure along the C1-C2 section;

[0026] Figure 15 to Figure 31A schematic diagram of the structure of the semiconductor structure corresponding to each step in the method for preparing a memory array structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] As can be seen from the background art, the integration level of current semiconductor structures is poor.

[0028] The disclosed embodiment provides a semiconductor structure and a preparation method thereof, and a storage array structure. In the semiconductor structure, a first semiconductor layer is provided to include a first end and a second end opposite to each other, and a second semiconductor layer includes a third end and a fourth end opposite to each other along a second direction. The first direction intersects with the second direction. Through the design of the first semiconductor layer and the second semiconductor layer, the extension direction of the first transistor and the second transistor are different. Based on this, a read bit line electrically connected to the first end, a read word line electrically connected to the second end, and a write bit line electrically connected to the fourth end can be arranged in sequence along a surface perpendicular to the substrate, and the extension directions of the read bit line, the read word line, and the write bit line are also consistent, thereby saving the projection area and improving the integration. In addition, at least two of the read bit line, the read word line, and the write bit line overlap in the positive projection of the substrate, thereby further increasing the projection area and improving the integration.

[0029] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0030] Figure 1 A schematic diagram of a first structure of a semiconductor structure provided by an embodiment of the present disclosure; Figure 2 A second structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figure 3 A third structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figure 4 for Figure 3 Schematic diagram of the cross-sectional structure along the A1-A2 section; Figure 5 for Figure 3 Schematic diagram of the cross-sectional structure along the B1-B2 section; Figure 6 A fourth structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figure 7 for Figure 6 Schematic diagram of the cross-sectional structure along the C1-C2 section. Figure 1 to Figure 3 as well as Figure 6 The writing lines in the figure are perspective views, that is, the film structure below the writing lines can be seen through the writing lines.

[0031] refer to Figure 1According to some embodiments of the present disclosure, the present disclosure provides a semiconductor structure on one hand, including: a substrate 100; a first transistor 10 located on the substrate 100, the first transistor 10 including a first semiconductor layer 130, a first gate 133, a read bit line 121 and a read word line 122, the first semiconductor layer 130 including a first end 131 and a second end 132 opposite to each other along a first direction Z, the read bit line 121 is in electrical contact with the first end 131, and the read word line 122 is in electrical contact with the second end 132; a second transistor 20, the second transistor 20 is located on one side of the first semiconductor layer 130 along a second direction X; the second transistor 20 includes a second semiconductor layer 140, a second gate 143, a write bit line 123 and a write word line 124, the second gate 143 is located on one side of the second semiconductor layer 140 along the first direction Z, and the write word line 124 is electrically contacted with one side of the second gate 143 along the third direction Y; the second semiconductor layer 140 includes a third end 141 and a fourth end 142 opposite to each other along the second direction X, the first gate 133 is electrically contacted with the third end 141, and the write bit line 123 is electrically contacted with the fourth end 142; the first direction Z, the second direction X and the third direction Y intersect each other; wherein, at least two of the read bit line 121, the read word line 122 and the write bit line 123 overlap in their orthographic projections on the substrate 100.

[0032] In some embodiments, the substrate 100 is a single-layer structure, and the material of the substrate 100 is a semiconductor material, and the semiconductor material may include any one of silicon, germanium, silicon carbide, or silicon germanium. The substrate 100 contains an N-type doping element or a P-type doping element. The N-type doping element may be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), and the P-type doping element may be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0033] In some embodiments, the first transistor 10 is used as a read transistor and the second transistor 20 is used as a write transistor. The first transistor 10 and the second transistor 20 form a 2T0C structure. Among them, the gate of the write transistor (T1) is used to connect to the write word line 124 (WWL), one of the source and drain electrodes of the write transistor (T1) is used to connect to the write bit line 123 (WBL), and the other electrode of the source and drain of the write transistor (T1) is used to connect to the gate of the read transistor (T2). The electrode in the write transistor (T1) connected to the gate of the read transistor (T2) and the gate of the read transistor (T2) constitute a storage node (SN) for storing data. One of the source and drain electrodes of the read transistor (T2) is used to connect to the read word line 122 (RWL), and the other electrode of the source and drain of the read transistor is used to connect to the read bit line 121 (RBL).

[0034] In some embodiments, the write transistor (T1) or the read transistor (T2) may be an N-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or a P-type MOSFET.

[0035] The working principle of the first transistor 10 and the second transistor 20 is: a large voltage is applied to the gate of the write transistor (T1) through the write word line 124 (WWL) to turn on the write transistor (T1); when "1" needs to be written, a first voltage is applied to the write bit line 123 (WBL); when "0" needs to be written, a second voltage is applied to the write bit line 123 (WBL). There is a certain voltage difference between the first voltage and the second voltage. Whether the read data is "1" or "0" is determined by judging whether there is current passing between the read bit line 121 (RBL) and the read word line 122 (RWL).

[0036] In some embodiments, the material of the first semiconductor layer 130 includes a semiconductor material, such as silicon, germanium, or silicon germanium.

[0037] In some embodiments, the material of the first semiconductor layer 130 is an amorphous material, which has gaps inside and has a higher carrier mobility, which can reduce the thickness of the first semiconductor layer 130, reduce the line width of the semiconductor structure within a limited unit area, and further improve the storage density of the semiconductor structure. The amorphous material may include at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten-doped Indium Oxide), or ITO (Indium Tin Oxide).

[0038] In some embodiments, the material of the first semiconductor layer 130 includes IGZO, and the carrier mobility of IGZO is 20 to 50 times that of polysilicon, which is beneficial to improve the carrier mobility in the first semiconductor layer 130, thereby helping to reduce the leakage current when the semiconductor structure is working, so as to reduce the power consumption of the semiconductor structure and improve the working efficiency of the semiconductor structure. In addition, the thin film deposition process for preparing IGZO is simple, and the deposition temperature is low, which can improve the problems of thermal damage and thermal defects to the substrate and the active layer. Due to the characteristics of IGZO itself, the large-area first semiconductor layer 130 prepared by using IGZO has good uniformity, which can improve the electrical performance and stability of the first semiconductor layer 130.

[0039] In some embodiments, the first semiconductor layer 130 includes a first source-drain terminal, a third channel region, and a second source-drain terminal arranged in sequence. The first source-drain terminal is electrically in contact with the read bit line 121, the second source-drain terminal is electrically in contact with the read word line 122, and the first gate 133 is directly opposite to the third channel region.

[0040] In some embodiments, the material of the first gate 133 includes a metal material of doped polysilicon, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), tungsten (W), or an alloy thereof.

[0041] In some embodiments, the material of the read bit line 121 includes a metal material of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), tungsten (W) or alloys thereof.

[0042] In some embodiments, the material of the read word line 122 includes a metal material of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), tungsten (W) or alloys thereof.

[0043] In some embodiments, the material of the second semiconductor layer 140 includes semiconductor material and amorphous material.

[0044] In some embodiments, the second semiconductor layer 140 includes a third source-drain terminal, a first channel region, and a fourth source-drain terminal arranged in sequence, the third source-drain terminal is electrically in contact with the first gate 133 , and the fourth source-drain terminal is electrically in contact with the write bit line 123 .

[0045] In some embodiments, reference Figure 2 The second semiconductor layer 140 includes: a first doping region, a first channel region, a second doping region, a second channel region and a third doping region arranged in sequence, the second semiconductor layer surrounds the second gate 143, the first gate 133 is in electrical contact with the first doping region and the third doping region, and the write bit line 123 is in electrical contact with the second doping region. The second gate 143 controls the first channel region and the second channel region. Through the two channel regions, the gate control capability of the second gate 143 can be improved, and the length of the channel region is also increased, thereby reducing the threshold voltage of the second transistor 20. In addition, the second transistor 20 can be used as an active load of an amplifier, which can provide both current and large output impedance to achieve a large gain.

[0046] In some embodiments, the material of the second gate 143 includes a metal material of doped polysilicon, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), tungsten (W), or an alloy thereof.

[0047] In some embodiments, the material of the write bit line 123 includes a metal material of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), tungsten (W), or alloys thereof.

[0048] In some embodiments, the material of the write word line 124 includes a metal material of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), tungsten (W), or alloys thereof.

[0049] In some embodiments, the writing line 124 is made of the same material as the second gate 143. The writing line 124 and the second gate 143 are made in the same manufacturing process, so there is no interface threshold difference between the writing line 124 and the second gate 143, and the current can cross the interface between the second gate and the writing line 124 without any interface, thereby improving the migration speed of the current and improving the response speed of the second gate 143.

[0050] In some embodiments, the orthographic projection overlap of at least two of the read bit line 121, the read word line 122, and the write bit line 123 on the substrate 100 may include the orthographic projection overlap of the read bit line 121 and the read word line 122 on the substrate 100, and the orthographic projection overlap of the read bit line 121 and the write bit line 123 on the substrate 100 (refer to Figure 1 ), the orthographic projections of the write bit line 123 and the read word line 122 on the substrate 100 overlap, and the orthographic projections of the read bit line 121, the read word line 122 and the write bit line 123 on the substrate 100 overlap (refer to Figure 2 or Figure 3 ).

[0051] It is worth noting that the overlap of orthographic projections has two meanings: First, the area and contour of the orthographic projections are completely consistent, that is, the orthographic projections completely overlap (refer to Figure 1 ); The second type is that the area and contour of the orthographic projection are not completely consistent. The areas vary in size, and the larger area covers the smaller area, that is, the orthographic projections cover each other (refer to Figure 2 ).

[0052] Take the case where the orthographic projections of the read bit line 121 and the write bit line 123 on the substrate 100 completely overlap as an example. Figure 1 The extending direction of the read bit line 121 is the same as that of the write bit line 123, and the extending direction of the read word line 122 is opposite to that of the read bit line 121. The orthographic projections of the read bit line 121 and the write bit line 123 on the substrate 100 completely overlap.

[0053] The orthographic overlap of the read bit line 121, the read word line 122 and the write bit line 123 on the substrate 100 includes: Figure 2The orthographic projection of the read bit line 121 on the substrate 100 is located within the orthographic projection of the write bit line 123 on the substrate 100, and the orthographic projection of the write bit line 123 on the substrate 100 is located within the orthographic projection of the read word line 122 on the substrate 100; or as shown in Figure 3 As shown, the orthographic projections of the read bit line 121, the read word line 122, and the write bit line 123 on the substrate 100 completely overlap. In this way, the read bit line 121, the read word line 122, and the write bit line 123 have the same extension direction on the substrate 100, and the orthographic projections also overlap, which can save the unit configuration size of the read bit line 121, the read word line 122, and the write bit line 123, that is, there is spatial overlap in the vertical space, so as to save the floor space and floor space in the two-dimensional space, and improve the integration of the semiconductor structure in the horizontal direction.

[0054] Understandably, Figure 2 The orthographic projection of the read bit line 121 on the substrate 100 is shown to be located within the orthographic projection of the write bit line 123 on the substrate 100, and the orthographic projection of the write bit line 123 on the substrate 100 is located within the orthographic projection of the read word line 122 on the substrate 100. This is only for illustrative purposes. It is sufficient that the extension directions of the read bit line 121, the read word line 122 and the write bit line 123 on the substrate 100 are the same, and the orthographic projections of at least two of the read bit line 121, the read word line 122 and the write bit line 123 on the substrate 100 overlap.

[0055] refer to Figure 1 The semiconductor structure also includes: a first contact structure 151, a second contact structure 152 and a third contact structure 153, the first contact structure 151, the second contact structure 152 and the third contact structure 153 are respectively electrically contacted with the read bit line 121, the read word line 122 and the write bit line 123; at least three of the first contact structure 151, the second contact structure 152, the third contact structure 153, the read bit line 121, the read word line 122 and the write bit line 123 overlap in their orthographic projections on the substrate 100.

[0056] Among them, the first contact structure 151, the second contact structure 152 and the third contact structure 153 are used to connect the read bit line 121, the read word line 122 and the write bit line 123 in the semiconductor structure with external elements, so as to realize the positioning of the read bit line 121, the read word line 122 and the write bit line 123 in the semiconductor structure to a specific storage unit by regulating the external elements, so as to perform related reading and writing.

[0057] In some embodiments, the material of the first contact structure 151 includes a metal material of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), tungsten (W), or alloys thereof.

[0058] In some embodiments, the material of the second contact structure 152 includes a metal material of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), tungsten (W), or alloys thereof.

[0059] In some embodiments, the material of the third contact structure 153 includes a metal material of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), tungsten (W), or an alloy thereof.

[0060] In some embodiments, the first contact structure 151 , the second contact structure 152 , and the third contact structure 153 are fabricated in the same fabrication process.

[0061] In some embodiments, any one of the read bit line, the read word line, or the write bit line has a protrusion, and one of the first contact structure, the second contact structure, or the third contact structure is in electrical contact with the protrusion. The remaining first contact structure, the second contact structure, or the third contact structure is directly in electrical contact with the corresponding read bit line, the read word line, and the write bit line. For example, the write bit line has a protrusion, the third contact structure is in electrical contact with the protrusion, the first contact structure is in electrical contact with the read bit line, and the second contact structure penetrates the thickness of the read bit line and the write bit line and is in electrical contact with the read word line. In this way, the etching of the film layer of the read bit line and the write bit line can be reduced, thereby avoiding the problem of short circuit.

[0062] In some embodiments, any two of the read bit line, the read word line or the write bit line respectively have a first protrusion and a second protrusion, and two of the first contact structure, the second contact structure or the third contact structure are respectively electrically contacted with the first protrusion or the second protrusion; the orthographic projections of the first protrusion and the second protrusion on the substrate do not overlap.

[0063] In some embodiments, reference Figure 6 as well as Figure 7 , the read bit line 121, the read word line 122 or the write bit line 123 respectively have a first protrusion 161, a second protrusion 162 and a third protrusion 163, the first contact structure 151, the second contact structure 152 or the third contact structure 153 are respectively in electrical contact with the first protrusion 161, the second protrusion 162 and the third protrusion 163; the first protrusion 161, the second protrusion 162 and the third protrusion 163 do not overlap between the orthographic projections of the substrate 100. In this way, the etching of the film layer of the read bit line 121, the read word line 122 or the write bit line 123 may not be involved, thereby improving the stability of the film layer of the read bit line 121, the read word line 122 or the write bit line 123. In addition, there is no need to worry about the problem of short circuit and the increase in the yield of alignment, thereby improving the yield of the semiconductor structure.

[0064] refer to Figure 3 as well as Figure 5 , the first contact structure 151 is in electrical contact with the read bit line 121, the second contact structure 152 penetrates the thickness of the read bit line 121 and is in electrical contact with the read word line 122, and the third contact structure 153 penetrates the thickness of the read bit line 121 and is in electrical contact with the write bit line 123; and further includes: an isolation layer 154, the isolation layer 154 is located between the second contact structure 152 and the read bit line 121, between the second contact structure 152 and the write bit line 123, and between the third contact structure 153 and the read bit line 121. In this way, the orthographic projections of the first contact structure 151, the second contact structure 152, the third contact structure 153, the read bit line 121, the read word line 122, and the write bit line 123 on the substrate 100 are all overlapped, which can improve the integration of the semiconductor structure.

[0065] In some embodiments, the material of the isolation layer 154 includes silicon dioxide, silicon nitride, silicon oxynitride, or other high dielectric materials.

[0066] refer to Figure 4 The semiconductor structure further includes: a first gate dielectric layer 115 , and the first gate dielectric layer 115 is located between the first semiconductor layer 130 and the second semiconductor layer 140 and between the first semiconductor layer 130 and the first gate 133 .

[0067] The material of the first gate dielectric layer 115 may include silicon oxide, silicon carbide, silicon nitride or other materials with high dielectric constants, so as to suppress the short channel effect and thus suppress the tunneling leakage current and the like.

[0068] The semiconductor structure further includes: a second gate dielectric layer 125, which is located between the second gate 143 and the second semiconductor layer 140. The material of the second gate dielectric layer 125 may include silicon oxide, silicon carbide, silicon nitride or other high dielectric constant materials, which are used to suppress the short channel effect, thereby suppressing tunneling leakage current and the like.

[0069] The semiconductor structure further includes: a first sacrificial layer 101, the first sacrificial layer 101 is located on the surface of the substrate 100, a first semiconductor layer 130 and a second semiconductor layer 140 are located on the surface of the first sacrificial layer 101; a first isolation layer 113, the first isolation layer 113 is located between the first gate 133 and the second gate 143. A first filling layer 107, the first filling layer 107 is located between the read bit line 121 and the write bit line 123, and between the write bit line 123 and the read word line 122; a second filling layer 119, the second filling layer 119 is located between the first filling layer 107 and the first sacrificial layer 101; and further includes: a second filling layer 117, the second filling layer 117 is located on one side of the first semiconductor layer 130 along the second direction X.

[0070] In the semiconductor structure provided by the embodiment of the present disclosure, the first semiconductor layer 130 includes a first end 131 and a second end 132 opposite to each other, and the second semiconductor layer 140 includes a third end 142 and a fourth end 141 opposite to each other along the second direction X, and the first direction Z intersects with the second direction X. Through the design of the first semiconductor layer 130 and the second semiconductor layer 140, the extension directions of the first transistor 10 and the second transistor 20 are different. Based on this, the read bit line 121 electrically connected to the first end 131, the read word line 122 electrically connected to the second end 132, and the write bit line 123 electrically connected to the fourth end 142 can be arranged in sequence along the surface perpendicular to the substrate 100, and the extension directions of the read bit line 121, the read word line 122, and the write bit line 123 are also consistent, thereby saving the projection area and improving the integration. In addition, at least two of the read bit line 121, the read word line 122, and the write bit line 123 overlap in the positive projection on the substrate 100, thereby further increasing the projection area and improving the integration.

[0071] Accordingly, according to some embodiments of the present disclosure, the embodiments of the present disclosure further provide a storage array structure, including a semiconductor structure as described in any of the above embodiments, and technical features that are the same as or corresponding to the previous embodiment will not be repeated here.

[0072] Figure 8 A schematic diagram of a first structure of a storage array structure provided by an embodiment of the present disclosure; Fig. 9 for Figure 8 The corresponding top view; Fig.10 for Figure 8 or Fig. 9 Schematic diagram of the cross-sectional structure along the A1-A2 section; Fig.11 for Figure 8 or Fig. 9 Schematic diagram of the cross-sectional structure along the C1-C2 section; Fig.12 for Fig. 9 Schematic diagram of the cross-sectional structure along the D1-D2 section.

[0073] refer to Figure 8 The storage array structure includes: a plurality of semiconductor structures are arranged in an array along a third direction Y and along a first direction Z, a read bit line 121 is electrically connected to a first end 131 of a plurality of first semiconductor layers 130 arranged along the third direction Y, and a read word line 122 is electrically connected to a second end 132 of a plurality of first semiconductor layers 130 arranged along the third direction Y; the second transistor 20 is located on one side of the first semiconductor layer 130 of the corresponding first transistor 10 along the second direction X; a write word line 124 is electrically connected to a plurality of second gates 143 arranged along the first direction Z; and the write bit line 123 is electrically connected to a fourth end 142 of a plurality of second semiconductor layers 140 arranged along the third direction Y.

[0074] In some embodiments, orthographic projections of at least two read bit lines 121 on substrate 100 overlap.

[0075] In some embodiments, orthographic projections of at least two read word lines 122 on the substrate 100 overlap.

[0076] In some embodiments, orthographic projections of at least two write bit lines 123 on substrate 100 overlap.

[0077] refer to Figure 8 , the orthographic projections of each read bit line 121 , each read word line 122 , and each write bit line 123 on the substrate 100 overlap.

[0078] In some embodiments, it also includes: a plurality of first contact structures 151 arranged along the fourth direction, the first contact structure 151 is electrically in contact with the read bit line 121; a plurality of second contact structures 152 along the fifth direction, the second contact structure 152 is electrically in contact with the read word line 122; a plurality of third contact structures 153 arranged along the sixth direction, the third contact structure 153 is electrically in contact with the write bit line 123; at least one of the fourth direction, the fifth direction and the sixth direction is the same as the third direction Y.

[0079] In some embodiments, the fourth direction, the fifth direction, and the sixth direction are all the same as the third direction Y.

[0080] In some embodiments, a portion of the first contact structure 151 penetrates the thickness of the read word line 122 and the thickness of the write bit line 123 to electrically contact the read bit line 121 ; further comprising: an isolation layer 154 , the isolation layer 154 being located between the first contact structure 151 and the write bit line 123 and between the first contact structure 151 and the read word line 122 .

[0081] In some embodiments, part of the second contact structure 152 penetrates the thickness of the read bit line 121 and the thickness of the write bit line 123 to electrically contact the read word line 122; the isolation layer 154 is located between the second contact structure 152 and the write bit line 123 and between the second contact structure 152 and the read bit line 121.

[0082] In some embodiments, the third contact structure 153 penetrates the thickness of the read bit line 121 and the thickness of the read word line 122 to contact the write bit line 123; the isolation layer 154 is located between the third contact structure 153 and the read word line 122 and between the third contact structure 153 and the read bit line 121.

[0083] Fig.13 A second structural schematic diagram of a storage array structure provided in an embodiment of the present disclosure; Fig.14 for Fig.13 Schematic diagram of the cross-sectional structure along the C1-C2 section.

[0084] In some embodiments, reference Fig.13 or Fig.14 One end of the read bit line 121 away from the first semiconductor layer 130 has a first protrusion 161 , a plurality of first protrusions 161 are arranged at intervals along the fourth direction, and the first contact structure 151 is in electrical contact with the first protrusions 161 .

[0085] refer to Fig.13 or Fig.14 The read word line 122 has a second protrusion 162 on one side away from the first semiconductor layer 130 . The plurality of second protrusions 162 are arranged at intervals along the fifth direction, and the second contact structure 152 is in electrical contact with the second protrusions 162 .

[0086] refer to Fig.13 or Fig.14 The write bit line 123 has a third protrusion 163 on one side away from the first semiconductor layer 130 . The plurality of third protrusions 163 are arranged at intervals along the sixth direction, and the third contact structure 153 is in electrical contact with the third protrusions 163 .

[0087] Accordingly, according to some embodiments of the present disclosure, the embodiments of the present disclosure also provide a method for preparing a semiconductor structure and a method for preparing a storage array structure, which are used to prepare the semiconductor structure and storage array structure provided in the above embodiments. Elements that are the same as or corresponding to the previous embodiment will not be elaborated here. Figure 15 to Figure 31 A schematic diagram of the structure of the semiconductor structure corresponding to each step in the method for preparing a memory array structure provided in an embodiment of the present disclosure.

[0088] The preparation method comprises: providing a substrate 100; forming a first transistor 10, the first transistor 10 is located on the substrate 100, the first transistor 10 comprises a first semiconductor layer 130, a first gate 133, a read bit line 121 and a read word line 122, the first semiconductor layer 130 comprises a first end 131 and a second end 132 opposite to each other along a first direction Z, the read bit line 121 is in electrical contact with the first end 131, and the read word line 122 is in electrical contact with the second end 132; forming a second transistor 20, the second transistor 20 is located on one side of the first semiconductor layer 130 along a second direction X; the second transistor 20 comprises a second semiconductor layer 140, a second gate 133, a read bit line 121 and a read word line 122, the first semiconductor layer 130 comprises a first end 131 and a second end 132 opposite to each other along a first direction Z, the read bit line 121 is in electrical contact with the first end 131, and the read word line 122 is in electrical contact with the second end 132; The second gate 143, the write bit line 123 and the write word line 124, the second gate 143 is located on one side of the second semiconductor layer 140 along the first direction Z, and the write word line 124 is electrically in contact with one side of the second gate 143 along the third direction Y; the second semiconductor layer 140 includes a third end 141 and a fourth end 142 opposite to each other along the second direction X, the first gate 133 is electrically in contact with the third end 141, and the write bit line 123 is electrically in contact with the fourth end 142; the first direction Z, the second direction X and the third direction Y intersect in pairs; wherein, at least two of the read bit line 121, the read word line 122 and the write bit line 123 overlap in their orthographic projections on the substrate 100.

[0089] The present disclosure embodiment is formed Figure 8 The method for preparing the memory array structure shown is described as an example.

[0090] refer to Fig.15 , providing a substrate 100. The substrate 100 is a single film layer structure, and the material of the substrate 100 is a semiconductor material, and the semiconductor material may include any one of silicon, germanium, silicon carbide or silicon germanium. The substrate 100 has an N-type doping element or a P-type doping element. The N-type doping element may be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb) or arsenic (As), and the P-type doping element may be a Group III element such as boron (B), aluminum (Al), gallium (Ga) or indium (In).

[0091] refer to Fig.15 , a first sacrificial layer 101 and a second sacrificial layer 102 are formed on the surface of the substrate 100. Under the same etching process, the first sacrificial layer 101 and the second sacrificial layer 102 have different etching rates. The material of the first sacrificial layer 101 includes silicon oxide, and the material of the second sacrificial layer 102 includes silicon nitride.

[0092] Continue to refer Fig.15 A first film layer 103 , a second film layer 104 , a third film layer 105 and a fourth film layer 106 are alternately formed on the surface of the second sacrificial layer 102 , wherein the first film layer 103 and the third film layer 105 are made of the same material.

[0093] In some embodiments, the material of the first film layer 103 includes silicon dioxide, the material of the second film layer 104 includes polysilicon, the material of the third film layer 105 includes silicon dioxide, and the material of the second film layer 106 includes silicon nitride.

[0094] refer to Fig.16 , a portion of the width of the first film layer 103 and the third film layer 105 is removed to form a plurality of first grooves 171 arranged at intervals, and a portion of the width of the first film layer 103 and the third film layer 105 is still retained between the first grooves 171 and the first grooves 171.

[0095] refer to Fig.17 , forming a first filling layer 107, the first filling layer 107 is located in the first groove, the first filling layer 107 is located on the side of the first film layer 103 and the third film layer 105, and the first filling layer 107 is located on the top surface of the second sacrificial layer 102, the top surface and bottom surface of the second film layer 104, and the top surface and bottom surface of the fourth film layer 106. The material of the first filling layer 107 includes silicon dioxide.

[0096] refer to Fig.17 , a fourth sacrificial layer 108 is formed, and the fourth sacrificial layer 108 fills the first groove. The material of the fourth sacrificial layer 108 is a low-K material.

[0097] refer to Fig.18 , a portion of the width of the second film layer 104 is removed to form second grooves 172 arranged at intervals, and the width of the second grooves 172 is smaller than the width of the first grooves.

[0098] refer to Fig.18 , a first conductive film 109 is formed, and the first conductive film 109 fills the second groove.

[0099] In some embodiments, the material of the first conductive film 109 includes a metal material of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), tungsten (W) or an alloy thereof.

[0100] refer to Fig.19 , patterning the first film layer 103, the second film layer 104, the third film layer 105, the fourth film layer 106 and the second sacrificial layer 102 to form a third groove 173, wherein the third groove 173 does not overlap with the first groove, that is, the inner wall of the third groove 143 exposes the side surfaces of the first film layer 103 and the third film layer 105.

[0101] Continue to refer Fig.19 , the second film layer is removed along the third groove 173 to form a fourth groove 174 that intersects the third groove 173 .

[0102] refer to Fig. 20, forming a first semiconductor film 111, the first semiconductor film 111 is located on the inner wall surface and the bottom of the third groove 173 and the inner wall surface of the fourth groove 174. The first semiconductor film 111 is also located on the side surface of the second sacrificial layer 102, the side surface of the first film layer 103, the top surface and the bottom surface of the first filling layer 107, the side surface of the first conductive film 109, the side surface of the third film layer 105 and the side surface of the fourth film layer 106.

[0103] In some embodiments, the first semiconductor film 111 is used for subsequently preparing the first semiconductor layer 130. The material of the first semiconductor film includes semiconductor material and amorphous material.

[0104] refer to Fig. 20 , a sixth sacrificial layer 112 is formed, and the sixth sacrificial layer 112 fills the third groove and the fourth groove.

[0105] Continue to refer Fig. 20 , remove the first semiconductor film 111 and the sixth sacrificial layer 112 located in the third groove 173 , and retain the first semiconductor film 111 and the sixth sacrificial layer 112 located in the fourth groove.

[0106] Continue to refer Fig. 20 , the sixth sacrificial layer 112 located in the fourth groove 174 is thinned along the third groove 173 .

[0107] refer to Fig.21 , forming a first isolation layer 113 , the first isolation layer 113 fills the inner wall surface and the bottom of the fourth groove and the third groove 173 , and the first isolation layer 113 is located between the first semiconductor films 111 .

[0108] Continue to refer Fig.21 , remove the first isolation layer 113 located in the third groove and thin the first isolation layer 113 located in the fourth groove.

[0109] Continue to refer Fig.21 , forming a second conductive film 114 , the second conductive film 114 fills the inner wall surface and the bottom of the fourth groove and the third groove 173 , and the second conductive film 114 is located between the first semiconductor films 111 .

[0110] Continue to refer Fig.21 , remove the second conductive film 114 located in the third groove 173 .

[0111] refer to Fig. 22 , the first film layer 103 , the third film layer 105 and a portion of the first filling layer 107 are removed along the third groove 173 until the side surface of the fourth sacrificial layer 108 is exposed.

[0112] refer to Fig. 22, the fourth film layer and a portion of the second sacrificial layer 102 are removed along the third groove 173 to form a fifth groove 175 , and an overlapping area exists between the fifth groove 175 and the second groove.

[0113] refer to Fig.23 , forming a first gate dielectric layer 115 on the surfaces of the film layers exposed by the fifth groove 173 and the third groove 173 ,

[0114] In some embodiments, a first isolation film is formed on the side of the second sacrificial layer 102, the top of the first sacrificial layer 101, the side of the first filling layer 107, the side of the fourth sacrificial layer, the side of the second conductive film, the side, part of the bottom surface and part of the top surface of the first semiconductor, and the side of the fourth film layer.

[0115] refer to Fig.23 , a second semiconductor film 116 is formed on the surface of the first isolation layer.

[0116] refer to Fig.23 , a sixth sacrificial layer 117 is formed, and the sixth sacrificial layer fills the fifth groove and the third groove.

[0117] refer to Fig.24 , remove the fourth sacrificial layer to expose the side surface of the first gate dielectric layer 115.

[0118] Continue to refer Fig.24 , remove the partially exposed first gate dielectric layer 115 until the side of the second semiconductor film 116 is exposed. Fig.24 , a third conductive film 118 is formed, the third conductive film 118 is located between the first filling layers 107, and the third conductive film 118 is in electrical contact with the second semiconductor film 116.

[0119] refer to Fig.25 , remove the fourth film layer and remove the exposed first gate dielectric layer 115 and the second semiconductor film 116 until the side surface of the sixth sacrificial layer 117 is exposed.

[0120] refer to Fig.25 , forming a second filling layer 119 , the second filling layer 119 is located on the side of the sixth sacrificial layer 117 and between the adjacent first filling layers 107 .

[0121] refer to Fig.26 as well as Fig. 27 , patterning the sixth sacrificial layer 117 until the surface of the first sacrificial layer 101 is exposed and a sixth groove 120 is formed. The extension direction of the sixth groove 120 is different from that of the first groove. The sixth groove 120 does not run through the length of the semiconductor structure, that is, the first conductive film 109 and the second conductive film 114 are still retained on opposite sides of the sixth groove 120.

[0122] refer to Fig.28 , the remaining second semiconductor film serves as the first semiconductor layer 130, part of the remaining second conductive film serves as the read bit line 121, and part of the remaining second conductive film serves as the read word line 122, the remaining first semiconductor film serves as the second semiconductor layer 140, the remaining second conductive film serves as the first gate electrode 133, the remaining first conductive film serves as the write bit line 123, and the remaining 115 serves as the first gate dielectric layer.

[0123] refer to Fig.29 , remove 112 along the sixth groove and form a seventh groove, and then form a second gate dielectric layer 125 and a fourth conductive film 126, the fourth conductive film 126 fills the sixth groove and the seventh groove, and the second gate dielectric layer 125 is located between the fourth conductive film 126 and the second semiconductor layer 140.

[0124] refer to Fig.30 as well as Fig.31 , patterning the second gate dielectric layer 125 and the fourth conductive film 126 located in the sixth groove, and retaining the second gate dielectric layer 125 and the fourth conductive film 126 located in the sixth groove and facing the seventh groove.

[0125] refer to Fig.30 as well as Fig.31 , an eighth filling layer 127 is formed, and the eighth filling layer 127 fills the sixth groove.

[0126] refer to Fig.30 as well as Fig.31 , the fourth conductive film 126 located in the sixth groove is patterned, and the remaining fourth conductive film 126 located in the seventh groove is used as the second gate 143, and the fourth conductive film 126 located in the sixth groove is used as the write line 124.

[0127] refer to Fig.30 as well as Fig.31 , forming a third isolation layer 128, wherein the third isolation layer 128 is located between the two write word lines 124.

[0128] refer to Figure 8 to Figure 11 , forming a first contact structure 151, a second contact structure 152 and a third contact structure 153, the first contact structure 151, the second contact structure 152 and the third contact structure 153 are respectively electrically contacted with the read bit line 121, the read word line 122 and the write bit line 123; at least three of the first contact structure 151, the second contact structure 152, the third contact structure 153, the read bit line 121, the read word line 122 and the write bit line 123 have overlapping orthographic projections on the substrate 100.

[0129] In some embodiments, the method further includes forming an isolation layer 154 , the isolation layer being located between the second contact structure 152 and the read bit line 121 , between the second contact structure 152 and the write bit line 123 , and between the third contact structure and the read bit line 121 .

[0130] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; a first transistor located on the substrate, the first transistor comprising a first semiconductor layer, a first gate, a read bit line and a read word line, the first semiconductor layer comprising a first end and a second end opposite to each other in a first direction, the read bit line being in electrical contact with the first end, and the read word line being in electrical contact with the second end; a second transistor, the second transistor is located at one side of the first semiconductor layer along the second direction; the second transistor comprises a second semiconductor layer, a second gate, a write bit line and a write word line, the second gate is located at one side of the second semiconductor layer along the first direction, the write word line is electrically in contact with one side of the second gate along the third direction; the second semiconductor layer comprises a third end and a fourth end opposite to each other along the second direction, the first gate is electrically in contact with the third end, and the write bit line is electrically in contact with the fourth end; the first direction, the second direction and the third direction intersect each other; At least two of the read bit line, the read word line and the write bit line overlap in their orthographic projections on the substrate.

2. The semiconductor structure according to claim 1, characterized in that: Also includes: A first contact structure, a second contact structure and a third contact structure, wherein the first contact structure, the second contact structure and the third contact structure are electrically contacted with the read bit line, the read word line and the write bit line respectively; at least three of the first contact structure, the second contact structure, the third contact structure, the read bit line, the read word line and the write bit line overlap with each other in their orthographic projection on the substrate.

3. The semiconductor structure according to claim 2, characterized in that: Any one of the read bit line, the read word line or the write bit line has a protrusion, and one of the first contact structure, the second contact structure or the third contact structure is in electrical contact with the protrusion; or, Any two of the read bit line, the read word line or the write bit line respectively have a first protrusion and a second protrusion, and two of the first contact structure, the second contact structure or the third contact structure are respectively in electrical contact with the first protrusion or the second protrusion; the orthographic projections of the first protrusion and the second protrusion on the substrate do not overlap; or, The read bit line, the read word line or the write bit line respectively has a first protrusion, a second protrusion and a third protrusion, and the first contact structure, the second contact structure or the third contact structure are respectively electrically contacted with the first protrusion, the second protrusion and the third protrusion; the first protrusion, the second protrusion and the third protrusion do not overlap between the orthographic projections of the substrate.

4. The semiconductor structure according to claim 2, characterized in that: The first contact structure is in electrical contact with the read bit line, the second contact structure penetrates through the thickness of the read bit line and is in electrical contact with the read word line, and the third contact structure penetrates through the thickness of the read bit line and is in electrical contact with the write bit line; and also includes: an isolation layer, the isolation layer is located between the second contact structure and the read bit line, between the second contact structure and the write bit line, and between the third contact and the read bit line.

5. The semiconductor structure according to claim 1, characterized in that: The second semiconductor layer includes: a first doped region, a first channel region, a second doped region, a second channel region and a third doped region arranged in sequence, the second semiconductor layer surrounds the second gate, the first gate is electrically in contact with the first doped region and the third doped region, and the write bit line is electrically in contact with the second doped region.

6. A memory array structure, comprising the semiconductor structure according to any one of claims 1 to 5, characterized in that: A plurality of the semiconductor structures are arranged in an array along the third direction and along the first direction, the read bit line is electrically connected to the first ends of the plurality of the first semiconductor layers arranged along the third direction, and the read word line is electrically connected to the second ends of the plurality of the first semiconductor layers arranged along the third direction; the second transistor is located on one side of the first semiconductor layer of the corresponding first transistor along the second direction; the write word line is electrically connected to the plurality of the second gates arranged along the first direction, and the write bit line is electrically connected to the fourth ends of the plurality of the second semiconductor layers arranged along the third direction; Orthographic projections of at least two of the read bit lines on the substrate overlap; and / or, at least two of the read word lines have overlapping orthographic projections on the substrate; And / or, orthographic projections of at least two of the write bit lines on the substrate overlap.

7. The storage array structure according to claim 6, characterized in that: Also includes: a plurality of first contact structures arranged along a fourth direction, wherein the first contact structures are in electrical contact with the read bit lines; a plurality of second contact structures along a fifth direction, wherein the second contact structures are in electrical contact with the read word lines; A plurality of third contact structures are arranged along a sixth direction, wherein the third contact structures are in electrical contact with the write bit lines; and at least one of the fourth direction, the fifth direction and the sixth direction is the same as the third direction.

8. The storage array structure according to claim 7, characterized in that: A portion of the first contact structure penetrates the thickness of the read word line and the thickness of the write bit line and is in electrical contact with the read bit line; further comprising: an isolation layer, the isolation layer being located between the first contact structure and the write bit line and between the first contact structure and the read word line; and / or, Part of the second contact structure penetrates the thickness of the read bit line and the thickness of the write bit line and is in electrical contact with the read word line; an isolation layer is located between the second contact structure and the write bit line and between the second contact structure and the read bit line; and / or, The third contact structure penetrates through the thickness of the read bit line and the thickness of the read word line and contacts the write bit line; the isolation layer is located between the third contact structure and the read word line and between the third contact structure and the read bit line.

9. The storage array structure according to claim 8, characterized in that: The end of the read bit line away from the first semiconductor layer has a first protrusion, a plurality of the first protrusions are arranged at intervals along the fourth direction, and the first contact structure is in electrical contact with the first protrusion; and / or, The read word line has a second protrusion on a side away from the first semiconductor layer, a plurality of the second protrusions are arranged at intervals along the fifth direction, and the second contact structure is in electrical contact with the second protrusion; and / or, The write bit line has a third protrusion on a side away from the first semiconductor layer. A plurality of the third protrusions are arranged at intervals along the sixth direction, and the third contact structure is in electrical contact with the third protrusions.

10. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a first transistor, the first transistor being located on the substrate, the first transistor comprising a first semiconductor layer, a first gate, a read bit line and a read word line, the first semiconductor layer comprising a first end and a second end opposite to each other in a first direction, the read bit line being in electrical contact with the first end, and the read word line being in electrical contact with the second end; A second transistor is formed, wherein the second transistor is located at one side of the first semiconductor layer along the second direction; the second transistor comprises a second semiconductor layer, a second gate, a write bit line and a write word line, the second gate is located at one side of the second semiconductor layer along the first direction, and the write word line is electrically in contact with one side of the second gate along the third direction; the second semiconductor layer comprises a third end and a fourth end opposite to each other along the second direction, the first gate is electrically in contact with the third end, and the write bit line is electrically in contact with the fourth end; the first direction, the second direction and the third direction intersect each other; At least two of the read bit line, the read word line and the write bit line overlap in their orthographic projections on the substrate.

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