Gradient-doped separated trench gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a gradient-doped separated trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: carrying out the epitaxial growth on the upper side surface of a silicon carbide substrate with a drain metal layer, and sequentially forming a drift layer, a first N-type region and a second N-type region; a barrier layer is formed, etching and ion implantation are carried out, and a P-type well region and an N-type source region are formed; a barrier layer is formed again, and a first insulation region is formed through etching and deposition; forming a barrier layer again, etching and depositing metal, and forming a second gate metal layer; a barrier layer is formed again, a second insulating region is formed through etching and deposition, and the insulating dielectric layer comprises a first insulating region and a second insulating region; forming a barrier layer again, etching and depositing metal, and forming a first gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a source metal layer; the voltage endurance capability of the device is improved, the gate-drain capacitance of the device is reduced, the switching speed of the device is improved, and the switching loss of the device is reduced.

Description

Technical Field

[0001] The invention relates to a gradient-doped separated trench gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion, etc. For silicon carbide power VDMOS, the requirements for device performance in different fields have different emphases, but the overall requirements are lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, etc.), and lower body diode conduction loss. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a gradient-doped separated trench gate silicon carbide VDMOS and a preparation method, which improves the device's voltage resistance without affecting the device's on-resistance, reduces the device's gate-drain capacitance, increases the device's switching speed, and reduces the device's switching loss.

[0004] In a first aspect, the present invention provides a method for preparing a gradient-doped separated trench gate silicon carbide VDMOS, comprising the following steps: Step 1: epitaxially grow a drift layer on the side of the silicon carbide substrate with the drain metal layer; Step 2, epitaxially growing on the drift layer to form a first N-type region; Step 3, epitaxially growing on the first N-type region to form a second N-type region; Step 4, forming a barrier layer on the second N-type region, etching the barrier layer to form a through hole, and implanting ions to form a P-type well region; Step 5, removing the original barrier layer, forming a barrier layer on the second N-type region, etching the barrier layer to form a through hole, and implanting ions to form an N-type source region; Step 6, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the second N-type region and the first N-type region until the upper side of the drift layer, and depositing to form a first insulating region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the first insulating region, depositing metal, and forming a second gate metal layer; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a second insulating region, wherein the insulating dielectric layer includes the first insulating region and the second insulating region; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the second insulating region to form a groove, depositing metal, and forming a first gate metal layer; Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the second N-type region to the upper side of the P-type well region, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0005] In a second aspect, the present invention provides a gradient-doped separated trench gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a gradient-doped separated trench gate silicon carbide VDMOS according to the first aspect.

[0006] The advantages of the present invention are: 1. The present invention constructs a first gate metal layer and a second gate metal layer inside the device, which can effectively reduce the resistivity inside the device and reduce the on-resistance of the device; Second, the present invention constructs a first N-type region and a second N-type region on the upper part of the drift layer to achieve gradient doping; when the device is turned off, the voltage from the drain of the device is distributed in the first N-type region and the second N-type region, thereby improving the withstand voltage of the device; and the doping concentration of the first N-type region and the second N-type region is higher than that of the drift layer, so that the current can be distributed to the edge of the device to avoid current concentration inside the device; 3. The first gate metal layer and the second gate metal layer of the present invention can partially shield the gate-drain capacitance (i.e., the Maitreya capacitance), thereby reducing the Maitreya capacitance of the device and improving the switching speed of the device; Fourth, the P-type well region of the present invention forms an ohmic contact with the source metal layer, and no additional P-type source region process is required, thereby reducing process costs; 5. The present invention adopts multiple epitaxial processes, which can reduce the process difficulty, improve the quality of the device gate structure, reduce the defect density, and improve the device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0008] Figure 1 The schematic diagram of a gradient-doped separated trench-gate silicon carbide VDMOS of the present invention is shown.

[0009] Figure 2 The process section of the gradient doped separated trench gate silicon carbide VDMOS of the present invention is shown in FIG. Figure 1 .

[0010] Figure 3 The process section of the gradient doped separated trench gate silicon carbide VDMOS of the present invention is shown in FIG. Figure 2 .

[0011] Figure 4 The process section of the gradient doped separated trench gate silicon carbide VDMOS of the present invention is shown in FIG. Figure 3 .

[0012] Figure 5 The process section of the gradient doped separated trench gate silicon carbide VDMOS of the present invention is shown in FIG. Figure 4 .

[0013] Figure 6 The process section of the gradient doped separated trench gate silicon carbide VDMOS of the present invention is shown in FIG. Figure 5 .

[0014] Figure 7 The process section of the gradient doped separated trench gate silicon carbide VDMOS of the present invention is shown in FIG. Figure 6 .

[0015] Figure 8 The process section of the gradient doped separated trench gate silicon carbide VDMOS of the present invention is shown in FIG. Figure 7 .

[0016] Fig. 9 The process section of the gradient doped separated trench gate silicon carbide VDMOS of the present invention is shown in FIG. Figure 8 .

[0017] Fig.10 The process section of the gradient doped separated trench gate silicon carbide VDMOS of the present invention is shown in FIG. Figure 9 .

[0018] Fig.11 The process section of the gradient doped separated trench gate silicon carbide VDMOS of the present invention is shown in FIG. Figure 10 .

[0019] Fig.12 The process section of the gradient doped separated trench gate silicon carbide VDMOS of the present invention is shown in FIG. Figure 10 one.

[0020] Fig.13 The process section of the gradient doped separated trench gate silicon carbide VDMOS of the present invention is shown in FIG. Figure 10 two.

[0021] Fig.14 The process section of the gradient doped separated trench gate silicon carbide VDMOS of the present invention is shown in FIG. Figure 10 three.

[0022] Fig.15 The process section of the gradient doped separated trench gate silicon carbide VDMOS of the present invention is shown in FIG. Figure 10 Four. DETAILED DESCRIPTION

[0023] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0025] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0026] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0027] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0028] like Figures 1 to 15 As shown, the embodiment of the present application provides a method for preparing a gradient-doped separated trench gate silicon carbide VDMOS, comprising the following steps: Step 1: epitaxially grow a drift layer 102 on the silicon carbide substrate 101 having the drain metal layer 109; Step 2: epitaxially grow the first N-type region 103 on the drift layer 102; Step 3, epitaxially growing on the first N-type region 103 to form a second N-type region 104; Step 4, forming a barrier layer 110 on the second N-type region 104, etching the barrier layer 110 to form a through hole, and implanting ions to form a P-type well region 105, wherein the ion implantation energy is 70-230kev; Step 5, removing the original barrier layer 110, forming a barrier layer 110 on the second N-type region 104, etching the barrier layer 110 to form a through hole, and ion implantation to form an N-type source region 1051, the ion implantation energy is 70-170kev; Step 6, removing the original barrier layer 110, re-forming the barrier layer 110, etching the barrier layer 110 to form a through hole, etching the second N-type region 104 and the first N-type region 103 until the upper side of the drift layer 102, and depositing to form a first insulating region 1063; Step 7, removing the original barrier layer 110, re-forming the barrier layer 110, etching the barrier layer 110 to form a through hole, etching the first insulating region 1063, depositing metal, and forming a second gate metal layer 1061; Step 8, removing the original barrier layer 110, re-forming the barrier layer 110, etching the barrier layer 110 to form a through hole, and depositing to form a second insulating region 1064, the insulating dielectric layer 106 includes a first insulating region 1063 and a second insulating region 1064; Step 9, removing the original barrier layer 110, re-forming the barrier layer 110, etching the barrier layer 110 to form a through hole, etching the second insulating region 1064 to form a groove 1062, depositing metal to form a first gate metal layer 107; Step 10, remove the original barrier layer 110, re-form the barrier layer 110, etch the barrier layer 110 to form a through hole, and etch the second N-type region 104 to the upper side of the P-type well region 105, deposit metal to form a source metal layer 108, remove the barrier layer 110, and complete the preparation.

[0029] In this embodiment, preferably, the bottom of the trench 1062 and the upper side of the second N-type region 104 are located in the same plane.

[0030] In this embodiment, preferably, the thickness of the second gate metal layer 1061 is 2-6 μm.

[0031] In this embodiment, preferably, the doping concentration of the first N-type region 103 is greater than the doping concentration of the drift layer 102 ; the doping concentration of the second N-type region 104 is greater than the doping concentration of the first N-type region 103 ; and the doping concentration of the P-type well region 105 is greater than the doping concentration of the second N-type region 104 .

[0032] In this embodiment, preferably, the thickness of the first N-type region 103 is greater than or equal to the thickness of the second N-type region 104 .

[0033] In this embodiment, preferably, the distance between the upper side of the second gate metal layer 1061 and the lower side of the first gate metal layer 107 is smaller than the distance between the lower side of the second gate metal layer 1061 and the upper side of the drift layer 102 .

[0034] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 101; A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101; A first N-type region 103 , wherein a lower side of the first N-type region 103 is connected to the drift layer 102 ; A second N-type region 104 , wherein a lower side of the second N-type region 104 is connected to an upper side of the first N-type region 103 ; A P-type well region 105, wherein the lower side of the P-type well region 105 is connected to the upper side of the second N-type region 104; an N-type source region 1051 is disposed in the P-type well region 105; an insulating dielectric layer 106, wherein the insulating dielectric layer 106 sequentially passes through the N-type source region 1051, the P-type well region 105, the second N-type region 104 and the first N-type region 103, and the lower side of the insulating dielectric layer 106 is connected to the upper side of the drift layer 102; a second gate metal layer 1061 and a trench 1062 are provided in the insulating dielectric layer 106, and the second gate metal layer 1061 is located below the trench 1062; A first gate metal layer 107, wherein the first gate metal layer 107 is disposed in the trench 1062; A source metal layer 108 , wherein the source metal layer 108 is connected to the P-type well region 105 and the N-type source region 1051 ; and a drain metal layer 109 , wherein the drain metal layer 109 is connected to the lower side of the silicon carbide substrate 101 .

[0035] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 101 is 1-5e18cm -3 , the doping concentration of the N-type drift layer 102 is 1-5e16cm -3 , the doping concentration of the first N-type region 103 is 1-5e17cm -3 , the doping concentration of the second N-type region 104 is 1-3e18cm -3 , the doping concentration of the P-type well region 105 is 0.8-1.2e19 cm -3 , the doping concentration of the N-type source region 1051 is 1-5e18cm -3 The material of the insulating dielectric layer 106 may be one or a combination of silicon dioxide, aluminum nitride, and hafnium dioxide; The doping concentration of the N-type silicon carbide substrate 101 is to ensure the formation of low-resistance ohmic contact with the drain metal layer 109, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 102 is a compromise between the reverse withstand voltage and the on-resistance of the device; the first N-type region 103 and the second N-type region 104 are to form a concentration gradient with the N-type drift layer 102, thereby achieving a trapezoidal distribution of the drain positive voltage in the N-type drift layer 102, the first N-type region 103, and the second N-type region 104, thereby improving the withstand voltage capability of the device; The doping concentration of the P-type well region 105 has two functions: one is to form a P-type turn-off region from the N-type source region 1051 to the second N-type region 104, to achieve turn-off and voltage resistance under zero gate voltage conditions; the other is to form a low-resistance ohmic contact with the source metal layer 108, to form a parasitic body diode of the device, to complete the freewheeling when the device is not turned on, and the N-type source region 1051 is to ensure ohmic contact with the source metal layer 108 and to provide electrons when a conductive channel is formed when the device is turned on.

[0036] The thickness of the N-type silicon carbide substrate 101 of the device is 500-800nm, which is to ensure the support of the subsequent structure preparation of the device; the thickness of the N-type drift layer 102 is 10-15μm, which is adjusted within the above range according to the different requirements for the withstand voltage characteristics of the device; the thickness of the first N-type region 103 is 3-6μm, and the thickness of the second N-type region 104 is 1-3μm, which is to form a concentration gradient and improve the withstand voltage capability of the device. The lower side of the device insulating dielectric layer 106 is flush with the lower side of the first N-type region 103, and the lower side of the second gate metal layer 1061 is 2μm away from the insulating dielectric layer 106. This is for the second gate metal layer 1061 to resist drain voltage impact. The thickness of the second gate metal layer 1061 is 2-6μm. The lower side of the second gate metal layer 1061 is 1μm higher than the upper side of the first N-type region 103. This is to achieve the control of the second gate metal layer 1061 by the first gate metal layer 107. The lower side of the first gate metal layer 107 of the device is flush with the lower side of the P-type well region 105 to ensure the gate control ability of the device. The thickness of the P-type well region 105 is 500nm, the thickness of the N-type source region 1051 is 300nm, and the thickness of the source metal layer 108 is 200nm. A first gate metal layer 107 and a second gate metal layer 1061 are constructed inside the device. The first gate metal layer 107 effectively controls the inversion of the device's P-type well region 105 to form a conductive channel. The second gate metal layer 1061 can increase the electron concentration, thereby reducing the on-resistance of the device. There is an insulating medium with a thickness of 2μm between the second gate metal layer 1061 and the drift layer 102, which can effectively suppress the gate-drain capacitance (Miller capacitance). Reducing the Maitreya capacitance of the device can effectively increase the switching speed of the device. A first N-type region 103 and a second N-type region 104 are constructed on the upper part of the N-type drift layer 102 inside the device to realize gradient doping, which has two functions: first, when the device is turned off, the voltage from the device drain is divided into the N-type drift layer 102, the first N-type region 103 and the second N-type region 104 for trapezoidal distribution, thereby improving the withstand voltage of the device; second, the doping concentration of the first N-type region 103 and the second N-type region 104 is higher than that of the N-type drift layer 102, which can distribute the current to the edge of the device to avoid current concentration inside the device; The P-type well region 105 constructed by the device can form an ohmic contact with the source metal layer 108, and no additional P-type source region process is required, thereby reducing the process cost; The device structure adopts multiple epitaxial processes, which can reduce the difficulty of thick epitaxy, improve the quality of the device gate structure, reduce defect density, and improve device reliability.

[0037] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a gradient doped separated trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: epitaxially grow a drift layer on the silicon carbide substrate with a drain metal layer; Step 2, epitaxially growing on the drift layer to form a first N-type region; Step 3, epitaxially growing on the first N-type region to form a second N-type region; Step 4, forming a barrier layer on the second N-type region, etching the barrier layer to form a through hole, and implanting ions to form a P-type well region; Step 5, removing the original barrier layer, forming a barrier layer on the second N-type region, etching the barrier layer to form a through hole, and implanting ions to form an N-type source region; Step 6, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the second N-type region and the first N-type region until the upper side of the drift layer, and depositing to form a first insulating region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the first insulating region, depositing metal, and forming a second gate metal layer; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a second insulating region, wherein the insulating dielectric layer includes the first insulating region and the second insulating region; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the second insulating region to form a groove, depositing metal, and forming a first gate metal layer; Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the second N-type region to the upper side of the P-type well region, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a gradient doped separated trench gate silicon carbide VDMOS according to claim 1, characterized in that: The bottom of the trench and the upper side of the second N-type region are located in the same plane.

3. The method for preparing a gradient doped separated trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the second gate metal layer is 2-6 μm.

4. The method for preparing a gradient doped separated trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the first N-type region is greater than the doping concentration of the drift layer; the doping concentration of the second N-type region is greater than the doping concentration of the first N-type region; and the doping concentration of the P-type well region is greater than the doping concentration of the second N-type region.

5. The method for preparing a gradient doped separated trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the first N-type region is greater than or equal to the thickness of the second N-type region.

6. The method for preparing a gradient doped separated trench gate silicon carbide VDMOS according to claim 1, characterized in that: The distance between the upper side of the second gate metal layer and the lower side of the first gate metal layer is smaller than the distance between the lower side of the second gate metal layer and the upper side of the drift layer.

7. A gradient doped separated trench gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 6.

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