Chain type semiconductor device and manufacturing method thereof

Abstract

The invention discloses a chain-type semiconductor device and a manufacturing method thereof, and relates to a power semiconductor device, more than one section of chain-type groove and an insulating oxide layer arranged above the chain-type groove are distributed on the upper surface of a semiconductor of the device, and a first contact hole and a second contact hole are formed in the insulating oxide layer; the chain-type groove comprises a first-type groove and a second-type groove, the first-type groove is provided with a gate electrode and a shield gate electrode, the shield gate electrode is connected to the source electrode through a second contact hole, the second-type groove is provided with a gate electrode, and the gate electrodes in the first-type groove and the second-type groove are connected; a second conductive type dopant region and a first conductive type heavily doped source region are arranged between the first type of grooves and are connected to the source electrode through a first contact hole. According to the invention, a chain-type groove structure is adopted, so that lower turn-on resistance, smaller groove density and better switching performance can be realized compared with a device with an existing structure.

Description

Technical Field

[0001] The invention relates to a power semiconductor device, in particular to a chain-type semiconductor device and a manufacturing method thereof. Background Art

[0002] An existing structure of an N-type shielded gate trench field effect transistor is as follows Figure 1 As shown, the left figure is a top view of the semiconductor trench and contact hole trench structure, and the right figure is a schematic cross-sectional view of the structure. The device structure includes multiple parallel cell trenches 101 in an N-type semiconductor, and the trenches are filled with a gate electrode 102 located above and a shielding gate electrode 103 located below, wherein the gate electrode 102 and the corresponding trench sidewall are isolated by a gate oxide layer; the shielding gate electrode 103 and the corresponding trench sidewall are isolated by a trench oxide layer; and the gate electrode 102 and the shielding gate electrode 103 are isolated by an inter-electrode isolation oxide layer. There are P-doped body regions 108 and N-doped body regions 108 on the upper surface of the semiconductor between the cell trenches 101. + Doped source region 109. N + The doped source region 109 is connected to the source metal 120 located on the upper surface of the device through the contact hole 104 on the oxide dielectric layer 117; the shielded gate electrode 103 is connected to the source metal located on the upper surface of the device through the contact hole on the oxide dielectric layer 117. In the above structure, the cell trenches are parallel to each other. When the device is reverse biased, the shielded gate electrode in the trench provides a horizontal electric field to the N-type semiconductor within the range a1 between the trenches, so that the charge balance is achieved in the N-type semiconductor, thereby improving the breakdown voltage of the device.

[0003] On this basis, an improved N-type shielded gate trench field effect transistor with an existing structure is provided. Figure 2 As shown, the left figure is a top view of the semiconductor trench and contact hole trench structure, and the right figure is a cross-sectional schematic diagram of the structure. The structure has a cell trench 201 of an independent columnar structure, and a mesh gate electrode trench 202 surrounding the cell trench, and there is a contact hole 204 surrounding the cell trench between the gate electrode trench 202 and the cell trench 201. Figure 1 The traditional structure of the structure has a low trench-semiconductor area ratio. When reverse biased, the columnar cell trench provides a horizontal electric field to the surrounding N-type semiconductor, which can ensure the charge balance of the N semiconductor within the range of a2 and b2. Therefore, it can increase the semiconductor's conduction area, reduce the on-resistance, and ensure the device's breakdown voltage. At the same time, this structure can improve Figure 1 The wafer warpage problem caused by the horizontally arranged deep grooves in the structure, but Figure 2The structure requires a gate electrode trench 202 to be set between the cell trenches and two contact holes 204, thus limiting the distance (a2 / b2) between the cell trenches, which is not conducive to reducing the cell size of the device, thereby limiting the further reduction of the on-resistance. In addition, the narrower gate electrode trench 202 will increase the gate transmission resistance of the device, affecting the uniformity of the switching speed between cells. Summary of the invention

[0004] In order to solve the above-mentioned problems, the present invention proposes the following technical solutions:

[0005] The first object of the present invention is to provide a chain-type semiconductor device, the device comprising a first conductive substrate layer at the bottom, an epitaxial layer above the first conductive substrate layer, and a source electrode located on the upper surface of the device; the upper surface of the semiconductor is provided with more than one chain-type groove and an insulating oxide layer arranged above the chain-type groove, and the insulating oxide layer is provided with a first contact hole and a second contact hole;

[0006] The chain-type grooves include a first type of groove and a second type of groove connected to the first type of groove and narrower and shallower than the first type of groove. The first type of groove is provided with a gate electrode and a shielding gate electrode separated from the gate electrode. The shielding gate electrode is connected to the source through a second contact hole provided thereon. The second type of groove is provided with a gate electrode. The first type of groove and the gate electrode in the second type of groove are connected. A second conductive type doped body region and a first conductive type heavily doped source region are provided between the first type of grooves. The second conductive type doped body region and the first conductive type heavily doped source region are connected to the source through a first contact hole.

[0007] Furthermore, the upper surface opening of the first type of groove is circular or regular polygonal, and the bottom is a smooth arc surface, which includes a shielding gate electrode arranged in the middle of the groove and a gate electrode surrounding the shielding gate electrode, and / or the second type of groove is a straight groove.

[0008] Furthermore, the gate electrode in the first type of trench is provided with a gate electrode notch, and the gate electrode notch is provided with a second contact hole, which respectively connects the shielding gate electrode in the first type of trench, the semiconductor region outside the gate electrode notch, and the source electrode.

[0009] Furthermore, the spacing between adjacent non-connected first-type grooves is equal to the spacing between adjacent connected first-type grooves.

[0010] Furthermore, the isolation layer between the shielding gate electrode and the trench sidewall is thin on the top and thick on the bottom.

[0011] Furthermore, the epitaxial layer includes a first epitaxial layer located above the first conductive substrate layer and a second epitaxial layer located on the first epitaxial layer, and the doping concentration of the second epitaxial layer is lower than the doping concentration of the first epitaxial layer.

[0012] Furthermore, the first contact holes are long straight grooves evenly distributed in the device, or the first contact holes are strip structures surrounding the chain-shaped grooves;

[0013] And / or the ratio of the minimum width of the first contact hole to the minimum width of the second contact hole is less than 3:1.

[0014] Furthermore, the first contact holes include first direction contact holes parallel to the chain-shaped grooves and second direction contact holes perpendicular to the first direction contact holes.

[0015] Furthermore, the first contact hole is a long straight groove, and the first contact hole includes a long contact hole and a short contact hole parallel to the chain-shaped groove, wherein the long contact hole is equidistant from the chain-shaped grooves on both sides thereof, and the short contact holes are evenly distributed on both sides of the second type of groove.

[0016] Furthermore, a third type of trench is provided at the device breakdown weak point between adjacent trench chain structures.

[0017] Furthermore, the chain-shaped grooves are evenly arranged in a straight line, S-shape, U-shape or cross-shape in the device.

[0018] A second object of the present invention is to provide a method for manufacturing a chain-type semiconductor device, the method comprising the following steps:

[0019] The first step is to form a hard mask layer on the upper surface of the first conductive type semiconductor, perform photolithography on the hard mask layer to form a hard mask opening, and etch the first type of trench, the second type of trench, and the third type of trench at the hard mask opening;

[0020] Step 2: forming a shielding gate isolation layer in the first type of trench, wherein the shielding gate isolation layer material completely fills the second type of trench and the third type of trench;

[0021] The third step is to fill the shielding grid material in the first type of trench;

[0022] The fourth step is to perform chemical mechanical polishing, where the polishing stops on the hard mask layer on the upper surface of the semiconductor;

[0023] The fifth step is to perform photolithography under the protection of photoresist to etch a portion of the shielding gate isolation layer above the first type of trench and adjacent to the trench, as well as the shielding gate isolation layer above the second type of trench; after etching, the remaining shielding gate isolation layer above the first type of trench serves as an inter-electrode isolation layer of the device;

[0024] Step 6, forming a gate oxide layer and a gate electrode in the first type of trench and the second type of trench;

[0025] The seventh step is to form a second conductivity type doped body region and a first conductivity type heavily doped source region, to form an insulating oxide layer located above the semiconductor, and then to form a contact hole in the insulating oxide layer, and finally to form an upper surface metal and finally to form a device.

[0026] In the fifth step, photolithography is first performed, and then the shielding gate isolation layer above the first type of trench and the second type of trench is etched; after etching, the shielding gate isolation layer above the first type of trench is removed, and the side wall of the shielding gate electrode in the trench is exposed;

[0027] In the sixth step, thermal oxidation is performed to form a gate oxide layer between the trenches and the semiconductor trenches, and to form an inter-electrode isolation layer between the gate electrode and the shielding gate electrode in the first type of trenches.

[0028] The present invention adopts a chain-type groove structure, which can achieve lower on-resistance and smaller groove density than existing structural devices, and better switching performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1-2 The present invention is a top view and a cross-sectional schematic diagram of the structure of the trench and contact hole of an existing shielded gate trench field effect transistor device.

[0030] Figure 3 A is a top view of the structure of the trench and contact hole of an embodiment of the device of the present invention.

[0031] Figure 3 B-3D Figure 3 A is a schematic cross-sectional view of different positions of the embodiment described.

[0032] Figure 4 A-4B are top views of the structures of the grooves of different embodiments of the device of the present invention.

[0033] Figure 5 A-5D are top views of the structures of the trenches and contact holes of different embodiments of the device of the present invention.

[0034] Figure 6-Figure 12 The cross-sectional schematic diagram is a key step of the manufacturing process of an embodiment of the device of the present invention.

[0035] Fig.13 A-13B is a cross-sectional schematic diagram of key steps of the manufacturing process of another embodiment of the device of the present invention. DETAILED DESCRIPTION

[0036] It should be noted that the corresponding position words described in this document, such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", and "vertical", correspond to the relative positions of the reference diagrams. In the specific implementation, there is no restriction on fixed directions. It should be noted that the devices in the drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and trenches in the drawings, and the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0037] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that in the following description of the shielded gate trench field effect transistor device and its manufacturing method of the present invention, the semiconductor substrate of the shielded gate trench field effect transistor device is considered to be composed of silicon (Si) material. However, the substrate can also be composed of any other material suitable for the manufacture of shielded gate trench field effect transistors, such as gallium nitride (GaN), silicon carbide (SiC), etc. In the following description, the conductivity type of the semiconductor region is divided into P type (second conductivity type) and N type (first conductivity type). A semiconductor region of P type conductivity type can be formed by doping one or more impurities into the original semiconductor region. These impurities can be but are not limited to: boron (B), aluminum (Al), gallium (Ga), etc. An N type conductive semiconductor region can also be formed by doping one or more impurities into the original semiconductor region. These impurities can be but are not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H + In the following description, the heavily doped P-type conductive semiconductor region is marked as P + The heavily doped N-type conductive semiconductor region is marked as N + For example, in a silicon substrate, unless otherwise specified, the impurity concentration of a heavily doped region is generally 1×10 19 cm -3 Up to 1×10 21 cm -3 Those skilled in the art should know that the P-type (second conductivity type) and the N-type (first conductivity type) described in the present invention can be interchanged.

[0038] The structure of the semiconductor trench field effect transistor device of the first embodiment of the present invention is as follows: Figure 3 As shown in A-3D. Figure 3 A is a partial top view of the trench and contact hole structure of the device. Figure 3 B-3D Figure 3 Schematic diagram of the cross-sectional structure corresponding to tangent lines A, B, and C in A.

[0039] The structure of the semiconductor trench field effect transistor device includes: an N-type substrate layer 310 located at the bottom, a first epitaxial layer 311 above the N-type substrate layer 310 , and a second epitaxial layer 321 above the first epitaxial layer.

[0040] A first type of groove 301 is located on the upper surface of the semiconductor and is periodically distributed. In the first type of groove, there is a gate electrode 302 located above the groove, and a shielding gate electrode 303 located in the middle of the groove. The gate electrode 302 is isolated from the sidewall of the groove by a gate oxide layer. The gate electrode 302 and the shielding gate electrode 303 are isolated by an inter-electrode isolation layer. The shielding gate electrode 303 in the first type of groove 301 is connected to the source metal 320 on the upper surface of the device through a second contact hole 334 on the insulating oxide layer 317. In addition, the shielding gate electrode 303 is isolated from the sidewall of the groove by a shielding gate isolation layer 313.

[0041] The second type of trench 305 is located between the first type of trenches 301, and the second type of trench is narrower and shallower than the first type of trench. The second type of trench 305 has a gate electrode 302, and the gate electrode 302 is isolated from the sidewall of the trench by a gate oxide layer. The gate electrode 302 is isolated from the bottom of the trench by a bottom oxide layer. The first type of trench 301 and the second type of trench 305 form a chain-type trench structure. The gate electrodes 302 in adjacent first type of trenches 301 and second type of trenches 305 are connected to each other.

[0042] The P-doped body region 308 and the N-doped body region 308 between the first type trenches 301 on the upper surface + The P doped source region 309. + The doped source region 309 is connected to the source metal 320 on the upper surface of the device through the first contact hole 304 on the insulating oxide layer 317 .

[0043] like Figure 3 As shown in FIG. 1A , the first type of trench 301 and the second type of trench 305 are connected in series to form a chain-type trench structure. The gate signal is conducted through the gate electrode 302 in the chain-type trench. The gate electrode is usually made of polysilicon material, but in some embodiments, in order to further reduce the gate resistance and reduce the gap, a metal material such as Al, Ti, W, etc. may also be used. The gate electrode in the chain-type trench may be connected to the gate metal layer located above the semiconductor in the peripheral area of ​​the chip.

[0044] Typically, the bottom of the first type of groove 301 is a smooth arc surface. The upper surface opening of the first type of groove 301 is a circle or a regular polygon, such as a square or a regular hexagon. However, in some embodiments, the upper opening may also be an elliptical cylinder or a convex polygon, such as a rectangle. In one embodiment, the upper opening of the first type of groove 301 is a circle with a diameter of 2-5um, and the depth of the groove is 6-20um.

[0045] The second type groove 305 is located between two adjacent first type grooves 301 and is generally a straight groove. In one embodiment, each second type groove 305 has a length of 0.5-3 um, a width of 0.3-3 um, and a depth of 0.5-3 um.

[0046] like Figure 3 As shown in Figure A, the spacing between adjacent first-type trenches 301 is the same (a3=b3), so that a charge balance in each direction can be formed when the first-type trenches 301 are reverse biased. In some embodiments, in order to compensate for the influence of the second-type trenches 305 on the charge balance, the spacing between adjacent first-type trenches 301 in the direction of the second-type trenches 305 may be appropriately adjusted to maintain the charge balance in each direction of the first-type trenches 301 when the first-type trenches 301 are reverse biased, thereby ensuring the device breakdown voltage.

[0047] The shielding gate isolation layer 313 between the shielding gate electrode 303 and the trench sidewall may have a uniform thickness, or may have a structure that is thin at the top and thick at the bottom, such as Figure 3 B, 3C. In one embodiment, the shielding gate isolation layer 313 is divided into two parts, the thickness of the upper isolation layer is between 3000A and 2um, and the thickness of the lower isolation layer is between 5000A and 2.5um.

[0048] like Figure 3 B. The gate electrodes 302 in the second type trench 305 and the first type trench 301 generally have the same depth. However, in some embodiments, the gate electrode 302 in the second type trench 305 may be deeper than the gate electrode 302 in the first type trench 301 .

[0049] In the second type trench 305, the bottom oxide layer 323 located below the gate electrode 302 is generally thicker than the gate oxide layer. Figure 3 D. However, in some embodiments, the bottom oxide layer 323 may be as thick as the gate oxide layer and formed simultaneously with the gate oxide layer.

[0050] The doping concentration of the second epitaxial layer 321 is lower than that of the first epitaxial layer 311, and the depth of the second epitaxial layer 321 is generally deeper than that of the second type trench 305. In some embodiments, the N-type semiconductor located between the first type trenches 301 may have more doping layers to achieve a doping structure with a light doping concentration at the top and a heavy doping concentration at the bottom. In some embodiments, the N-type semiconductor located below the first type trench 301 may have more doping layers, and the doping concentration thereof is lower than that of the N-type semiconductor between the trenches.

[0051] Around the chain-shaped trench, there is a first contact hole 304 surrounding the trench and connected to the source metal 320 on the upper surface of the semiconductor. Figure 3As shown in A, in one embodiment, the first contact hole 304 is a long strip-shaped groove with a width between 0.2um and 1um. The first contact hole 304 is divided into two directions: the first direction contact hole is parallel to the direction of the second type of groove 305, and its shortest distance to the first type of groove 301 is between 0.1 and 0.5um. The second direction contact hole is perpendicular to the direction of the second type of groove 305 and is located between two sections of the second type of groove 305. Its shortest distance to the second type of groove 305 is between 0.1 and 0.5um. The function of the first contact hole 304 is to connect the P-doped body region 308 and the N-doped body region 308 between the grooves. + The P doped source region 309 is connected to the source metal 320. The P doped body region 308 and the N + The doped source regions 309 are usually distributed along the chain-shaped trenches, so the contact holes are arranged around the trenches as much as possible (but they cannot touch the trenches, and avoid touching 302 in the trenches).

[0052] The first contact hole 304 connecting the semiconductor and the source metal 320 and the second contact hole 334 connecting the shielding gate electrode 303 and the source metal 320 may be formed at the same time, and the depths of the two are usually the same. Generally, the ratio of the minimum width of the first contact hole 304 to the second contact hole 334 is less than 3, for example: in a practical embodiment, the minimum width of the first contact hole 304 is 0.5-1.5um, and the minimum width of the second contact hole 334 is 0.2-1um.

[0053] It should be noted that the groove chain structure of the present invention may not have a single direction. Figure 4 A and Figure 4 B shows a groove chain structure of a feasible embodiment, wherein the second type of grooves 305 on the groove chain structure may have at least two or more groove directions, and form an S-shaped, U-shaped or cross-shaped groove chain structure.

[0054] The above mentioned Figure 3 In the embodiment A, the first contact holes 304 in two directions may form a cross-shaped contact hole groove at the intersection. In some embodiments, the cross-shaped contact hole groove structure may be avoided to prevent the problem of uneven contact hole etching, such as Figure 5 A, as shown in 5B.

[0055] Figure 5A shows a top view of an embodiment of a feasible groove and contact hole structure. The first contact hole 304 is divided into a long contact hole 337 and a short contact hole 338 according to the length. The long contact hole 337 is parallel to the direction of the second type of groove 305, and the shortest distance between it and the first type of groove 301 is between 0.1 and 0.5 um. The length of the short contact hole 338 is between 0.2 um and 5 um, and is evenly distributed between the long contact hole 337 and the groove chain. The shortest distance between all contact hole segments is between 0.3 and 1.5 um. The shortest distance from the short contact hole 338 to the groove chain is between 0.1 and 0.5 um. The short contact hole 338 may be parallel to the long contact hole 337, such as Figure 4 As shown in A, the direction may also be different from that of the long contact hole 337.

[0056] Figure 5 B shows a top view of another possible embodiment of the trench and contact hole structure. In this structure, the first contact hole 304 is a long strip structure surrounding the trench chain, and there are at least two sections of first contact holes 304 between adjacent trench chains. In one embodiment, the distance between the first contact hole 304 and the trench chain is the same, and the distance is between 0.2 and 0.6 um.

[0057] In the top view of the above embodiment, the second contact hole 334 connecting the shielding gate electrode 303 and the source metal 320 is not drawn. The second contact hole 334 is usually located directly above the shielding gate electrode 303 in the middle of the first type of trench, and needs to avoid contacting the gate electrode 302 in the trench to prevent gate-source leakage. Therefore, the opening size of the second contact hole 334 is limited. An implementation scheme to solve this problem is as follows Figure 5 As shown in C.

[0058] Figure 5 C shows a top view of another feasible embodiment of the trench and contact hole structure, which is different from the aforementioned embodiment in that the gate electrode 302 in the first type of trench does not completely surround the shielding gate trench 303 in the middle, but at least a part is vacant to form a gate electrode gap. On the gate electrode gap, there is a long strip of second contact hole 344. The long strip of second contact hole trench 344 respectively connects the shielding gate electrode 303 in the first type of trench 301, the semiconductor region outside the gate gap, and the source metal 320. Usually, there is an oxide layer at the gate gap in the trench and isolates the long strip contact hole 344 and the gate electrode 302. In some embodiments, the above-mentioned long strip contact holes 344 are respectively connected to the first type of trenches 301 in adjacent trench chains, such as Figure 5 C. In one embodiment, the width of the long strip contact hole 344 is between 0.2um and 1um, and the minimum distance from the long strip contact hole 344 to the gate electrode 302 is between 0.2um and 0.5um.

[0059] Figure 5 D shows a top view of an embodiment of a feasible groove and contact hole structure. Among them, the structure also includes a third type of groove 330 located between adjacent groove chain structures. The third type of groove 330 is completely filled with oxide. The third type of groove 330 may be a single groove distributed periodically, and the opening above it is usually circular or regular polygonal, or it may be a long groove distributed periodically. The depth of the third type of groove 330 is shallower than that of the first type of groove 301, and may be similar to that of the second type of groove 305. Usually, the distance from the third type of groove 330 to the second type of groove 305 of the adjacent groove chain structure is the same. The third type of groove 330 is beneficial to reduce the gate capacitance of the device and improve the switching speed. In addition, the third type of groove 330 set at the breakdown weak point of the device can improve the breakdown voltage and UIS performance of the device.

[0060] Figures 6 to 12 The key steps in a feasible manufacturing method of the device of the embodiment of the present invention are shown, wherein the left diagram corresponds to the first type of trench 301 structure, and the right diagram corresponds to the second type of trench 305 structure and the third type of trench 330 structure.

[0061] In the first step, a hard mask layer 312 is formed on the upper surface of the N-type semiconductor 300, and a hard mask opening is formed by photolithography on the hard mask layer 312, and a first type of trench 301, a second type of trench 305, and a third type of trench 330 are etched at the hard mask opening. Figure 6 shown.

[0062] The N-type semiconductor 300 may include an N-type substrate layer at the bottom and a plurality of N-type epitaxial layers at the top.

[0063] The material of the hard mask layer may be an oxide layer or a nitride layer, or a combination of an oxide layer and a nitride layer. In one embodiment, the hard mask includes 50A-1000A oxide at the bottom and 1000A-4000A nitride at the top.

[0064] The first type of groove 301, the second type of groove 305, and the third type of groove 330 have different depths. The three types of grooves may be formed simultaneously by the same etching process, and by controlling the etching process, a shallow etching depth (second and third types of grooves) is formed in a narrow etching opening, and a deep etching depth (first type of groove) is formed in a wider etching opening. In addition, in some embodiments, the three types of grooves may also be formed successively by different etching steps to better control the etching depths required for different types of grooves.

[0065] For example, in one embodiment, the first type of groove 301 is firstly formed by the first photolithography, and the first groove etching is performed. Then, the second type of groove 301 and the third type of groove 330 are formed by the second photolithography, and the second type of groove etching is performed. By adjusting the etching conditions of the above two groove etchings, a series of groove structures with greatly different depths and / or aspect ratios required by the present invention can be achieved.

[0066] In the second step, a shielding gate isolation layer 313 is formed in the first type trench 301. At this time, the shielding gate isolation layer 313 material completely fills the second type trench 305 and the third type trench 330. Figure 7 As shown in A.

[0067] The shielding gate isolation layer 313 may be an oxide, a nitride, a low-k material, or a combination thereof. In one embodiment, the shielding gate isolation layer 313 is an oxide, and the method of forming the oxide is thermal oxidation or deposition. In one embodiment, the shielding gate isolation layer 313 is an oxide, and the method of forming the oxide is as follows: first, a 1000A-5000A oxide is formed by thermal oxidation, and then a 2000A-7000A oxide is deposited.

[0068] The shielding gate isolation layer 313 may be a single thickness structure. In some embodiments, in order to increase the breakdown voltage of the cylindrical trench, the shielding gate isolation layer 313 may also be a structure that is thin at the top and thick at the bottom.

[0069] Figure 7 B-7C shows the key steps to achieve the double-layer structure of the shielding gate isolation layer 313, which is thin on the top and thick on the bottom. First, a thicker shielding gate isolation layer 313 is formed; then, a trench filler 344 is deposited and etched back to the required depth, such as Figure 7 B; Finally, an isotropic etching is performed to etch the shielding gate isolation layer 313 above the trench to the desired thickness, such as Figure 7 C. The trench filler 344 is usually polysilicon. After forming the shielding gate isolation layer 313 structure with a thin top and a thick bottom, the trench filler 344 may be removed or may remain in the trench.

[0070] Figure 7D-7E shows another key step to achieve a double-layer thickness structure of the shielding gate isolation layer 313, which is thin on the top and thick on the bottom. In this structure, the shielding gate isolation layer 313 is a three-layer structure: a first isolation layer 351, a second isolation layer 352, and a third isolation layer 353. Among them, the material of the second isolation layer 352 is different from that of the first isolation layer 351 and the third isolation layer 353. In one embodiment, the first isolation layer 351 and the third isolation layer 353 are oxides, and the second isolation layer 352 is nitride. The key steps of the process flow are as follows: First, the first isolation layer 351, the second isolation layer 352, and the third isolation layer 353 are formed in the grooves respectively. Then, the trench filler 344 is deposited and etched back to the desired depth, such as Figure 7 D; then the third isolation layer 352 is isotropically etched to completely remove the third isolation layer 352 above the trench, as shown in FIG. Figure 7 E. In the above method, the morphology of the final shielded gate isolation layer 313 can be controlled by adjusting the thickness of the first isolation layer 353 and the third isolation layer 353, which is beneficial to process control.

[0071] The third step is to fill the first type trench 301 with a shielding gate material 314. The shielding gate material 314 is usually polysilicon, such as Figure 8 shown.

[0072] The fourth step is to perform chemical mechanical polishing, and the polishing stops on the hard mask layer 312 on the upper surface of the semiconductor. Fig. 9 shown.

[0073] The hard mask layer 312 may be a nitride layer. In one embodiment, the hard mask layer 312 may be removed after chemical mechanical polishing.

[0074] The fifth step is to perform photolithography, and under the protection of the photoresist, a portion of the shielding gate isolation layer 313 adjacent to the first type of trench 301 and the shielding gate isolation layer 313 above the second type of trench 305 are etched, such as Fig.10 shown.

[0075] The etching method is usually dry etching, but dry etching may be performed first and then wet etching.

[0076] After etching, the distance between the remaining shielding gate isolation layer 313 above the first type trench 301 and the shielding gate electrode 303 is between 0.1-0.8um, and the remaining isolation layer serves as the inter-electrode isolation layer of the device. After etching, the notch depth of the shielding gate isolation layer 313 above the first type trench 301 is between 0.3-1.5um.

[0077] After etching, part of the shielding gate isolation layer 313 material usually remains under the second type trench 305 and serves as the final bottom oxide layer 323. In some embodiments, the depth of the second type trench 305 may be shallower than the etching depth of the shielding gate isolation layer 313, and the shielding gate isolation layer 313 material in the second type trench 305 will be completely removed.

[0078] In the sixth step, a gate oxide layer and a gate electrode 302 are formed in the first type trench 301 and the second type trench 305. Fig.11 shown.

[0079] The process of forming the gate electrode may include polysilicon deposition and etching back steps.

[0080] In one embodiment, when etching back the gate electrode polysilicon, the upper surface of the shielding gate electrode 303 formed of polysilicon material is protected by an oxide layer.

[0081] The process of forming the gate electrode may also include a chemical mechanical polishing process. In one embodiment, polysilicon may be deposited first, and then a chemical mechanical polishing process is performed to grind the polysilicon material at the top of the trench, the shielding gate isolation layer 313, and the shielding gate electrode 303, and stop on the hard mask layer 312, and then the polysilicon is etched back to form the gate electrode.

[0082] In the seventh step, a P-doped body region 308 and an N+-doped source region 309 are formed, an insulating oxide layer 317 is formed above the semiconductor, and then contact holes (304, 334) are formed in the insulating oxide layer 317, and finally a top surface metal is formed to finally form a device, such as Fig.12 shown.

[0083] The above process flow shows a key step in manufacturing the device structure of the present invention, which can be appropriately changed according to the actual process. For example, Fig.13 A and Fig.13 B provides a variation of the process flow of the embodiment:

[0084] In the fifth step of the above process, photolithography is performed first, and then the shielding gate isolation layer 313 above the first type trench 301 and the second type trench 305 is etched. Fig.13 A. After etching, the shielding gate isolation layer above the first type trench 301 is removed, and the sidewall of the shielding gate electrode 303 in the first type trench 301 is exposed.

[0085] In the sixth step of the above process, thermal oxidation is performed to form a gate oxide layer between the trenches and the semiconductor trenches, and to form an inter-electrode isolation layer 349 between the gate electrode and the shielding gate electrode in the first type trench 301 .

[0086] The final result of the device is as follows Fig.13As shown in B.

[0087] The thickness of the inter-electrode isolation layer 349 is generally between 1000 Å and 5000 Å. In some embodiments, a sidewall protection layer may be formed in advance and thermal oxidation may be performed twice to form the inter-electrode isolation layer 349 and the gate oxide layer respectively. In some embodiments, the oxidation rate of the shielding gate electrode polysilicon may be increased by an additional ion implantation method. The above method can form a thicker inter-electrode isolation layer 349.

[0088] Those skilled in the art should know that the above manufacturing steps only list key steps and do not show the complete steps of forming a device. Specific detailed manufacturing steps can be obtained based on common manufacturing process steps and common sense knowledge in the field and can be appropriately increased, decreased or changed.

[0089] In addition, those skilled in the art should know that the structural features and process steps mentioned in the above-mentioned embodiments of the present invention can be combined with each other to form more embodiment device structures and manufacturing processes.

Claims

1. A chain-type semiconductor device, comprising a first conductive substrate layer at the bottom, an epitaxial layer above the first conductive substrate layer, and a source electrode at the upper surface of the device; characterized in that: The upper surface of the semiconductor is provided with more than one chain-shaped groove and an insulating oxide layer arranged above the chain-shaped groove, and the insulating oxide layer is provided with a first contact hole and a second contact hole; The chain-type grooves include a first type of groove and a second type of groove connected to the first type of groove and narrower and shallower than the first type of groove. The first type of groove is provided with a gate electrode and a shielding gate electrode separated from the gate electrode. The shielding gate electrode is connected to the source through a second contact hole provided thereon. The second type of groove is provided with a gate electrode. The first type of groove and the gate electrode in the second type of groove are connected. A second conductive type doped body region and a first conductive type heavily doped source region are provided between the first type of grooves. The second conductive type doped body region and the first conductive type heavily doped source region are connected to the source through a first contact hole.

2. The chain-type semiconductor device according to claim 1, characterized in that: The first type of groove has a circular or regular polygonal upper surface opening and a smooth arc bottom, and includes a shielding gate electrode disposed in the middle of the groove and a gate electrode surrounding the shielding gate electrode, and / or the second type of groove is a linear groove.

3. The chain-type semiconductor device according to claim 2, characterized in that: The gate electrode in the first type of trench is provided with a gate electrode notch, and the gate electrode notch is provided with a second contact hole, which respectively connects the shielding gate electrode in the first type of trench, the semiconductor region outside the gate electrode notch, and the source electrode.

4. The chain-type semiconductor device according to claim 1, characterized in that: The spacing between adjacent non-connected first-type grooves is equal to the spacing between adjacent connected first-type grooves.

5. The chain-type semiconductor device according to claim 1, characterized in that: The isolation layer between the shielding gate electrode and the groove sidewall is in a structure of being thin at the top and thick at the bottom.

6. The chain-type semiconductor device according to claim 1, characterized in that: The epitaxial layer includes a first epitaxial layer located above the first conductive substrate layer and a second epitaxial layer located on the first epitaxial layer, and the doping concentration of the second epitaxial layer is lower than that of the first epitaxial layer.

7. The chain-type semiconductor device according to claim 1, characterized in that: The first contact holes are long straight grooves evenly distributed in the device, or the first contact holes are strip structures surrounding the chain grooves; And / or the ratio of the minimum width of the first contact hole to the minimum width of the second contact hole is less than 3:

1.

8. The chain-type semiconductor device according to claim 7, characterized in that: The first contact holes include first direction contact holes parallel to the chain-shaped grooves and second direction contact holes perpendicular to the first direction contact holes.

9. The chain-type semiconductor device according to claim 7, characterized in that: The first contact hole is a long linear groove, and the first contact hole includes a long contact hole and a short contact hole parallel to the chain groove, wherein the long contact hole is at an equal distance from the chain grooves on both sides thereof, and the short contact holes are evenly distributed on both sides of the second type groove.

10. The chain-type semiconductor device according to claim 1, characterized in that: A third type of trench is also provided on the device breakdown weak point between adjacent trench chain structures.

11. The chain-type semiconductor device according to claim 1, characterized in that: The chain-shaped grooves are evenly arranged in a straight line, S-shape, U-shape or cross-shape in the device.

12. A method for manufacturing a chain-type semiconductor device according to any one of claims 1 to 11, characterized in that: The manufacturing method comprises the following steps: The first step is to form a hard mask layer on the upper surface of the first conductive type semiconductor, perform photolithography on the hard mask layer to form a hard mask opening, and etch the first type of trench, the second type of trench, and the third type of trench at the hard mask opening; Step 2: forming a shielding gate isolation layer in the first type of trench, wherein the shielding gate isolation layer material completely fills the second type of trench and the third type of trench; The third step is to fill the shielding grid material in the first type of trench; The fourth step is to perform chemical mechanical polishing, where the polishing stops on the hard mask layer on the upper surface of the semiconductor; The fifth step is to perform photolithography under the protection of photoresist to etch a portion of the shielding gate isolation layer above the first type of trench and adjacent to the trench, as well as the shielding gate isolation layer above the second type of trench; after etching, the remaining shielding gate isolation layer above the first type of trench serves as an inter-electrode isolation layer of the device; Step 6, forming a gate oxide layer and a gate electrode in the first type of trench and the second type of trench; The seventh step is to form a second conductivity type doped body region and a first conductivity type heavily doped source region, to form an insulating oxide layer located above the semiconductor, and then to form a contact hole in the insulating oxide layer, and finally to form an upper surface metal and finally to form a device.

13. A method for manufacturing a chain-type semiconductor device according to claim 12, characterized in that: In the fifth step, photolithography is performed first, and then the shield gate isolation layer above the first type of trench and the second type of trench is etched; after etching, the shield gate isolation layer above the first type of trench is removed, and the side wall of the shield gate electrode in the trench is exposed; In the sixth step, thermal oxidation is performed to form a gate oxide layer between the trenches and the semiconductor trenches, and to form an inter-electrode isolation layer between the gate electrode and the shielding gate electrode in the first type of trenches.

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