Silicon carbide super junction power device and manufacturing method thereof

Abstract

The invention provides a silicon carbide super junction power device and a manufacturing method thereof. The silicon carbide super junction power device comprises a silicon carbide substrate, a plurality of vertical medium structures and n epitaxial layers stacked on one side of the silicon carbide substrate, wherein n is a positive integer greater than 1. Each epitaxial layer is provided with a plurality of horizontal doped regions, the plurality of horizontal doped regions are arranged in the top of the epitaxial layer in an array, and the upper surfaces of the horizontal doped regions are flush with the upper surface of the epitaxial layer. The horizontal doped regions of all the layers are opposite. The n epitaxial layers comprise a first epitaxial layer, and first horizontal doped regions are arranged in the top of the first epitaxial layer in an array mode. And the vertical medium structures pass through the horizontal doped regions in the same column and extend into the first horizontal doped region. And the product is independent of related contents. The epitaxial layer with higher concentration is used while the voltage withstanding level is guaranteed, so that the specific on-resistance of the power device can be reduced, and the current density of the power device can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a silicon carbide super junction power device and a method for manufacturing the same. Background Art

[0002] Silicon carbide superjunction power devices are suitable for high voltage, high current, high temperature, high frequency and other working conditions, which can significantly improve the efficiency of power conversion and reduce the loss of power conversion. Currently, they have been widely used in high-end switching power supplies, new energy vehicles and new energy vehicle main electric drives.

[0003] However, current silicon carbide superjunction power devices still have the problem of large on-resistance. Summary of the invention

[0004] In view of the shortcomings of the existing methods, the present application proposes a silicon carbide super junction power device and a manufacturing method thereof, so as to solve the technical problem of large on-resistance in the related technology.

[0005] In a first aspect, an embodiment of the present application provides a silicon carbide super junction power device, including:

[0006] Silicon carbide substrate;

[0007] n epitaxial layers are stacked on one side of the silicon carbide substrate; each epitaxial layer is provided with a plurality of horizontal doping regions, and the plurality of horizontal doping regions are arrayed on the top of the epitaxial layer, and the upper surface of the horizontal doping region is flush with the upper surface of the epitaxial layer; the horizontal doping regions of each layer are opposite; wherein n is a positive integer greater than 1;

[0008] The n epitaxial layers include a first epitaxial layer, wherein a first horizontal doping region is arranged in an array on the top of the first epitaxial layer;

[0009] A plurality of vertical dielectric structures are provided, wherein the vertical dielectric structures pass through the horizontal doping regions located in the same column and extend to the interior of the first horizontal doping region.

[0010] In a second aspect, an embodiment of the present application provides a method for manufacturing a silicon carbide super junction power device, comprising:

[0011] S1: manufacturing a first epitaxial layer on one side of the silicon carbide substrate; forming a first horizontal doping region arranged in an array on the top of the first epitaxial layer by ion implantation under a mask of a first mask plate, so that the upper surface of the first horizontal doping region is flush with the upper surface of the first epitaxial layer;

[0012] S2: manufacturing an nth epitaxial layer on the first epitaxial layer, and forming an nth horizontal doping region arranged in an array on the top of the nth epitaxial layer by ion implantation; repeating this step until a set number of epitaxial layers is obtained, wherein n is a positive integer greater than 1;

[0013] S3: patterning the horizontal doping regions located in the same column to obtain vertical grooves, so that the vertical grooves extend into the first horizontal doping region;

[0014] S4: manufacturing a vertical dielectric structure in the vertical trench.

[0015] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0016] Because the vertical dielectric structure with a high dielectric constant can withstand high electric field strength, it promotes the depletion of the epitaxial layer and the horizontal doping region, which is beneficial to use a higher concentration epitaxial layer while ensuring the withstand voltage level, thereby reducing the specific on-resistance of the power device and helping to increase the current density of the power device.

[0017] Due to the existence of the vertical grooves, the alignment accuracy of the n horizontal doping regions and the design margin of charge fluctuation can be increased, and the lithography registration deviation of the vertical grooves and the ohmic contact holes can be eliminated, which is beneficial to the design of small-size, high-density silicon carbide super junction power devices, and at the same time makes the design and process of silicon carbide super junction power devices more robust.

[0018] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0020] Figure 1 A schematic diagram of the structure of a silicon carbide super junction power device provided in an embodiment of the present application;

[0021] Figure 2 A schematic structural diagram of a cell in a silicon carbide super junction power device provided in an embodiment of the present application;

[0022] Figure 3 A schematic diagram of the change of electric field intensity in a vertical doping region provided in an embodiment of the present application;

[0023] Figure 4 A schematic diagram of a process for manufacturing a silicon carbide super junction power device provided in an embodiment of the present application;

[0024] Figure 5 and Figure 6 All of them are process flow charts of a method for manufacturing a silicon carbide super junction power device provided in an embodiment of the present application;

[0025] Figures 7 to 15 A schematic diagram of the structure obtained in a method for manufacturing a silicon carbide super junction power device provided in an embodiment of the present application. Description of the drawings:

[0027] 100-silicon carbide substrate;

[0028] 200 - first epitaxial layer; 201 - first mask; 210 - first horizontal doping region;

[0029] 300 - a second epitaxial layer; 310 - a second horizontal doping region;

[0030] 400 - a third epitaxial layer; 410 - a third horizontal doping region;

[0031] 500-high epitaxial layer; 510-shielding structure; 520-horizontal part; 530-vertical part; 540-source region; 550-base region;

[0032] 600-second mask; 601-dielectric mask; 602-sidewall mask; 610-first trench; 620-second trench; 630-vertical trench;

[0033] 700-vertical dielectric structure; 701-first dielectric structure; 702-second dielectric structure; 710-first gate dielectric layer; 711-second gate dielectric layer; 720-gate electrode; 721-pseudo electrode;

[0034] 800 - first interlayer dielectric layer; 801 - second interlayer dielectric layer; 810 - source electrode; 820 - drain electrode;

[0035] 900-vertical doping region. DETAILED DESCRIPTION

[0036] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0037] It will be understood by those skilled in the art that, unless specifically stated, the "said" and "the" used herein may also include plural forms. It should be further understood that the wording "including" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may refer to the connection relationship between the element and the other element through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0038] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0039] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.

[0040] The descriptions "first conductivity type" and "second conductivity type" used in this application refer to n-type conductivity (i.e., electron conductivity) and p-type conductivity (i.e., hole conductivity), respectively. Specifically, the first conductivity type is n-type conductivity, and the second conductivity type is p-type conductivity; or, the first conductivity type is p-type conductivity, and the second conductivity type is n-type conductivity.

[0041] The present application embodiment provides a silicon carbide super junction power device, the structural schematic diagram of the silicon carbide super junction power device is as follows Figure 1 and Figure 2 As shown, it includes: a silicon carbide substrate 100, a plurality of vertical dielectric structures 700, and n epitaxial layers stacked on one side of the silicon carbide substrate 100, wherein n is a positive integer greater than 1.

[0042] Each epitaxial layer is provided with a plurality of horizontal doping regions, which are arrayed on the top of the epitaxial layer, and the upper surface of the horizontal doping region is flush with the upper surface of the epitaxial layer. The horizontal doping regions of each layer are opposite to each other.

[0043] The n epitaxial layers include a first epitaxial layer 200 , and a first horizontal doping region 210 is arranged in an array on the top of the first epitaxial layer 200 .

[0044] The vertical dielectric structure 700 passes through the horizontal doping regions in the same column and extends to the inside of the first horizontal doping region 210 .

[0045] In this embodiment, the material of the vertical dielectric structure 700 is a material with a high dielectric constant, including metal oxides such as HfO2, TiO2, ZrO2, and Ta2O5. Since the vertical dielectric structure 700 with a high dielectric constant can withstand high electric field strength, thereby promoting the depletion of the epitaxial layer and the horizontal doping region, it is beneficial to use a higher concentration epitaxial layer while ensuring the withstand voltage level, thereby reducing the specific on-resistance of the power device and facilitating the improvement of the current density of the power device.

[0046] When the power device is subjected to reverse withstand voltage, the epitaxial layer and the horizontal doping region are gradually depleted or even completely depleted, and the vertical dielectric structure 700 can withstand high electric field strength, thereby enabling the epitaxial layer to withstand higher voltage at a higher doping level. The power device of the present application has a simple structure and a simple implementation method, which is conducive to improving the current density of the silicon carbide super junction power device.

[0047] Optionally, the height of the nth horizontal doping region is not less than the height of the n-1th horizontal doping region in a direction perpendicular to the silicon carbide substrate 100. In a direction vertically downward from the silicon carbide substrate 100, the interval between the nth horizontal doping region and the n-1th horizontal doping region is equal or increases.

[0048] In this embodiment, the height of the n horizontal doping regions is not less than 0.5 micrometers and not more than 1.5 micrometers. The doping concentration of the n horizontal doping regions is 1e 16 ~1e 18 cm -3 It is understandable that the size of the horizontal doping region is calculated according to the amount of charge required for charge balance, and no limitation is made herein.

[0049] Optionally, refer to Figure 1 and Figure 2 The silicon carbide super junction power device further includes a plurality of vertical doping regions 900 , and the vertical doping regions 900 are disposed on the outer side of the vertical dielectric structure 700 .

[0050] In this embodiment, the vertical doping region 900 is of the second conductivity type and has the function of adjusting the electric field strength of the vertical dielectric structure 700 .

[0051] For example, Figure 3 Schematic diagram of the electric field intensity distribution at AA' in the vertical doping region 900. The electric field intensity first increases and then decreases in the vertical doping region 900, which has the function of regulating the electric field intensity.

[0052] Optionally, the silicon carbide super junction power device further includes a high epitaxial layer 500 , a plurality of gate electrodes 720 and a plurality of pseudo electrodes 721 , a plurality of first gate dielectric layers 710 and a plurality of second gate dielectric layers 711 , a first dielectric structure 701 and a shielding structure 510 .

[0053] The high epitaxial layer 500 is disposed on the side of the nth epitaxial layer away from the silicon carbide substrate 100. A plurality of gate electrodes 720 and a plurality of pseudo electrodes 721 are arranged in the high epitaxial layer 500 at intervals; the first gate dielectric layer 710 is disposed on the sidewall of the gate electrode 720, and the second gate dielectric layer 711 is disposed on the sidewall of the pseudo electrode 721.

[0054] The first dielectric structure 701 is disposed at the bottom of the gate electrode 720 .

[0055] The shielding structure 510 is disposed on a side of the first dielectric structure 701 close to the silicon carbide substrate 100 .

[0056] Optionally, the orthographic projection of the first dielectric structure 701 on the silicon carbide substrate 100 falls within the orthographic projection of the shielding structure 510 on the silicon carbide substrate 100 .

[0057] In this embodiment, the shielding structure 510 can wrap the bottom of the first dielectric structure 701 , thereby wrapping the bottom of the gate electrode 720 .

[0058] Optionally, the material of the first dielectric structure 701 is a material with a high dielectric constant, and the thickness of the first dielectric structure 701 is more than twice the thickness of the first gate dielectric layer 710 .

[0059] Optionally, the silicon carbide super junction power device further includes a second dielectric structure 702 and a body region.

[0060] The second dielectric structure 702 is disposed at the bottom of the pseudo electrode 721 .

[0061] The body region includes a vertical portion 530 and a horizontal portion 520 connected to each other. The vertical portion 530 is disposed on the outer side of the second gate dielectric layer 711 and the second dielectric structure 702. The horizontal portion 520 extends to the side of the vertical dielectric structure 700, and the vertical doping region 900 is connected to the horizontal portion 520.

[0062] Optionally, the silicon carbide super junction power device further includes a plurality of source regions 540 and a plurality of base regions 550 , a plurality of first interlayer dielectric layers 800 and a plurality of second interlayer dielectric layers 801 , and a source electrode 810 and a drain electrode 820 .

[0063] The source region 540 and the base region 550 are both disposed between the vertical portion 530 of the body region and the first gate dielectric layer 710. The base region 550 is disposed on a side of the source region 540 close to the silicon carbide substrate 100. The upper surface of the source region 540 is flush with the upper surface of the high epitaxial layer 500.

[0064] The first interlayer dielectric layer 800 is disposed on the top of the gate electrode 720 , and the second interlayer dielectric layer 801 is disposed on the top of the pseudo electrode 721 .

[0065] The source electrode 810 is disposed on a side of the high epitaxial layer 500 away from the silicon carbide substrate 100 . The drain electrode 820 is disposed on the bottom of the silicon carbide substrate 100 .

[0066] In this embodiment, the bottom of the gate electrode 720 is closer to the silicon carbide substrate 100 than the bottom of the base region 550 .

[0067] Based on the same inventive concept, the present application embodiment provides a method for manufacturing a silicon carbide super junction power device, and the flow chart of the method is as follows: Figure 4 As shown, the method includes steps S1 to S3, which are specifically as follows:

[0068] S1: Fabricate a first epitaxial layer 200 on one side of the silicon carbide substrate 100 to obtain Figure 7 Schematic diagram of the structure shown; under the mask of the first mask plate 201, the first horizontal doping region 210 arranged in an array is formed by ion implantation on the top of the first epitaxial layer 200, so that the upper surface of the first horizontal doping region 210 is flush with the upper surface of the first epitaxial layer 200, reference Figure 8 and Fig. 9 Schematic diagram of the structure of a cell shown.

[0069] In this embodiment, the silicon carbide substrate 100 is of the first conductivity type. The epitaxial layer is also of the first conductivity type. The first mask 201 is formed into a structure with a specific line width by thin film deposition, photolithography, and etching.

[0070] S2: manufacturing an nth epitaxial layer above the first epitaxial layer 200, and forming an nth horizontal doping region arranged in an array on the top of the nth epitaxial layer by ion implantation; repeating this step until a set number of epitaxial layers is obtained, where n is a positive integer greater than 1.

[0071] In this embodiment, n stacked epitaxial layers of the first conductivity type can be obtained. The horizontal doping region is of the second conductivity type. In the direction perpendicular to the silicon carbide substrate 100, the height of the nth horizontal doping region is not less than the height of the n-1th horizontal doping region. In the vertical downward direction of the silicon carbide substrate 100, the interval between the nth horizontal doping region and the n-1th horizontal doping region is equal or increasingly larger. Specifically, the heights of the n horizontal doping regions are not less than 0.5 microns and not more than 1.5 microns. The doping concentration of the n horizontal doping regions is 1e 16 ~1e 18 cm -3 .

[0072] For example, Fig.10 As shown, three epitaxial layers are manufactured, namely, a first epitaxial layer 200, a second epitaxial layer 300, and a third epitaxial layer 400. A first horizontal doping region 210 is set on the top of the first epitaxial layer 200, a second horizontal doping region 310 is set on the top of the second epitaxial layer 200, and a third horizontal doping region 410 is set on the top of the third epitaxial layer 400. The first horizontal doping region 210, the second horizontal doping region 310, and the third horizontal doping region 410 are arranged relatively.

[0073] Optionally, after step S2 and before step S3, the manufacturing method further includes:

[0074] S201: A high epitaxial layer 500 is manufactured on a side of the nth epitaxial layer away from the silicon carbide substrate 100, and ion implantation is performed in the high epitaxial layer above the junction region between adjacent horizontal doping regions to sequentially form a base region 550 and a source region 540, so that the upper surface of the source region 540 is flush with the upper surface of the high epitaxial layer 500.

[0075] In this embodiment, a high epitaxial layer 500 is manufactured on the side of the nth epitaxial layer away from the silicon carbide substrate 100. Fig.10 A mask structure with a specific line width is formed by thin film deposition, photolithography, and etching, and the mask structure is disposed on the upper portion of the high epitaxial layer 500. Through the mask of the mask structure, ion implantation is performed to form a base region 550 of the second conductivity type and a source region 540 of the first conductivity type.

[0076] It should be noted that the height of the base region 550 is the length of the channel. The height of the base region 550 is not less than 0.3 micrometers and not more than 0.5 micrometers. The doping concentration of the base region 550 is 1e 17 ~1e 19 cm -3 .

[0077] S202: Under the mask of the second mask plate 600, the high epitaxial layer 500 is patterned to obtain the first trenches 610 and the second trenches 620 arranged at intervals, so that the first trenches 610 pass through the base region 550 and the source region 540, and the bottom of the first trenches 610 is lower than the lower surface of the base region 550, so that the second trenches 620 expose the side surfaces of the base region 550 and the source region 540. The obtained structural schematic diagram is shown in FIG. Fig.12 shown.

[0078] S203: Perform ion implantation through the first trench 610 and the second trench 620 to form a shielding structure 510 below the bottom of the first trench 610 and a horizontal portion 520 of the body region below the bottom of the second trench 620; fill the first trench 610 with a dielectric mask 601, and then perform ion implantation through the side of the second trench 620 to form a vertical portion 530 of the body region.

[0079] In this embodiment, the shielding structure 510 and the horizontal portion 520 of the body region can be obtained by vertical ion implantation; the vertical portion 530 of the body region can be obtained by oblique angle ion implantation.

[0080] S204 : manufacturing a spacer mask 602 on the side of the second trench 620 .

[0081] In this embodiment, a sidewall mask 602 is manufactured on the side of the second trench 620, and the resulting structure is shown in FIG. Fig.13 The spacer mask 602 can be formed by a self-aligned spacer process, which is beneficial to avoid the photolithography registration deviation of the traditional process.

[0082] S3 : patterning the horizontal doping regions in the same column to obtain the vertical trenches 630 , such that the vertical trenches 630 extend into the first horizontal doping region 210 .

[0083] In this embodiment, under the sidewall mask 602, the horizontal portion 520 of the body region is masked, and the horizontal doping region located in the same column is patterned to obtain a vertical groove 630. The obtained structural schematic diagram is shown in FIG. Fig.14 As shown. Due to the existence of the vertical groove 630, the alignment accuracy of the n horizontal doping regions and the design margin of the charge fluctuation can be increased, and the photolithography registration deviation of the vertical groove and the ohmic contact hole can be eliminated, which is conducive to the design of small-size and high-density silicon carbide super junction power devices, and at the same time makes the design and process of the silicon carbide super junction power device have strong robustness.

[0084] Optionally, after step S3 and before step S4, the manufacturing method further includes: performing ion implantation on the side of the vertical trench 630 to form a vertical doping region 900, so that the vertical doping region passes through the horizontal doping region in the same column and is connected to the horizontal portion 520 of the body region. The obtained structural schematic diagram is as shown in FIG. Fig.14 shown.

[0085] In this embodiment, the ion implantation method may be an oblique angle ion implantation. The width of the vertical doping region 900 is not greater than 0.3 micrometers, and the doping concentration is 1e 16 ~1e 18 cm -3 The amount of charge in the vertical doping region 900 and the spatial distribution of the charge can be precisely controlled by ion implantation.

[0086] Optionally, after forming the vertical doping region and before step S4 , the manufacturing method further includes: removing the second mask 600 , the dielectric mask 601 and the sidewall mask 602 .

[0087] S4 : manufacturing a vertical dielectric structure 700 in the vertical trench 630 .

[0088] In this embodiment, the material of the vertical dielectric structure 700 is a material with a high dielectric constant, specifically including metal oxides such as HfO 2 , TiO 2 , ZrO 2 , and Ta 2 O 5 .

[0089] Optionally, in step S4, the manufacturing method further includes: filling the bottom of the first trench 610 and the bottom of the second trench 620 with a medium with a high dielectric constant to form a first dielectric structure 701 and a second dielectric structure 702 respectively. The obtained structural schematic diagram is shown in FIG. Fig.15 shown.

[0090] In this embodiment, the materials of the first dielectric structure 701 and the second dielectric structure 702 include metal oxides such as HfO2, TiO2, ZrO2, Ta2O5, etc. The thickness of the first dielectric structure 701 and the second dielectric structure 702 is not less than 50 nanometers and not more than 200 nanometers.

[0091] Optionally, after step S4, the manufacturing method further includes:

[0092] S5: A first gate dielectric layer 710 and a second gate dielectric layer 711 are respectively formed on the sidewalls of the first trench 610 and the second trench 620; then a gate electrode 720 is formed in the first trench 610, and a pseudo electrode 721 is formed in the second trench 620. The obtained structure schematic diagram is shown in FIG. Fig.15 shown.

[0093] In this embodiment, the gate electrode 720 and the pseudo electrode 721 are both made of polysilicon. The pseudo electrode 721 can be floating or grounded.

[0094] S6: forming a first interlayer dielectric layer 800 and a second interlayer dielectric layer 801 above the gate electrode 720 and the pseudo electrode 721 , respectively.

[0095] In this embodiment, the first interlayer dielectric layer 800 and the second interlayer dielectric layer 801 can be manufactured by a self-oxidation process. The first interlayer dielectric layer 800 and the second interlayer dielectric layer 801 both include a self-oxidation layer. The gap in the self-oxidation layer can be used as an ohmic contact hole. Compared with the contact hole obtained by the photolithography process in the traditional process, it can be more accurate and save cost and time.

[0096] S7: A source electrode 810 is fabricated on the side of the high epitaxial layer 500 away from the silicon carbide substrate 100, and a drain electrode 820 is fabricated on the bottom of the silicon carbide substrate 100. The resulting structure is shown in FIG. Figure 2 shown.

[0097] In this embodiment, the source electrode 810 is in ohmic contact with both the source region 540 and the body region.

[0098] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, changed, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, changed, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the related art that are similar to those disclosed in this application may also be alternated, changed, rearranged, decomposed, combined, or deleted.

[0099] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0100] The terms "first", "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0101] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0102] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0103] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A silicon carbide super junction power device, characterized in that: include: Silicon carbide substrate; n epitaxial layers are stacked on one side of the silicon carbide substrate; each epitaxial layer is provided with a plurality of horizontal doping regions, and the plurality of horizontal doping regions are arrayed on the top of the epitaxial layer, and the upper surface of the horizontal doping region is flush with the upper surface of the epitaxial layer; the horizontal doping regions of each layer are opposite; wherein n is a positive integer greater than 1; The n epitaxial layers include a first epitaxial layer, wherein a first horizontal doping region is arranged in an array on the top of the first epitaxial layer; A plurality of vertical dielectric structures are provided, wherein the vertical dielectric structures pass through the horizontal doping regions located in the same column and extend to the interior of the first horizontal doping region.

2. The silicon carbide super junction power device according to claim 1, characterized in that: It also includes a plurality of vertical doping regions, wherein the vertical doping regions are arranged on the outer side surfaces of the vertical dielectric structure.

3. The silicon carbide super junction power device according to claim 1, characterized in that: Also includes: A high epitaxial layer, arranged on a side of the nth epitaxial layer away from the silicon carbide substrate; A plurality of gate electrodes and a plurality of pseudo electrodes, a plurality of first gate dielectric layers and a plurality of second gate dielectric layers, wherein the plurality of gate electrodes and the plurality of pseudo electrodes are arranged in the high epitaxial layer at intervals; The first gate dielectric layer is disposed on a side wall of the gate electrode, and the second gate dielectric layer is disposed on a side wall of the pseudo electrode; A first dielectric structure is disposed at the bottom of the gate electrode; The shielding structure is arranged on a side of the first dielectric structure close to the silicon carbide substrate.

4. The silicon carbide super junction power device according to claim 3, characterized in that: Also includes: A second dielectric structure is disposed at the bottom of the pseudo electrode, and a bottom surface of the second dielectric structure is connected to the vertical dielectric structure; The body region includes a vertical portion and a horizontal portion connected to each other, wherein the vertical portion is arranged on the outer side of the second gate dielectric layer and the second dielectric structure, the horizontal portion extends to the side of the vertical dielectric structure, and the vertical doping region is connected to the horizontal portion.

5. The silicon carbide super junction power device according to claim 4, characterized in that: Also includes: A plurality of source regions and a plurality of base regions, wherein the source regions and the base regions are both arranged between the vertical portion of the body region and the first gate dielectric layer; The base region is arranged on a side of the source region close to the silicon carbide substrate, and the upper surface of the source region is flush with the upper surface of the high epitaxial layer; A plurality of first interlayer dielectric layers and a plurality of second interlayer dielectric layers, wherein the first interlayer dielectric layers are arranged on top of the gate electrode, and the second interlayer dielectric layers are arranged on top of the pseudo electrode; A source electrode, disposed on a side of the high epitaxial layer away from the silicon carbide substrate; The drain electrode is arranged at the bottom of the silicon carbide substrate.

6. The silicon carbide super junction power device according to claim 3, characterized in that: Also includes at least one of the following: The orthographic projection of the first dielectric structure on the silicon carbide substrate falls within the orthographic projection of the shielding structure on the silicon carbide substrate; Along the direction perpendicular to the silicon carbide substrate, the height of the nth horizontal doping region is not less than the height of the n-1th horizontal doping region; along the vertical downward direction of the silicon carbide substrate, the interval between the nth horizontal doping region and the n-1th horizontal doping region is equal or increases.

7. A method for manufacturing a silicon carbide super junction power device, characterized in that: include: S1: Fabricating the first epitaxial layer on one side of the silicon carbide substrate; Under the mask of the first mask plate, forming a first horizontal doping region arranged in an array on the top of the first epitaxial layer by ion implantation, so that the upper surface of the first horizontal doping region is flush with the upper surface of the first epitaxial layer; S2: manufacturing an nth epitaxial layer on the first epitaxial layer, and forming an nth horizontal doping region arranged in an array on the top of the nth epitaxial layer by ion implantation; repeating this step until a set number of epitaxial layers is obtained, wherein n is a positive integer greater than 1; S3: patterning the horizontal doping regions located in the same column to obtain vertical grooves, so that the vertical grooves extend into the first horizontal doping region; S4: manufacturing a vertical dielectric structure in the vertical trench.

8. The manufacturing method according to claim 7, characterized in that: After patterning the horizontal doping regions located in the same column to obtain vertical trenches, and before manufacturing the vertical dielectric structure in the vertical trenches, the manufacturing method further includes: Ion implantation is performed on the side of the vertical trench to form a vertical doping region, so that the vertical doping region passes through the horizontal doping region in the same column and is connected to the horizontal portion of the body region.

9. The manufacturing method according to claim 7, characterized in that: After obtaining the set number of epitaxial layers, patterning the horizontal doping regions located in the same column, and before obtaining the vertical grooves, the manufacturing method further includes: S201: manufacturing a high epitaxial layer on a side of the nth epitaxial layer away from the silicon carbide substrate, and performing ion implantation in the high epitaxial layer above the junction region between adjacent horizontal doping regions to sequentially form a base region and a source region, so that an upper surface of the source region is flush with an upper surface of the high epitaxial layer; S202: patterning the high epitaxial layer under a mask of a second mask plate to obtain first trenches and second trenches arranged at intervals, so that the first trenches pass through the base region and the source region, the bottom of the first trenches is lower than the lower surface of the base region, and the second trenches expose the side surfaces of the base region and the source region; S203: performing ion implantation through the first trench and the second trench to form a shielding structure below the bottom of the first trench and a horizontal portion of the body region below the bottom of the second trench; filling the first trench with a dielectric mask, and then performing ion implantation through the side of the second trench to form a vertical portion of the body region; S204: manufacturing a sidewall mask on the side of the second trench.

10. The manufacturing method according to claim 8, characterized in that: After forming the vertical doping region and before manufacturing the vertical dielectric structure in the vertical trench, the manufacturing method further includes: removing the second mask, the dielectric mask and the sidewall mask; And, while manufacturing the vertical dielectric structure in the vertical trench, the manufacturing method further includes: filling a dielectric with a high dielectric constant at the bottom of the first trench and the bottom of the second trench to form a first dielectric structure and a second dielectric structure respectively. And, after manufacturing the vertical dielectric structure in the vertical groove, the manufacturing method further comprises: S5: manufacturing a first gate dielectric layer and a second gate dielectric layer on the sidewalls of the first trench and the second trench respectively; then manufacturing a gate electrode in the first trench and manufacturing a pseudo electrode in the second trench; S6: manufacturing a first interlayer dielectric layer and a second interlayer dielectric layer respectively above the gate electrode and the pseudo electrode; S7: manufacturing a source electrode on a side of the high epitaxial layer away from the silicon carbide substrate, and manufacturing a drain electrode at the bottom of the silicon carbide substrate.

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