Power device and manufacturing method thereof
By using a layered silicon carbide substrate and epitaxial layer in the active region of the power device, and setting up an interconnected metal layer to electrically connect it to the source metal layer, the problem of large on-resistance of the existing power device is solved, and the on-resistance reduction and high-temperature stability are improved.
Patent Information
- Application Number
- CN202510031958.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-09
- Publication Date
- 2025-04-22
AI Technical Summary
Existing power devices have technical problems with large on-resistance.
A power device is used, which includes an active region and a terminal region, which is arranged around the periphery of the active region. The active region includes a layered silicon carbide substrate and an epitaxial layer, a gate layer, an interlayer dielectric layer, an ohmic contact layer and an interconnected metal layer, and the interconnected metal layer is electrically connected to the source metal layer to ensure uniform current conduction.
By increasing the density of the gate layer and removing the gate connections, the on-resistance is reduced, the stability of the power device in high temperature environments is improved, and the on-resistance is reduced by 10% to 25%.
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Figure CN119866036A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular, to a power device and a method for manufacturing the same. Background Art
[0002] The breakdown field strength of silicon carbide can reach 3.5 (MV / cm), which is about 10 times that of silicon. Therefore, the thickness of the silicon carbide epitaxial layer required for withstand voltage is reduced, and it has the characteristics of high withstand voltage, low on-resistance, and low on-thermal resistance. The thermal conductivity of silicon carbide can reach 4.0 (W / cm·K), which is about 3 times that of silicon, and is suitable for high-temperature conditions. The saturated electron drift rate of silicon carbide is about 2 times that of silicon, which can be used in high-frequency applications. Therefore, power electronic systems based on silicon carbide power devices are the development direction of the new generation of power electronic systems.
[0003] However, current power devices still have the technical problem of large on-resistance. Summary of the invention
[0004] In view of the shortcomings of the existing methods, the present application proposes a power device and a manufacturing method thereof, so as to solve the technical problem that the current power devices have a large on-resistance.
[0005] In a first aspect, an embodiment of the present application provides a power device, the power device comprising an active region and a terminal region, the terminal region being arranged around the periphery of the active region, the power device comprising a stacked silicon carbide substrate and a silicon carbide epitaxial layer. The active region comprises:
[0006] A gate layer, the gate layer being arranged on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate; the gate layer comprising first through holes arranged in an array;
[0007] An interlayer dielectric layer, disposed on the outer surface of the gate layer;
[0008] An ohmic contact layer, disposed in the first through hole and located between adjacent interlayer dielectric layers;
[0009] An interconnect metal layer, disposed on a side of the interlayer dielectric layer and the ohmic contact layer away from the silicon carbide substrate, and covering the active area;
[0010] The source metal layer is arranged on a side of the interconnect metal layer away from the silicon carbide substrate and is electrically connected to the interconnect metal layer.
[0011] Optionally, in a plane parallel to the silicon carbide substrate, a shape of the first through hole includes a square or a hexagon.
[0012] Optionally, the interconnect metal layer includes a stacked first metal layer, a second metal layer and a third metal layer, the first metal layer and the second metal layer are sequentially arranged on a side of the ohmic contact layer away from the silicon carbide substrate, and the third metal layer covers the active area; the material of the first metal layer includes titanium, the material of the second metal layer includes titanium nitride, and the material of the third metal layer includes tungsten;
[0013] The material of the ohmic contact layer includes nickel silicide.
[0014] Optionally, the active area further includes:
[0015] A well region arranged in an array on the top of the silicon carbide epitaxial layer, two first conductivity type source regions symmetrically arranged in each of the well regions, and a second conductivity type source region arranged between the two first conductivity type source regions, wherein the upper surfaces of the well region, the first conductivity type source region, and the second conductivity type source region are all flush with the upper surface of the silicon carbide epitaxial layer;
[0016] The lower surface of the ohmic contact layer is in contact with the upper surface of the second conductive type source region and a portion of the upper surface of the first conductive type source region;
[0017] The extension layer is arranged on a side of the second conductive type source region close to the silicon carbide substrate, and the extension layer is located inside the silicon carbide epitaxial layer.
[0018] Optionally, the active region further comprises: a gate dielectric layer and a second insulating layer;
[0019] The gate dielectric layer is disposed on a side of the gate layer close to the well region;
[0020] The second insulating layer is disposed on a portion of the outer surface of the interconnect metal layer.
[0021] Optionally, the terminal area includes:
[0022] A field line ring is arranged inside a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, and an upper surface of the field line ring is flush with an upper surface of the silicon carbide epitaxial layer;
[0023] A first insulating layer is disposed on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate and covers the field line ring;
[0024] A gate line layer, the gate line layer is arranged on a side of the first insulating layer away from the field line ring, and the gate line layer is electrically connected to the gate layer;
[0025] An interlayer dielectric layer is arranged on an outer surface of the gate line layer away from the first insulating layer, the interlayer dielectric layer has a second through hole, and the second through hole exposes a portion of the gate line layer;
[0026] A second insulating layer, disposed on an outer surface of the interlayer dielectric layer, the second insulating layer comprising a third through hole, the third through hole being connected to the second through hole;
[0027] The gate metal layer is disposed on a side of the second insulating layer away from the silicon carbide substrate, and passes through the second through hole and the third through hole to be electrically connected to the gate line layer.
[0028] Optionally, the gate metal layer extends to the active area, and the power device further comprises:
[0029] A third insulating layer, disposed outside the source metal layer and the gate metal layer;
[0030] a fourth insulating layer, disposed on an outer surface of the third insulating layer;
[0031] A drain metal layer is disposed on a side of the silicon carbide substrate away from the silicon carbide epitaxial layer.
[0032] In a second aspect, an embodiment of the present application provides a method for manufacturing the above-mentioned power device, comprising:
[0033] S1: Fabricating a silicon carbide epitaxial layer on one side of a silicon carbide substrate;
[0034] S2: manufacturing a gate layer located in the active area on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, so that a plurality of the gate layers include first through holes arranged in an array; and conformally manufacturing an interlayer dielectric layer on the outer surface of the gate layer;
[0035] S3: manufacturing an ohmic contact layer in the first through hole and between adjacent interlayer dielectric layers, and manufacturing an interconnect metal layer on top of the interlayer dielectric layer and the ohmic contact layer, so that the interconnect metal layer covers the active area;
[0036] S4: manufacturing a source metal layer on a side of the interconnect metal layer away from the silicon carbide substrate, so that the source metal layer is electrically connected to the interconnect metal layer.
[0037] Optionally, while manufacturing a gate layer in the active area on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, a gate line layer in the terminal area is manufactured so that a plurality of the gate layers are electrically connected through the gate line layer.
[0038] Optionally, the method further comprises:
[0039] Manufacturing an array-arranged well region inside a side of the silicon carbide epitaxial layer located in the active area away from the silicon carbide substrate, so that the upper surface of the well region is flush with the upper surface of the silicon carbide epitaxial layer;
[0040] Manufacturing a symmetrically arranged first conductivity type source region inside the well region so that the upper surface of the first conductivity type source region is flush with the upper surface of the well region;
[0041] A second conductive type source region is fabricated in the active region between two first conductive type source regions, so that an upper surface of the second conductive type source region is flush with an upper surface of the first conductive type source region.
[0042] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:
[0043] The gate layer with a plurality of first through holes covers the entire active area, replacing the strip-shaped gate layer in the prior art, and can remove the gate connection line, which is beneficial to increase the area of the channel region.
[0044] In addition, an ohmic contact layer is provided in the first through hole, and an interconnection metal layer is provided on top of the interlayer dielectric layer and the ohmic contact layer, so that the interconnection metal layer can be electrically connected to each ohmic contact layer, and the current can reach any ohmic contact layer in the active area after passing through the interconnection metal layer, and then be transferred to the first conductive type source area and the second conductive type source area. Therefore, by providing an interconnection metal layer and a source metal layer electrically connected, the source current can pass through all ohmic contact layers, so that the conduction current and heat generation are uniform, which is conducive to avoiding or eliminating the risk of power device failure; at the same time, the forward conduction current and heat generation can be made more uniform, thereby improving the stability of the power device in a high temperature environment.
[0045] Furthermore, by increasing the density of the gate layer and eliminating the gate connection line, the density of the well region can also be increased, thereby effectively reducing the on-resistance, for example, reducing the on-resistance by 10% to 25%.
[0046] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0048] Figure 1 A schematic top view of a power device provided in an embodiment of the present application;
[0049] Figure 2 for Figure 1 Schematic diagram of the cross section at AA';
[0050] Figure 3 A schematic diagram of a gate layer provided in an embodiment of the present application;
[0051] Figure 4 A schematic diagram of another gate layer provided in an embodiment of the present application;
[0052] Figure 5 A schematic diagram of a process for manufacturing a power device provided in an embodiment of the present application;
[0053] Figures 6 to 19 This is a structural schematic diagram obtained from each step in a flow diagram for manufacturing a power device provided in an embodiment of the present application.
[0054] Description of reference numerals:
[0055] B-active region; C-terminal region;
[0056] 1-Silicon carbide substrate;
[0057] 2-silicon carbide epitaxial layer; 21-extension layer;
[0058] 311 - well region; 32 - first conductivity type source region; 33 - second conductivity type source region;
[0059] 411 - gate dielectric layer; 42 - gate layer; 421 - first through hole; 43 - gate line layer;
[0060] 5-interlayer dielectric layer;
[0061] 61-ohmic contact layer; 62-interconnect metal layer;
[0062] 71-source metal layer; 72-gate metal layer;
[0063] 8-field line loop;
[0064] 91 - first insulating layer; 92 - second insulating layer; 93 - third insulating layer; 94 - fourth insulating layer;
[0065] 10-Drain metal layer. DETAILED DESCRIPTION
[0066] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.
[0067] It will be understood by those skilled in the art that, unless specifically stated, the "said" and "the" used herein may also include plural forms. It should be further understood that the wording "including" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may refer to the connection relationship between the element and the other element through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".
[0068] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.
[0069] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.
[0070] The descriptions "first conductivity type" and "second conductivity type" used in this application refer to n-type conductivity (i.e., electron conductivity) and p-type conductivity (i.e., hole conductivity), respectively. Specifically, the first conductivity type is n-type conductivity, and the second conductivity type is p-type conductivity; or, the first conductivity type is p-type conductivity, and the second conductivity type is n-type conductivity.
[0071] The present application embodiment provides a power device. The structural diagram of the power device is as follows: Figures 1 to 4 shown.
[0072] like Figure 1 and Figure 2 As shown, the power device includes an active region B and a terminal region C, wherein the terminal region C is arranged around the periphery of the active region B.
[0073] like Figure 2 As shown, the power device includes a silicon carbide substrate 1 and a silicon carbide epitaxial layer 2 which are stacked.
[0074] In this embodiment, the silicon carbide substrate 1 may be an n+ type silicon carbide substrate, and the silicon carbide epitaxial layer 2 may be an n- type silicon carbide epitaxial layer. The doping impurities of the silicon carbide substrate 1 and the silicon carbide epitaxial layer 2 both include nitrogen or phosphorus, and the doping impurities of the silicon carbide substrate 1 and the silicon carbide epitaxial layer 2 may be the same or different, and no specific restrictions are made here. The thickness of the silicon carbide substrate 1 is not less than 100 microns and not more than 500 microns, and the doping concentration is 1*10 18 -1*10 20 / cm 3 The thickness of the silicon carbide epitaxial layer 2 is not less than 1 micron and not more than 50 microns, and the doping concentration is 1*10 14 -1*10 19 / cm 3 .
[0075] like Figure 1 and Figure 2 As shown, the active region B includes: a gate layer 42 , an interlayer dielectric layer 5 and an ohmic contact layer 61 , as well as an interconnect metal layer 62 and a source metal layer 71 .
[0076] The gate layer 42 is disposed on a side of the silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1. The gate layer 42 includes first through holes 421 arranged in an array.
[0077] The interlayer dielectric layer 5 located in the active area B is disposed on the outer surface of the gate layer 42. The interlayer dielectric layer 5 covers the gate layer 42, and can isolate the gate layer 42 from the subsequently manufactured ohmic contact layer 61 and interconnect metal layer 62, effectively preventing the power device from short circuiting.
[0078] The ohmic contact layer 61 is disposed in the first through hole 421 and is located between adjacent interlayer dielectric layers 5 .
[0079] The interconnection metal layer 62 is arranged on a side of the interlayer dielectric layer 5 and the ohmic contact layer 61 away from the silicon carbide substrate 1 , and covers the active area B completely.
[0080] The source metal layer 71 is disposed on a side of the interconnect metal layer 62 away from the silicon carbide substrate 1 , and is electrically connected to the interconnect metal layer 62 .
[0081] In this embodiment, the gate layer 42 having a plurality of first through holes 421 covers the entire active area B, replacing the strip-shaped gate layer in the prior art, and can remove the gate connection line, which is beneficial to increase the area of the channel region.
[0082] In addition, an ohmic contact layer 61 is provided in the first through hole 421, and an interconnection metal layer 62 is provided on the top of the interlayer dielectric layer 5 and the ohmic contact layer 61, so that the interconnection metal layer 62 can be electrically connected to each ohmic contact layer 61, and the current can reach any ohmic contact layer 61 in the active area B after passing through the interconnection metal layer 62, and then be transferred to the first conductive type source area 32 and the second conductive type source area 33. Therefore, by providing an interconnection metal layer 62 and a source metal layer 71 to be electrically connected, the source current can pass through all the ohmic contact layers 61, so that the conduction current and heat generation are uniform, which is conducive to avoiding or eliminating the risk of power device failure; at the same time, the forward conduction current and heat generation can be made more uniform, thereby improving the stability of the power device in a high temperature environment.
[0083] Furthermore, by increasing the density of the gate layer 42 and eliminating the gate connection line, the density of the well region 31 can also be increased, thereby effectively reducing the on-resistance, for example, reducing the on-resistance by 10% to 25%.
[0084] Alternatively, if Figure 3 and Figure 4 As shown, in a plane parallel to the silicon carbide substrate 1 , the shape of the first through hole 421 includes a square or a hexagon.
[0085] In this embodiment, the power device using the hexagonal first through hole 421 and the power device using the square first through hole 421 both have a larger channel area than the power device with a strip-shaped gate layer, which is beneficial to increase the on-current.
[0086] In one embodiment, Figure 3 As shown, the first through hole 421 is in a square shape.
[0087] In another embodiment, Figure 4 As shown, the shape of the first through hole 421 is hexagonal.
[0088] It can be understood that the area of the channel region of the power device using the hexagonal first through hole 421 is larger than the area of the channel region of the power device using the square first through hole 421, further increasing the on-current.
[0089] Optionally, the interconnection metal layer 62 includes a first metal layer (not shown in the figure), a second metal layer (not shown in the figure) and a third metal layer (not shown in the figure), the first metal layer and the second metal layer are sequentially arranged on a side of the ohmic contact layer 61 away from the silicon carbide substrate 1; the third metal layer covers the active area B. The material of the first metal layer includes titanium, the material of the second metal layer includes titanium nitride, and the material of the third metal layer includes tungsten.
[0090] In this embodiment, the first metal layer and the second metal layer are arranged on top of the ohmic contact layer 61, which can facilitate the connection between the third metal layer and the ohmic contact layer 61. The third metal layer is spread over the active area B, so that the source metal layer 71 is connected with each ohmic contact layer 61, so that the conduction current and heat generation are uniform, which is conducive to avoiding or eliminating the risk of power device failure.
[0091] Optionally, the thickness of the first metal layer is not less than 10 nanometers and not more than 500 nanometers; the thickness of the second metal layer is not less than 10 nanometers and not more than 200 nanometers; the thickness of the third metal layer is not less than 0.5 micrometers and not more than 2 micrometers.
[0092] In this embodiment, the thickness of the third metal layer is within the above range, and can be easily laid on the top to facilitate the connection between the source metal layer 71 and the ohmic contact layer 61. If the thickness of the third metal layer 62 is less than 0.5 microns, the third metal layer 62 is easily disconnected and cannot be connected to any ohmic contact layer 61; if the thickness of the third metal layer 62 is greater than 2 microns, the thickness of the third metal layer 62 is too large, resulting in a large on-resistance.
[0093] Optionally, the material of the ohmic contact layer 61 includes nickel silicide.
[0094] In this embodiment, the thickness of the nickel silicide is not less than 50 nanometers and not more than 500 nanometers.
[0095] Alternatively, if Figure 2 As shown, the active area B also includes: a well area 31 arranged in an array on the top of the silicon carbide epitaxial layer 2, two first conductivity type source areas 32 symmetrically arranged in each well area 31, and a second conductivity type source area 33 arranged between the two first conductivity type source areas 32. The upper surfaces of the well area 31, the first conductivity type source area 32, and the second conductivity type source area 33 are all flush with the upper surface of the silicon carbide epitaxial layer 2.
[0096] The lower surface of the ohmic contact layer 61 contacts the upper surface of the second conductive type source region 33 and a portion of the upper surface of the first conductive type source region 32 .
[0097] The active region B further includes an extension layer 21 . The extension layer 21 is disposed on a side of the second conductive type source region 33 close to the silicon carbide substrate 1 and is located inside the silicon carbide epitaxial layer 2 .
[0098] In this embodiment, the well region 31 is laid in the active region B, and the first conductive type source region 32 is symmetrically arranged in the well region 31. When the current is turned on, the current can flow to the drain metal layer 10 through the well region 31 through the two symmetrically arranged first conductive type source regions 32, thereby making the forward conductive current generate heat more uniformly, which is beneficial to improving the stability of the power device when working at high temperatures. The ohmic contact layer 61 contacts the upper surface of the second conductive type source region 33 to form an ohmic contact. The ohmic contact layer 61 contacts the upper surface of the first conductive type source region 32 to form an ohmic contact. After passing through the interconnect metal layer 62, the current reaches each ohmic contact layer 61, and then is transferred to the first conductive type source region 32 and the second conductive type source region 33.
[0099] The extension layer 21 is lightly doped with the first conductivity type, and the doping concentration is higher than that of the silicon carbide epitaxial layer 2. The extension layer 21 allows the current to be distributed more evenly when it reaches the bottom of the well region 31. The current path is filled with the silicon carbide epitaxial layer 2 in advance, and the area between adjacent well regions 31 has a large resistance. The extension layer 21 can reduce the on-resistance here.
[0100] It can be understood that the well region 31 is lightly doped with the second conductivity type, the first conductivity type source region 32 is heavily doped, and the second conductivity type source region 33 is heavily doped.
[0101] It should be noted that the well region 31 , the first conductivity type source region 32 , and the second conductivity type source region 33 are all arranged corresponding to the shape of the first through hole 421 of the gate layer 42 .
[0102] Optionally, the active region B further includes: a gate dielectric layer 41 and a second insulating layer 92 .
[0103] The gate dielectric layer 41 is disposed on a side of the gate layer 42 close to the well region 31. The second insulating layer 92 is disposed on a portion of the outer surface of the interconnect metal layer 62.
[0104] In this embodiment, the gate dielectric layer 41 can isolate the gate layer 42 and the well region 31 to prevent short circuit. The second insulating layer 92 is disposed on the outer surface of a portion of the interconnect metal layer 62 to isolate the interconnect metal layer 62 and the gate metal layer 72 to prevent short circuit.
[0105] Alternatively, if Figure 2 As shown, the terminal region C includes a field line ring 8 , a first insulating layer 91 and a gate line layer 43 , as well as an interlayer dielectric layer 5 , a second insulating layer 92 and a gate metal layer 72 .
[0106] The field line ring 8 is disposed inside a side of the silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1 , and an upper surface of the field line ring 8 is flush with an upper surface of the silicon carbide epitaxial layer 2 .
[0107] The first insulating layer 91 is disposed on a side of the silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1 and covers the field line ring 8 .
[0108] The gate line layer 43 is disposed on a side of the first insulating layer 91 away from the field line ring 8 , and the gate line layer 43 is electrically connected to the gate layer 42 .
[0109] The interlayer dielectric layer 5 is disposed on the outer surface of the gate line layer 43 . The interlayer dielectric layer 5 has a second through hole. The second through hole exposes a portion of the gate line layer 43 .
[0110] The second insulating layer 92 is disposed on the outer surface of the interlayer dielectric layer 5 . The second insulating layer includes a third through hole, and the third through hole is connected to the second through hole.
[0111] The gate metal layer 72 is disposed on a side of the second insulating layer 92 away from the silicon carbide substrate 1 , and is electrically connected to the gate line layer 43 through the second through hole and the third through hole.
[0112] In the related art, an area including a gate metal layer 72 and a gate line layer 43 needs to be provided in the active area B of the power device. No well area (channel) is arranged in this area, and it does not participate in the forward current flow of the power device. Therefore, the area of the power device is not fully utilized, and the on-resistance of the power device cannot be effectively reduced.
[0113] In this embodiment, the gate line layer 43 is disposed in the terminal region C, so that the area occupied by the gate line layer 43 can be saved, thereby increasing the density of the well region (channel), which is beneficial to improving the current conduction capability.
[0114] Optionally, the doping concentration range of the field line loop is not less than 1*10 18 per cubic centimeter and not more than 1*10 19 The manufacturing depth is not less than 0.3 microns and not more than 0.6 microns per cubic centimeter.
[0115] Alternatively, if Figure 2 As shown, the gate metal layer 72 extends to the active region B, and the power device further includes: a third insulating layer 93 , a fourth insulating layer 94 and a drain metal layer 10 .
[0116] The third insulating layer 93 is disposed outside the source metal layer 71 and the gate metal layer 72 .
[0117] The fourth insulating layer 94 is disposed on the outer surface of the third insulating layer 93 .
[0118] The drain metal layer 10 is disposed on a side of the silicon carbide substrate 1 away from the silicon carbide epitaxial layer 2 .
[0119] In this embodiment, the silicon carbide substrate 1 may be an n+ type silicon carbide substrate, and the silicon carbide epitaxial layer 2 may be an n- type epitaxial layer; the drain metal layer 10 forms an ohmic contact with the silicon carbide substrate 1, which is beneficial to reduce the forward conduction resistance. The third insulating layer 93 and the fourth insulating layer 94 can isolate the source metal layer 71 from the gate metal layer 72. The material of the third insulating layer 93 includes at least one of oxide, nitride and oxynitride. The material of the fourth insulating layer 94 includes polyimide. The fourth insulating layer 94 can better isolate water vapor.
[0120] Based on the same inventive concept, the present application embodiment provides a method for manufacturing the above-mentioned power device, and the flow chart of the method is as follows Figure 5 As shown, the method includes steps S1 to S4, which are specifically as follows:
[0121] S1: a silicon carbide epitaxial layer 2 is produced on one side of a silicon carbide substrate 1 .
[0122] In this embodiment, a silicon carbide epitaxial layer 2 is fabricated on one side of a silicon carbide substrate 1 by epitaxial growth, and the obtained structure is as follows: Figure 6 shown.
[0123] Exemplarily, the silicon carbide substrate 1 is heavily doped with the first conductivity type, and the silicon carbide epitaxial layer 2 is lightly doped with the first conductivity type. The thickness of the silicon carbide substrate 1 ranges from 100 microns to 500 microns, and the doping concentration is 1*10 18 -1*10 20 / cm 3 The thickness of the silicon carbide epitaxial layer 2 ranges from 1 micron to 50 microns, and the doping concentration is 1*10 14 -1*10 19 / cm 3 The doping impurities of the silicon carbide substrate 1 and the silicon carbide epitaxial layer 2 both include nitrogen or phosphorus. In this embodiment, the doping impurity is nitrogen.
[0124] Optionally, after step S1 and before step S2, the method further includes:
[0125] An array of well regions 31 is fabricated inside the silicon carbide epitaxial layer 2 located in the active region B on a side away from the silicon carbide substrate 1, so that the upper surface of the well region 31 is flush with the upper surface of the silicon carbide epitaxial layer 2. The obtained structure is as follows: Figure 7 shown.
[0126] A symmetrically arranged first conductive type source region 32 is fabricated inside the well region 31 so that the upper surface of the first conductive type source region 32 is flush with the upper surface of the well region 31. The obtained structure is as follows: Figure 8 shown.
[0127] A second conductive type source region 33 located in the active region B is fabricated between the two first conductive type source regions 32 so that the upper surface of the second conductive type source region 33 is flush with the upper surface of the first conductive type source region 32. The obtained structure is as follows: Fig. 9 shown.
[0128] In this embodiment, a mask is used to define the injection area (located on the side of the silicon carbide epitaxial layer 2 in the active area B away from the silicon carbide substrate 1) by photolithography and etching on the mask layer (not shown in the figure), and the well region 31 is formed by injection at a temperature between 200 degrees Celsius and 500 degrees Celsius. Since the well region 31 is formed by injection at high temperature, the material of the mask layer is selected as an oxide that is relatively stable at high temperature; the thickness of the mask layer is determined by the type, energy and dose of the injected element to ensure that the element will not penetrate the mask layer and enter the silicon carbide epitaxial layer 2 during injection. The well region 31 is lightly doped with the second conductivity type. The doping concentration range of the well region 31 is 5*10 16 per cubic centimeter to 5*10 17 The depth of the well region 31 ranges from 0.8 micrometers to 1.2 micrometers. The doping elements of the well region 31 include boron (B), aluminum (Al), etc.
[0129] The first conductive type source region 32 is heavily doped, and the doping concentration range is not less than 1*10 18 per cubic centimeter and not more than 1*10 19 The depth of the fabrication is not less than 0.2 micrometers and not more than 0.4 micrometers per cubic centimeter. The doping type of the first conductive type source region 32 includes nitrogen or phosphorus.
[0130] The second conductive type source region 33 is heavily doped, and the doping concentration range is not less than 1*10 18 per cubic centimeter and not more than 1*10 19 The depth of the second conductive type source region 33 is not less than 0.3 micrometers and not more than 0.6 micrometers per cubic centimeter. The lower surface of the second conductive type source region 33 is closer to the silicon carbide substrate 1 than the lower surface of the first conductive type source region 32. The doping elements of the second conductive type source region 33 include boron (B), aluminum (Al), etc.
[0131] Optionally, in step 3, a second conductivity type source region 33 located in the active region B is manufactured between the two first conductivity type active regions 32, and the method further comprises:
[0132] While the second conductivity type source region 33 is formed between the two first conductivity type source regions 32 in the active region B, a field line ring 8 is formed on the surface of the silicon carbide epitaxial layer 2 in the terminal region C away from the silicon carbide substrate 1 .
[0133] Optionally, after the step of manufacturing the second conductivity type source region 33 located in the active region B between the two first conductivity type source regions 32 and before step S2, the method further comprises:
[0134] In the active region B, an extension layer 21 is fabricated on the side of the well region 31 close to the silicon carbide substrate 1, and the resulting structure is as follows: Fig.10 shown.
[0135] In the terminal region C, a first insulating layer 91 is fabricated on the side of the field line loop 8 away from the silicon carbide substrate 1, and the obtained structure is as follows: Fig.11 shown.
[0136] In the active region B, an initial gate dielectric layer is manufactured on the upper surface of the structure obtained after manufacturing the second conductive type source region 33, and the obtained structure is as follows: Fig.12 shown.
[0137] In this embodiment, the extension layer 21 is formed by photolithography on a mask layer (not shown) through a mask plate to define an implantation region (the implantation region is located on the side of the silicon carbide epitaxial layer 2 in the active region B away from the silicon carbide substrate 1), and implanted at a high temperature (200°C to 500°C). Both the extension layer 21 and the silicon carbide epitaxial layer 2 are lightly doped with the first conductivity type, and the doping concentration of the extension layer 21 is not less than 5*10 15 per cubic centimeter and not more than 2*10 16 The doping depth is not less than 0.8 microns and not more than 2 microns per cubic centimeter. The extension layer 21 is lightly doped with the first conductivity type, and the doping type of the extension layer 21 includes nitrogen or phosphorus. The doping concentration of the extension layer 21 is higher than that of the silicon carbide epitaxial layer 2. The extension layer 21 allows the current to be distributed more evenly when it reaches the bottom of the well area 31. The current path is filled with the silicon carbide epitaxial layer 2 in advance, and the area between adjacent well areas 31 has a large resistance. The extension layer 21 can reduce the on-resistance here.
[0138] The first insulating layer 91 is obtained by photolithography on the dielectric layer through a mask, and is disposed in the terminal region C. The material of the first insulating layer 91 includes oxide. The thickness of the first insulating layer 91 is set according to the withstand voltage of the terminal region C. Exemplarily, the thickness of the first insulating layer 91 is not less than 0.1 micrometers and not more than 2 micrometers.
[0139] The initial gate dielectric layer uses oxygen and silicon carbide to form silicon dioxide in a high temperature environment, and the oxidation temperature is not less than 1200°C and not higher than 1400°C. The thickness of the initial gate dielectric layer is not less than 10 nanometers and not more than 100 nanometers. In order to ensure the compactness and voltage resistance of the initial gate dielectric layer, it is necessary to use N-doped annealing to reduce the interface state density, improve the carrier mobility, and thus reduce the channel resistance.
[0140] S2: A gate layer 42 located in the active area B is manufactured on the side of the silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1, so that the gate layer 42 includes first through holes arranged in an array. The obtained structure is as follows: Fig.13 As shown; an interlayer dielectric layer 5 is conformally manufactured on the outer surface of the gate layer 42.
[0141] In this embodiment, the gate layer 42 is formed by photolithography on the initial gate layer using a mask, and the thickness of the gate layer 42 is not less than 0.1 micrometer and not more than 1 micrometer. The material of the gate layer 42 includes P-doped polysilicon or metal.
[0142] Optionally, step S2 includes: manufacturing a gate layer 42 located in the active area B on the side of the silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1, and manufacturing a gate line layer 43 located in the terminal area C, so that the gate layer 42 is electrically connected to the gate line layer 43.
[0143] In this embodiment, the gate line layer 43 is disposed in the terminal region C, which can save the area occupied by the gate line layer 43 in the active region B, thereby increasing the density of the well region (channel), which is beneficial to improving the current conduction capability.
[0144] Optionally, in step S2, an interlayer dielectric layer 5 is manufactured on the outer surface of the gate layer 42, including:
[0145] An initial interlayer dielectric layer is manufactured on the surface of the structure obtained after manufacturing the gate layer 42 , and the initial interlayer dielectric layer covers the active area B and the terminal area C.
[0146] The initial interlayer dielectric layer not covering the surface of the gate layer 42 in the active region B is removed to form an interlayer dielectric layer 5, and then the initial gate dielectric layer not covered by the gate layer 42 and the interlayer dielectric layer 5 in the active region B is removed to form a gate dielectric layer 41. The obtained structural schematic diagram is shown in FIG. Fig.14 shown.
[0147] In this embodiment, the gate dielectric layer 42 covers the well region 31 and a portion of the first conductivity type source region 32 .
[0148] S3 : manufacturing an ohmic contact layer 61 between the interlayer dielectric layers 5 , and manufacturing an interconnection metal layer 62 on a side of the interlayer dielectric layer 5 and the ohmic contact layer 61 away from the silicon carbide substrate 1 .
[0149] In this embodiment, the ohmic contact layer 61 is formed by ohmic contact metal deposition, rapid thermal annealing (RTA), and metal stripping on the insulating layer. The interconnection metal layer 62 covers the active area B, so the interconnection metal layer 62 can be electrically connected to each ohmic contact layer 61, and the current can reach any ohmic contact layer 61 in the active area B after passing through the interconnection metal layer 62, and then be transferred to the first conductive type source area 32 and the second conductive type source area 33, which can improve the source current conduction and heat generation uniformity, and improve the operation stability of the device under high temperature conditions.
[0150] Optionally, after step S3 and before step S4, the method further includes:
[0151] An initial second insulating layer is manufactured on a side of the interconnect metal layer 62 away from the silicon carbide substrate 1 , and the initial second insulating layer extends to the terminal region C.
[0152] The initial second insulating layer in the area of the source metal layer 71 to be subsequently manufactured is removed, and the interlayer dielectric layer 5 and the initial second insulating layer on the top of the gate line layer 43 are removed to obtain the second insulating layer 92 .
[0153] In this embodiment, the structural diagram after obtaining the second insulating layer 92 is as follows: Fig.16 The second insulating layer 92 can isolate the interconnect metal layer 62 and the gate metal layer 72, which is helpful to avoid short circuit between them.
[0154] S4 : manufacturing a source metal layer 71 on a side of the interconnect metal layer 62 away from the silicon carbide substrate 1 .
[0155] In this embodiment, the source metal layer 71 is formed by depositing metal and photolithography. The source metal layer 71 is a stacked metal layer, and the materials of each layer of the stacked metal layer can include titanium, titanium nitride and aluminum, or include titanium, titanium nitride and aluminum copper, or include titanium, titanium nitride and aluminum silicon copper. Among them, the thickness of titanium is not less than 10 nanometers and not more than 500 nanometers, the thickness of titanium nitride is not less than 10 nanometers and not more than 200 nanometers, and the thickness of aluminum, aluminum copper and aluminum silicon copper is not less than 1 micrometer and not more than 8 micrometers.
[0156] The source metal layer 71 is in direct contact with the interconnect metal layer 62, and the source current flows through the source metal layer 71, the interconnect metal layer 62 and the ohmic contact layer 61 to reach all the first conductive type source regions 32 and the second conductive type source regions 33 connected in parallel in the active region B, so as to realize the control of the source current. It can be understood that the source metal layer 71 is the source pinning position for subsequent electrical testing or the packaging source wire bonding position.
[0157] Optionally, after step S4, the method further comprises: manufacturing a gate metal layer 72 on a side of the second insulating layer 92 away from the silicon carbide substrate 1, wherein the gate metal layer 72 is electrically connected to the gate line layer 43, and the obtained structure is as follows: Fig.17 shown.
[0158] In this embodiment, the gate metal layer 72 extends to part of the active area B. The gate metal layer 72 is formed by depositing metal and photolithography. The gate metal layer 72 is a stacked metal layer, and the materials of each layer of the stacked metal layer may include titanium, titanium nitride and aluminum, or include titanium, titanium nitride and aluminum copper, or include titanium, titanium nitride and aluminum silicon copper. Among them, the thickness of titanium is not less than 10 nanometers and not more than 500 nanometers, the thickness of titanium nitride is not less than 10 nanometers and not more than 200 nanometers, and the thickness of aluminum, aluminum copper and aluminum silicon copper is not less than 1 micrometer and not more than 8 micrometers.
[0159] The gate metal layer 72 is electrically connected to the gate line layer 43, and the gate current flows through the gate metal layer 72 and the gate line layer 43 to reach all the parallel gate layers 42 in the active area B, thereby controlling the gate current. It can be understood that the gate metal layer 72 is the gate needle insertion position for subsequent electrical testing or the packaging gate wire bonding position.
[0160] Optionally, after manufacturing the gate metal layer 72 on the side of the second insulating layer 92 away from the silicon carbide substrate 1, the method further comprises: manufacturing a third insulating layer 93 on the outer surface of the source metal layer 71 and the gate metal layer 72. The obtained structural schematic diagram is shown in FIG. Fig.18 shown.
[0161] In this embodiment, the third insulating layer 93 is formed by photolithography on the initial third insulating layer formed by deposition using a mask. The third insulating layer 93 covers the side and part of the upper surface of the source metal layer 71 and the gate metal layer 72. The third insulating layer 93 can play the role of insulating and isolating the source metal layer 71 and the gate metal layer 72 and moisture-proofing. The material of the third insulating layer 93 includes at least one of oxide, nitride and oxynitride. The thickness of the third insulating layer 93 is not less than 0.1 micrometer and not more than 10 micrometers.
[0162] Optionally, after manufacturing the third insulating layer 93 on the outer surface of the source metal layer 71 and the gate metal layer 72, the method further includes: manufacturing a fourth insulating layer 94 on the outer surface of the third insulating layer 93. The obtained structural schematic diagram is shown in FIG. Fig.19 shown.
[0163] In this embodiment, the fourth insulating layer 94 is formed by photoresist spin coating, photolithography, and baking and curing. The fourth insulating layer 94 covers the surface of the third insulating layer 93, and can further insulate and isolate the source metal layer 71 and the gate metal layer 72. The material of the fourth insulating layer 94 includes polyimide. The thickness of the fourth insulating layer 94 is not less than 1 micron and not more than 20 microns. The fourth insulating layer 94 can be conducive to water vapor protection.
[0164] Optionally, a drain metal layer 10 is fabricated on a side of the silicon carbide substrate 1 away from the silicon carbide epitaxial layer 2, and the obtained structure is as follows: Figure 2 shown.
[0165] In this embodiment, the drain metal layer 10 is formed by thinning the back side of the silicon carbide substrate 1, evaporating the ohmic contact metal, annealing, and drain metal evaporation, wherein the annealing is generally laser annealing or rapid thermal annealing (RTA). The material of the drain metal layer 10 includes stacked nickel silicide, titanium, nickel and silver. The thickness of the nickel silicide is not less than 50 nanometers and not more than 500 nanometers, the thickness of the titanium is not less than 0.1 micrometer and not more than 2 micrometers, the thickness of the nickel is not less than 0.1 micrometer and not more than 1.5 micrometers, and the thickness of the silver is not less than 0.5 micrometer and not more than 3 micrometers. After the silicon carbide substrate 1 is thinned, the thickness of the silicon carbide substrate 1 can be reduced, which is beneficial to reducing the forward on-resistance and heat generation, and is also beneficial to reducing the volume of the subsequent packaged power device.
[0166] It can be understood that the drain metal layer 10 is the location where the metal test carrier is contacted during electrical testing and the location where the conductive frame is connected during packaging.
[0167] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, changed, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, changed, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the related art that are similar to those disclosed in this application may also be alternated, changed, rearranged, decomposed, combined, or deleted.
[0168] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0169] The terms "first", "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.
[0170] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0171] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.
[0172] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.
Claims
1. A power device, comprising an active region and a terminal region, wherein the terminal region is disposed around the periphery of the active region, characterized in that: include: A stacked silicon carbide substrate and a silicon carbide epitaxial layer; The active region comprises: A gate layer, the gate layer being arranged on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate; the gate layer comprising first through holes arranged in an array; An interlayer dielectric layer, disposed on the outer surface of the gate layer; An ohmic contact layer, disposed in the first through hole and located between adjacent interlayer dielectric layers; An interconnect metal layer, disposed on a side of the interlayer dielectric layer and the ohmic contact layer away from the silicon carbide substrate, and covering the active area; The source metal layer is arranged on a side of the interconnect metal layer away from the silicon carbide substrate and is electrically connected to the interconnect metal layer.
2. The power device according to claim 1, characterized in that: The method comprises: in a plane parallel to the silicon carbide substrate, a shape of the first through hole comprises a square or a hexagon.
3. The power device according to claim 1, characterized in that: Include at least one of the following: The interconnection metal layer comprises a stacked first metal layer, a second metal layer and a third metal layer, the first metal layer and the second metal layer are sequentially arranged on a side of the ohmic contact layer away from the silicon carbide substrate, and the third metal layer covers the active area; the material of the first metal layer comprises titanium, the material of the second metal layer comprises titanium nitride, and the material of the third metal layer comprises tungsten; The material of the ohmic contact layer includes nickel silicide.
4. The power device according to claim 1, characterized in that: The active region further comprises: A well region arranged in an array on the top of the silicon carbide epitaxial layer, two first conductivity type source regions symmetrically arranged in each of the well regions, and a second conductivity type source region arranged between the two first conductivity type source regions, wherein the upper surfaces of the well region, the first conductivity type source region, and the second conductivity type source region are all flush with the upper surface of the silicon carbide epitaxial layer; The lower surface of the ohmic contact layer is in contact with the upper surface of the second conductive type source region and a portion of the upper surface of the first conductive type source region; The extension layer is arranged on a side of the second conductive type source region close to the silicon carbide substrate, and the extension layer is located inside the silicon carbide epitaxial layer.
5. The power device according to claim 4, characterized in that: The active region further comprises: a gate dielectric layer and a second insulating layer; The gate dielectric layer is disposed on a side of the gate layer close to the well region; The second insulating layer is disposed on a portion of the outer surface of the interconnect metal layer.
6. The power device according to claim 1, characterized in that: The terminal area includes: A field line ring is arranged inside a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, and an upper surface of the field line ring is flush with an upper surface of the silicon carbide epitaxial layer; A first insulating layer is disposed on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate and covers the field line ring; A gate line layer, the gate line layer is arranged on a side of the first insulating layer away from the field line ring, and the gate line layer is electrically connected to the gate layer; An interlayer dielectric layer is disposed on the outer surface of the gate line layer, the interlayer dielectric layer has a second through hole, and the second through hole exposes a portion of the gate line layer; A second insulating layer, disposed on an outer surface of the interlayer dielectric layer, the second insulating layer comprising a third through hole, the third through hole being connected to the second through hole; The gate metal layer is disposed on a side of the second insulating layer away from the silicon carbide substrate, and passes through the second through hole and the third through hole to be electrically connected to the gate line layer.
7. The power device according to claim 6, characterized in that: The gate metal layer extends to the active area, and the power device further includes: A third insulating layer, disposed outside the source metal layer and the gate metal layer; a fourth insulating layer, disposed on an outer surface of the third insulating layer; A drain metal layer is disposed on a side of the silicon carbide substrate away from the silicon carbide epitaxial layer.
8. A method for manufacturing a power device according to any one of claims 1 to 7, characterized in that: include: S1: Fabricating a silicon carbide epitaxial layer on one side of a silicon carbide substrate; S2: manufacturing a gate layer located in the active area on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, so that the gate layer includes first through holes arranged in an array; and conformally manufacturing an interlayer dielectric layer on the outer surface of the gate layer; S3: manufacturing an ohmic contact layer in the first through hole and between adjacent interlayer dielectric layers, and manufacturing an interconnect metal layer on top of the interlayer dielectric layer and the ohmic contact layer, so that the interconnect metal layer is spread throughout the active area; S4: manufacturing a source metal layer on a side of the interconnect metal layer away from the silicon carbide substrate, so that the source metal layer is electrically connected to the interconnect metal layer.
9. The method according to claim 8, characterized in that In step S2, it includes: While manufacturing a gate layer located in the active area on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, a gate line layer located in the terminal area is manufactured so that the gate layer is electrically connected to the gate line layer.
10. The method according to claim 8, characterized in that After step S1 and before step S2, the method further includes: Manufacturing an array-arranged well region inside a side of the silicon carbide epitaxial layer located in the active area away from the silicon carbide substrate, so that the upper surface of the well region is flush with the upper surface of the silicon carbide epitaxial layer; Manufacturing a symmetrically arranged first conductivity type source region inside the well region so that the upper surface of the first conductivity type source region is flush with the upper surface of the well region; A second conductive type source region is fabricated in the active region between two first conductive type source regions, so that an upper surface of the second conductive type source region is flush with an upper surface of the first conductive type source region.