A SiC MOSFET device with a shallow P+ structure and its manufacturing process

Abstract

The present invention relates to the field of MOS semiconductor technology, and discloses a SiC MOSFET device with a shallow P+ structure, which includes a drain, a gate, a gate oxide layer, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a side P+ layer, an N well layer, and a P well layer. A groove is etched on the surface of the semiconductor epitaxial layer, wherein the source electrode is embedded in the semiconductor epitaxial layer through the groove, and the cross-sectional height of the source electrode is the same as that of the semiconductor epitaxial layer; a lower covering P+ layer is further provided inside the N drift layer and below the P well layer, and the lower covering P+ layer is in contact with the side P+ layer. In the present invention, the low-doped N layer can guide the charge carriers to flow along a more effective path, reducing the current crowding effect. This structure helps to enhance the conductance modulation effect, enabling a lower on-resistance to be maintained even under high voltage conditions. The low-doped N layer can help to homogenize the electric field distribution, especially in high-voltage applications.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and particularly to a SiC MOSFET device with a shallow P+ structure and its manufacturing process. Background Art

[0002] In a SiC MOSFET, the shallow P+ structure generally refers to forming a shallowly doped P+ layer under or near the gate through ion implantation or diffusion processes. This P+ layer does not contact the P-well layer but is located inside the N-drift layer, near the bottom of the gate. Its main purpose is to optimize the electric field distribution, increase the breakdown voltage, reduce the on-resistance, and improve other key performance indicators.

[0003] A prior patent discloses a SiC MOSFET structure with a shallow P+ structure (publication number CN115799303A). Based on the conventional planar SiC MOSFET structure, a P-type doped layer with a relatively high concentration is diffused directly below the N+ source region. In the technology disclosed in this patent, local overheating occurs under high-voltage environments, which increases the likelihood of non-uniform electric field distribution. At this time, when the device is under transient overvoltage conditions, it is extremely prone to breakdown due to avalanche. Summary of the Invention

[0004] The main technical problem to be solved by the present invention is to provide a SiC MOSFET device with a shallow P+ structure and its manufacturing process, which solves the problems in the above background art.

[0005] To solve the above technical problem, according to one aspect of the present invention, more specifically, a SiC MOSFET device with a shallow P+ structure is provided, including a drain, a gate, a gate oxide layer, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N-substrate layer, an N-drift layer, a side P+ layer, an N-well layer, and a P-well layer. A groove is etched on the surface of the semiconductor epitaxial layer, and the source electrode is embedded in the semiconductor epitaxial layer through this groove, and the cross-sectional height of the source electrode is the same as that of the semiconductor epitaxial layer.

[0006] A lower covering P+ layer is further provided inside the N-drift layer and below the P-well layer, and the lower covering P+ layer is in contact with the side P+ layer.

[0007] Furthermore, two symmetrically arranged low-doped N layers are formed by ion implantation at the inner bottom side of the N-drift layer, and an opening for charge flow is formed between the two low-doped N layers.

[0008] Furthermore, a number of doping media are doped inside the N-drift layer and between the drain and the gate. The distance between the doping media is equal, and the doping media inside the N-drift layer are distributed in an inverted triangular shape.

[0009] Further, a centered P+ layer that does not contact the P well layer is formed by ion implantation inside the N drift layer and under the gate.

[0010] Further, the cross-sectional width of the centered P+ layer is not less than the width of the opening formed between the two low-doped N layers.

[0011] A preparation process of a SiC MOSFET device with a shallow P+ structure includes:

[0012] S1. Select a semiconductor epitaxial layer that passes quality inspection, and form a low-doped N layer and a centered P+ layer by ion implantation;

[0013] S2. Inside the N drift layer, layer by layer doping medium is incorporated to make the doping medium distributed in an inverted triangular shape;

[0014] S3. Perform short-circuit performance detection on the formed SiC MOSFET device, and judge whether the performance of the SiC MOSFET device meets the standard according to the short-circuit detection data.

[0015] Further, in step S3, according to the stable value of the drain-source current after the SiC MOSFET device is short-circuited, the applied drain-source voltage, and the magnitude of the threshold voltage, it is determined whether the performance of the SiC MOSFET device meets the standard. Then there is:

[0016]

[0017] In the formula, represents the condition coefficient for the performance of the detected SiC MOSFET device to meet the standard, represents the stable value of the drain-source current after the SiC MOSFET device is short-circuited, represents the magnitude of the applied drain-source short-circuit voltage, represents the magnitude of the threshold voltage of the device.

[0018] Further, when it indicates that the performance of the detected SiC MOSFET device meets the standard;

[0019] When it indicates that the performance of the detected SiC MOSFET device does not meet the standard.

[0020] A SiC MOSFET device with a shallow P+ structure and its preparation process provided by the present invention, compared with the prior art, the effects obtained by this method are:

[0021] 1. In the present invention, the low-doped N layer can guide charge carriers to flow along a more effective path, reducing the current crowding effect. This structure helps to enhance the conductance modulation effect, enabling a lower on-resistance to be maintained even under high voltage conditions. The low-doped N layer can help to homogenize the electric field distribution, especially in high-voltage applications.

[0022] 2. By providing the underlying P+ layer, the present invention can solve the problem of difficulty in forming a charge channel, while also retaining the advantage of the shallow P well layer having a fast response time.

[0023] 3. The doped medium distributed in an inverted triangular shape in the present invention can effectively disperse the electric field, avoiding early breakdown caused by excessive local electric field. And by reasonably arranging the doped medium, a more uniform electric field distribution can be achieved within the entire N drift layer. This distribution method can guide the current to flow along a more effective path.

[0024] 4. The central P+ layer in the present invention can form a local high-doped region under the gate, which helps to shield the electric field under the gate to prevent electric field concentration, and can also effectively reduce the electric field strength at the gate edge to avoid early breakdown. Moreover, the design of the P+ layer helps the heat to be more evenly distributed inside the device, avoiding local overheating, thereby improving the overall thermal stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of Embodiment 1 in the present invention;

[0026] Figure 2 It is a schematic diagram of Embodiment 2 in the present invention;

[0027] Figure 3 It is a schematic diagram of Embodiment 3 in the present invention;

[0028] Figure 4 It is a schematic diagram of Embodiment 4 in the present invention;

[0029] Figure 5 It is a schematic diagram after the structure in Embodiment 3 of the present invention is connected to the gate voltage;

[0030] Figure 6 It is the variation of the drain-source current with time under short-circuit test conditions for the structures of four different embodiments in the present invention.

[0031] In the figure: 1. Drain; 2. Gate; 3. Gate oxide layer; 4. Source; 5. N substrate layer; 6. N drift layer; 7. Side P+ layer; 8. N well layer; 9. P well layer; 10. Underlying P+ layer; 11. Low-doped N layer; 12. Doped medium; 13. Central P+ layer. DETAILED DESCRIPTION OF THE INVENTION

[0032] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] As Figure 1-6 shown, a preparation process of a SiC MOSFET device with a shallow P+ structure includes:

[0034] 1) Select a semiconductor epitaxial layer that passes quality inspection, and form a low-doped N layer 11 and a central P+ layer 13 through ion implantation;

[0035] 2) Inside the N drift layer 6, the doping medium 12 is doped layer by layer to make the doping medium 12 distributed in an inverted triangular shape;

[0036] 3) Perform short-circuit performance detection on the formed SiC MOSFET device, and judge whether the performance of the SiC MOSFET device meets the standard according to the short-circuit detection data. According to the stable value of the drain-source current after the SiC MOSFET device is short-circuited, the applied drain-source voltage, and the magnitude of the threshold voltage, it is determined whether the performance of the SiC MOSFET device meets the standard. Then there is:

[0037]

[0038] In the formula, represents the condition coefficient for the performance of the detected SiC MOSFET device to meet the standard, represents the stable value of the drain-source current after the SiC MOSFET device is short-circuited, represents the magnitude of the applied drain-source short-circuit voltage, represents the magnitude of the threshold voltage of the device.

[0039] When it means that the performance of the detected SiC MOSFET device meets the standard;

[0040] When it means that the performance of the detected SiC MOSFET device does not meet the standard.

[0041] Among them, the performance of the SiC MOSFET structure in Embodiment 1 is detected. The stable value of the drain-source current after the SiC MOSFET device is short-circuited is taken as (A), the magnitude of the applied drain-source short-circuit voltage is taken as (V), and the magnitude of the threshold voltage of the device is taken as (V). Then there is:

[0042]

[0043] As can be known from the above calculations, it can be known from the above calculations that the devices in the detected Example 1 meet the performance requirements. And by comparing the data of multiple groups of examples (such as Figure 6 in which, the red line segment is the detection parameter of Example 1, the green is the detection parameter of Example 2, the blue is the detection parameter of Example 3, and the black is the detection parameter of Example 4), there are:

[0044] Table 1 Parameters and performance status of structure detection in four groups of examples

[0045]

[0046] As can be known from the data in Table 1 above, the samples of the four examples disclosed in the present invention all meet the actual use requirements.

[0047] Example 1

[0048] As Figure 1 shown, according to one aspect of the present invention, a SiC MOSFET device with a shallow P+ structure is provided, which includes a drain 1, a gate 2, a gate oxide layer 3, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer 5, an N drift layer 6, a side P+ layer 7, an N well layer 8, and a P well layer 9. It is characterized in that: a groove is etched on the surface of the semiconductor epitaxial layer, wherein the source electrode 4 is embedded in the semiconductor epitaxial layer through the groove, and the cross-sectional height of the source electrode 4 is the same as the cross-sectional height of the semiconductor epitaxial layer; a lower covering P+ layer 10 is further provided inside the N drift layer 6 and below the P well layer 9, and the lower covering P+ layer 10 is in contact with the side P+ layer 7. If there is no lower covering P+ layer 10, and since the resistance of the P well layer 9 is often particularly large, and the P well layer 9 is particularly thin, which will further increase the resistivity of the P well layer 9. When introducing the source electrode 4 charge into the P well layer 9 only through the side P+ layer 7, it is often necessary to apply a multiple of the gate voltage to form a charge channel on the P well layer 9, and the formed charge channel reaction will also be retarded. However, after adding the lower covering P+ layer 10, the problem of difficult formation of the charge channel will be solved, and at the same time, the advantage of the thin P well layer 9 having a fast reaction time is retained.

[0049] Example 2

[0050] As Figure 2As shown, two symmetric low-doped N layers 11 are formed by ion implantation at the inner bottom side of the N drift layer 6, and an opening for charge flow is formed between the two low-doped N layers 11. The design of the low-doped N layer 11 can guide the charge carriers to flow along a more effective path, reduce the current crowding effect, and thus reduce the on-resistance. This structure helps to enhance the conductance modulation effect, enabling a lower on-resistance to be maintained even under high-voltage conditions. The low-doped N layer 11 can help to homogenize the electric field distribution, especially in high-voltage applications; and it can also effectively prevent the early breakdown phenomenon caused by an overly strong local electric field. The presence of the low-doped region increases the width of the depletion region and improves the breakdown voltage of the device. By optimizing the current path, electromigration in the metal interconnect layer can be reduced, and the service life of the device can be extended.

[0051] Embodiment 3

[0052] As Figure 3 、 5 shown, several doping media 12 are doped inside the N drift layer 6 and between the drain 1 and the gate 2. The spacing between the doping media 12 is equal, and the doping media 12 inside the N drift layer 6 are distributed in an inverted triangular shape. The inverted triangular distribution can effectively disperse the electric field and avoid early breakdown caused by an overly high local electric field. By reasonably arranging the doping media, a more uniform electric field distribution can be achieved throughout the N drift layer. This distribution can guide the current to flow along a more effective path; the inverted triangular distribution helps the heat to be more evenly distributed inside the device, avoiding local overheating, and can homogenize the electric field distribution and increase the breakdown voltage, enabling the device to have better tolerance under transient overvoltage conditions and enhancing the anti-avalanche breakdown ability.

[0053] Embodiment 4

[0054] As Figure 4 shown, a centered P+ layer 13 that does not contact the P well layer 9 is formed by ion implantation inside the N drift layer 6 and below the gate 2. The cross-sectional width of the centered P+ layer 13 is not less than the width of the opening formed between the two low-doped N layers 11. The centered P+ layer 13 can form a local high-doped region under the gate, which helps to shield the electric field under the gate and prevent the electric field from concentrating. This can effectively reduce the electric field strength at the edge of the gate and avoid early breakdown. Also, the design of the P+ layer 13 helps the heat to be more evenly distributed inside the device, avoiding local overheating, thereby improving the overall thermal stability.

[0055] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent for the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention shall be subject to the appended claims.

Claims

1. A SiC MOSFET device with a shallow P+ structure, comprising a drain (1), a gate (2), a gate oxide layer (3) and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer comprises an N substrate layer (5), an N drift layer (6), a side P+ layer (7), an N well layer (8) and a P well layer (9), characterized in that: A groove is etched on the surface of the semiconductor epitaxial layer, wherein the source electrode (4) is embedded in the semiconductor epitaxial layer through the groove, and the cross-sectional height of the source electrode (4) is the same as the cross-sectional height of the semiconductor epitaxial layer; A lower covering P+ layer (10) is also provided inside the N drift layer (6) and below the P well layer (9), and the lower covering P+ layer (10) is in contact with the side P+ layer (7); Two mutually symmetrical low-doped N layers (11) are formed on the inner bottom side of the N drift layer (6) by ion implantation, and an opening for charge flow is formed between the two low-doped N layers (11).

2. The SiC MOSFET device with a shallow P+ structure according to claim 1, characterized in that: A central P+ layer (13) that is not in contact with the P well layer (9) is formed inside the N drift layer (6) and below the gate (2) by ion implantation.

3. The SiC MOSFET device with a shallow P+ structure according to claim 2, characterized in that: The cross-sectional width of the central P+ layer (13) is not less than the width of the opening formed between the two low-doped N layers (11).

4. A process for preparing a SiC MOSFET device having a shallow P+ structure, characterized in that: Applicable to the SiC MOSFET device according to claim 2 or 3, the preparation process of the SiC MOSFET device with a shallow P+ structure comprises: S1, selecting a semiconductor epitaxial layer that has passed the quality inspection, and forming a low-doped N layer (11) and a central P+ layer (13) by ion implantation; S2. Perform a short-circuit performance test on the formed SiC MOSFET device, and determine whether the performance of the SiC MOSFET device meets the standard based on the short-circuit test data.

5. The process for preparing a SiC MOSFET device with a shallow P+ structure according to claim 4, characterized in that: In step S2, whether the performance of the SiC MOSFET device meets the standard is determined according to the stable value of the drain-source current, the applied drain-source voltage, and the threshold voltage after the SiC MOSFET device is short-circuited: In the formula, w represents the condition coefficient for the performance of the tested SiC MOSFET device to meet the standard; a represents the stable value of the drain-source current after the SiC MOSFET device is short-circuited, in A; u1 represents the magnitude of the applied drain-source short-circuit voltage, in V; u0 represents the threshold voltage of the device, in V.

6. The process for preparing a SiC MOSFET device with a shallow P+ structure according to claim 5, characterized in that: When w ≥ 70%, it means that the performance of the SiC MOSFET device tested meets the standard; When w<70%, it means that the performance of the SiC MOSFET device tested does not meet the standard.

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