Silicon carbide super junction primitive cell structure, manufacturing method thereof and power device

Abstract

The invention provides a silicon carbide super junction primitive cell structure, a manufacturing method thereof and a power device. The silicon carbide super junction primitive cell structure comprises a conductive type silicon carbide substrate, n first conductive type epitaxial layers stacked on one side of the first conductive type silicon carbide substrate, a first conductive type high epitaxial layer and a source electrode, wherein the first conductive type high epitaxial layer and the source electrode are sequentially arranged on one side, away from the first conductive type silicon carbide substrate, of the nth first conductive type epitaxial layer; and two semi-insulating vertical structures, wherein n is a positive integer greater than 1. The first conductive type epitaxial layer with higher concentration can be used on the premise of ensuring the voltage withstanding level, so that the specific on-resistance of the primitive cell structure is reduced, and the current density of the primitive cell structure is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a silicon carbide super junction cell structure and a manufacturing method thereof, and a power device. Background Art

[0002] Silicon carbide superjunction power devices are suitable for high voltage, high current, high temperature, high frequency and other working conditions, which can significantly improve the efficiency of power conversion and reduce the loss of power conversion. Currently, they have been widely used in high-end switching power supplies, new energy vehicles and new energy vehicle main electric drives.

[0003] However, current silicon carbide superjunction power devices still have the problem of large on-resistance. Summary of the invention

[0004] In view of the shortcomings of the existing methods, the present application proposes a silicon carbide super junction cell structure and a manufacturing method thereof, and a power device to solve the technical problem of large on-resistance in related technologies.

[0005] In a first aspect, an embodiment of the present application provides a silicon carbide super junction primitive cell structure, including:

[0006] a first conductivity type silicon carbide substrate;

[0007] n first conductivity type epitaxial layers are stacked on one side of the first conductivity type silicon carbide substrate; two second conductivity type doped regions are symmetrically arranged on the top of each first conductivity type epitaxial layer, and the upper surface of the second conductivity type doped region is flush with the upper surface of the first conductivity type epitaxial layer; the second conductivity type doped regions of each layer are opposite; wherein n is a positive integer greater than 1;

[0008] A first conductivity type high epitaxial layer and a source electrode are sequentially arranged on a side of the nth first conductivity type epitaxial layer away from the first conductivity type silicon carbide substrate;

[0009] Two semi-insulating vertical structures, each of which passes through the first conductive type high epitaxial layer and n first conductive type epitaxial layers, and simultaneously passes through n second conductive type doped regions located in the same column, one end of each semi-insulating vertical structure is connected to the source electrode, and the other end is connected to the first conductive type silicon carbide substrate.

[0010] In a second aspect, an embodiment of the present application provides a silicon carbide super junction power device, comprising: an array-arranged silicon carbide super junction primitive cell structure as described in the first aspect.

[0011] In a third aspect, an embodiment of the present application provides a method for manufacturing a silicon carbide super junction cell structure, comprising:

[0012] S1: manufacturing a first first conductivity type epitaxial layer on one side of a first conductivity type silicon carbide substrate; forming two first second conductivity type horizontal doping regions oppositely disposed on the top of the first first conductivity type epitaxial layer by ion implantation, so that the upper surface of the first second conductivity type horizontal doping region is flush with the upper surface of the first first conductivity type epitaxial layer;

[0013] S2: manufacturing an nth first conductivity type epitaxial layer above the first first conductivity type epitaxial layer, and forming two oppositely arranged nth second conductivity type horizontal doping regions on the top of the nth first conductivity type epitaxial layer by ion implantation; repeating this step until a set number of first conductivity type epitaxial layers is obtained, wherein n is a positive integer greater than 1;

[0014] S3: manufacturing a first conductivity type high epitaxial layer above the nth first conductivity type epitaxial layer; patterning the first conductivity type high epitaxial layer and both sides of the n first conductivity type epitaxial layers to obtain two first vertical trenches, so that the first vertical trenches pass through the n second conductivity type doping regions in the same column and expose the first conductivity type silicon carbide substrate;

[0015] S4: manufacturing a semi-insulating vertical structure in the first vertical trench;

[0016] S5: manufacturing a source electrode on a side of the first conductive type high epitaxial layer away from the first conductive type silicon carbide substrate.

[0017] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0018] When the unit cell structure is subjected to a blocking high voltage, the internal potential of the semi-insulating vertical structure increases approximately linearly along the direction of the source electrode toward the first conductive type silicon carbide substrate, thereby assisting the first conductive type epitaxial layer and the second conductive type doped region to be gradually depleted, so that the first conductive type epitaxial layer can withstand a higher voltage at a higher doping level, and a higher concentration of the first conductive type epitaxial layer can be used while ensuring the withstand voltage level, which is beneficial to reducing the specific on-resistance of the unit cell structure and improving the current density of the unit cell structure.

[0019] The first vertical groove exposes the second conductive type doped regions of each layer, which can improve the design margin and process window for the charge fluctuation of the second conductive type doped regions, making the design and process of the silicon carbide super junction cell structure more robust.

[0020] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0022] Figure 1 A schematic diagram of the structure of a silicon carbide super junction cell structure provided in an embodiment of the present application;

[0023] Figure 2 A schematic diagram of the change of the internal potential of a semi-insulating vertical structure along the direction from the source electrode to the first conductive type silicon carbide substrate when the unit cell structure is subjected to a blocking high voltage provided in an embodiment of the present application;

[0024] Figure 3 A schematic diagram of a process for manufacturing a silicon carbide superjunction cell structure provided in an embodiment of the present application;

[0025] Figure 4-Figure 13 A schematic diagram of the structure obtained in each step of a method for manufacturing a silicon carbide super junction cell structure provided in an embodiment of the present application. Description of the drawings:

[0027] 100-a first conductivity type silicon carbide substrate;

[0028] 200 - a first first conductivity type epitaxial layer; 201 - a mask structure; 210 - a first second conductivity type horizontal doping region;

[0029] 300 - a second first conductivity type epitaxial layer; 310 - a second second conductivity type doped region;

[0030] 400 - a third first conductivity type epitaxial layer; 410 - a third second conductivity type doped region;

[0031] 500 - a fourth first conductivity type epitaxial layer; 510 - a fourth second conductivity type doped region; 520 - a second conductivity type shielding structure;

[0032] 600 - first conductivity type high epitaxial layer; 610 - second conductivity type body region; 620 - first conductivity type source region; 630 - second conductivity type base region;

[0033] 700 - mask layer; 710 - first vertical trench; 720 - semi-insulating vertical structure; 730 - second vertical trench; 740 - third vertical trench;

[0034] 810-horizontal dielectric structure; 820-vertical dielectric structure; 830-gate dielectric layer; 840-gate electrode; 850-interlayer dielectric layer;

[0035] 910 - source electrode; 920 - drain electrode. DETAILED DESCRIPTION

[0036] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0037] It will be understood by those skilled in the art that, unless specifically stated, the "said" and "the" used herein may also include plural forms. It should be further understood that the wording "including" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may refer to the connection relationship between the element and the other element through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0038] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0039] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following implementation modes can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementation modes will not be described repeatedly.

[0040] The descriptions "first conductivity type" and "second conductivity type" used in this application refer to n-type conductivity (i.e., electron conductivity) and p-type conductivity (i.e., hole conductivity), respectively. Specifically, the first conductivity type is n-type conductivity, and the second conductivity type is p-type conductivity; or, the first conductivity type is p-type conductivity, and the second conductivity type is n-type conductivity.

[0041] It should be noted that Figure 1 The middle dashed line represents the AA′ in the semi-insulating vertical structure 720 .

[0042] The present application embodiment provides a silicon carbide super junction primitive cell structure. The structural schematic diagram of the primitive cell structure is as follows: Figure 1As shown, it includes: a first conductive type silicon carbide substrate 100, n first conductive type epitaxial layers stacked on one side of the first conductive type silicon carbide substrate 100, a first conductive type high epitaxial layer 600 and a source electrode 910 sequentially arranged on the side of the nth first conductive type epitaxial layer away from the first conductive type silicon carbide substrate 100, and two semi-insulating vertical structures 720, wherein n is a positive integer greater than 1.

[0043] Two second conductivity type doped regions are symmetrically arranged on the top of each first conductivity type epitaxial layer, and the upper surface of the second conductivity type doped region is flush with the upper surface of the first conductivity type epitaxial layer; the second conductivity type doped regions of each layer are opposite.

[0044] The semi-insulating vertical structure 720 passes through the first conductive type high epitaxial layer and n first conductive type epitaxial layers, and at the same time passes through n second conductive type doped regions located in the same column. One end of the semi-insulating vertical structure 720 is connected to the source electrode 910, and the other end is connected to the first conductive type silicon carbide substrate 100.

[0045] In this embodiment, Figure 1 and Figure 2 As shown, when the unit cell structure is subjected to a blocking high voltage, the internal potential of the semi-insulating vertical structure 720 increases approximately linearly along the direction of the source electrode 910 toward the first conductive type silicon carbide substrate 100, thereby assisting the first conductive type epitaxial layer and the second conductive type doped region to be gradually depleted, so that the first conductive type epitaxial layer can withstand a higher voltage at a higher doping level, and a higher concentration of the first conductive type epitaxial layer can be used under the premise of ensuring the withstand voltage level, which is beneficial to reduce the specific on-resistance of the unit cell structure and improve the current density of the unit cell structure.

[0046] The semi-insulating vertical structure 720 is made of a semi-insulating material, including but not limited to silicon carbide, gallium nitride, gallium oxide or diamond, etc. The semi-insulating material has a high critical breakdown electric field, which can avoid the situation in which the critical breakdown electric field strength is low when the gate electrode is used as a deep trench electrode in the traditional primitive cell structure.

[0047] Optionally, the height of the nth second conductivity type doping region is not less than the height of the n-1th second conductivity type doping region along the direction perpendicular to the first conductivity type silicon carbide substrate 100. Along the vertical downward direction of the silicon carbide substrate 100, the interval between the nth second conductivity type doping region and the n-1th second conductivity type doping region is equal or increases.

[0048] In this embodiment, the heights of the n second conductive type doping regions are not less than 0.5 micrometers and not more than 1.5 micrometers. The doping concentration of the n second conductive type doping regions is 1e 16 ~1e 18cm -3 It is understandable that the size of the horizontal doping region is calculated according to the amount of charge required for charge balance, and no limitation is made herein.

[0049] Optionally, the silicon carbide super junction cell structure further includes two vertical dielectric structures 820 . The vertical dielectric structures 820 are disposed on the outer side of the semi-insulating vertical structure 720 .

[0050] In this embodiment, the vertical dielectric structure 820 can increase the voltage resistance of the unit cell structure, and can also isolate the semi-insulating vertical structure 720 from the second conductive type body region 610 and the second conductive type source region, effectively avoiding current interference.

[0051] Optionally, the silicon carbide super junction cell structure further includes n junction regions and a horizontal dielectric structure 810 .

[0052] The junction region is disposed between two adjacent second conductivity type doped regions in the same first conductivity type epitaxial layer. A second conductivity type shielding structure 520 is disposed in the nth junction region. The upper surface of the second conductivity type shielding structure 520 is flush with the upper surface of the nth first conductivity type epitaxial layer.

[0053] The bottom of the horizontal dielectric structure 810 is disposed within the top of the second conductive type shielding structure 520 .

[0054] In this embodiment, the second conductive type shielding structure 520 can make the charge distribution of the gate electrode 840 more uniform, and can also make the position of the gate electrode 840 more accurate, thereby reducing the alignment accuracy when manufacturing the gate electrode 840.

[0055] Optionally, the silicon carbide super junction cell structure further includes a gate electrode 840 , a gate dielectric layer 830 disposed on an outer side of the gate electrode 840 , and an interlayer dielectric layer 850 disposed on a top of the gate electrode 840 .

[0056] The gate electrode 840 is disposed in the first conductivity type high epitaxial layer 600 and is located on a side of the horizontal dielectric structure 810 away from the first conductivity type silicon carbide substrate 100 .

[0057] In this embodiment, the thickness of the horizontal dielectric structure 810 is greater than twice the thickness of the gate dielectric layer 830 .

[0058] Optionally, the silicon carbide super junction cell structure further includes a second conductivity type base region 630 , a first conductivity type source region 620 and a second conductivity type body region 610 arranged outside the gate dielectric layer 830 , and a drain electrode 920 arranged at the bottom of the first conductivity type silicon carbide substrate 100 .

[0059] The second conductive type base region 630 and the first conductive type source region 620 are located in the first conductive type high epitaxial layer 600 above the junction region. The second conductive type base region 630 is located below the first conductive type source region 620; the bottom surface of the second conductive type base region 630 is farther away from the first conductive type silicon carbide substrate 100 than the bottom surface of the gate electrode 840. The first conductive type source region 620 is connected to the source electrode 910.

[0060] The second conductivity type body region 610 is located between the vertical dielectric structure 820 and the first conductivity type source region 620 ; the upper surface of the second conductivity type body region 610 is connected to the source electrode 910 , and the lower surface thereof is flush with the lower surface of the second conductivity type base region 630 .

[0061] In this embodiment, the depth of the gate electrode 840 is not less than the depth of the second conductivity type base region 630 .

[0062] Based on the same inventive concept, an embodiment of the present application provides a silicon carbide super junction power device, including an array-arranged silicon carbide super junction primitive cell structure as provided above.

[0063] In this embodiment, since the power device includes the silicon carbide super junction cell structure provided above, the beneficial effects during the power device also include the beneficial effects of the silicon carbide super junction cell structure provided above, which will not be repeated here.

[0064] Based on the same inventive concept, the present application embodiment provides a method for manufacturing a silicon carbide super junction cell structure, and the flow chart of the method is as follows: Figure 3 As shown, the method includes:

[0065] S1: Manufacturing a first first conductive type epitaxial layer 200 on one side of a first conductive type silicon carbide substrate 100; forming two oppositely arranged first second conductive type horizontal doping regions 210 on the top of the first first conductive type epitaxial layer 200 by ion implantation, so that the upper surface of the first second conductive type horizontal doping region 210 is flush with the upper surface of the first first conductive type epitaxial layer 200.

[0066] In this embodiment, a schematic diagram of a structure obtained by manufacturing a first first conductivity type epitaxial layer 200 on one side of a first conductivity type silicon carbide substrate 100 is shown in FIG. Figure 4 shown.

[0067] Before ion implantation is performed on the top of the first first conductivity type epitaxial layer 200, a mask structure 201 needs to be provided above the junction region of the first first conductivity type epitaxial layer 200. The obtained structure diagram is as shown in FIG. Figure 5Under the mask of the mask structure 201, ion implantation is performed on the top of the first first conductivity type epitaxial layer 200 to obtain a first second conductivity type horizontal doping region 210 as shown in FIG. Figure 6 The mask structure 201 is a structure with a specific line width formed by thin film deposition, photolithography, and etching.

[0068] S2: manufacturing an nth first conductivity type epitaxial layer above the first first conductivity type epitaxial layer 200, and forming two oppositely arranged nth second conductivity type horizontal doping regions on the top of the nth first conductivity type epitaxial layer by ion implantation; and continuously repeating this step until a set number of first conductivity type epitaxial layers is obtained, where n is a positive integer greater than 1.

[0069] In this embodiment, the second conductivity type horizontal doping region is obtained by ion implantation, and the charge amount and the spatial distribution of the charge in the second conductivity type horizontal doping region can be precisely controlled.

[0070] Optionally, the height of the nth second conductivity type doping region is not less than the height of the n-1th second conductivity type doping region along the direction perpendicular to the first conductivity type silicon carbide substrate 100. Along the vertical downward direction of the silicon carbide substrate 100, the interval between the nth second conductivity type doping region and the n-1th second conductivity type doping region is equal or increases.

[0071] In this embodiment, the height of the n horizontal doping regions is not less than 0.5 micrometers and not more than 1.5 micrometers. The doping concentration of the n horizontal doping regions is 1e 16 ~1e 18 cm -3 .

[0072] For example, Figure 7 As shown, the present application manufactures four epitaxial layers, namely, a first first conductivity type epitaxial layer 200, a second first conductivity type epitaxial layer 300, a third first conductivity type epitaxial layer 400, and a fourth first conductivity type epitaxial layer 500. A first second conductivity type doping region 210 is arranged on the top of the first first conductivity type epitaxial layer 200, a second second conductivity type doping region 310 is arranged on the top of the second first conductivity type epitaxial layer 200, a third second conductivity type doping region 410 is arranged on the top of the third first conductivity type epitaxial layer 400, and a fourth second conductivity type doping region 510 is arranged on the top of the fourth first conductivity type epitaxial layer 500. The first second conductivity type doping region 210, the second second conductivity type doping region 310, the third second conductivity type doping region 410, and the fourth second conductivity type doping region 510 are arranged relatively.

[0073] Optionally, in step S2, the manufacturing method includes: manufacturing an nth first conductivity type epitaxial layer above the first first conductivity type epitaxial layer 200, forming two oppositely disposed nth second conductivity type horizontal doping regions by ion implantation on the top of the nth first conductivity type epitaxial layer, and manufacturing a second conductivity type shielding structure 520 in an nth junction region between the two oppositely disposed nth second conductivity type horizontal doping regions, so that the upper surface of the second conductivity type shielding structure 520 is flush with the upper surface of the nth epitaxial layer, and the obtained structural schematic diagram is as shown in FIG. Figure 7 .

[0074] In this embodiment, the second conductive type shielding structure 520 can make the charge of the gate electrode 840 manufactured subsequently more uniform.

[0075] S3: manufacture a first conductivity type high epitaxial layer 600 above the nth first conductivity type epitaxial layer; pattern the first conductivity type high epitaxial layer 600 and both sides of the n first conductivity type epitaxial layers to obtain two first vertical grooves 710, so that the first vertical grooves 710 pass through the n second conductivity type doped regions in the same column and expose the first conductivity type silicon carbide substrate 100.

[0076] In this embodiment, the first vertical trench 710 penetrates the first conductive type high epitaxial layer 600 and the n first conductive type epitaxial layers to reach the first conductive type silicon carbide substrate 100. The first vertical trench 710 exposes the second conductive type doped regions of each layer, which can improve the design margin and process window for the charge fluctuation of the second conductive type doped regions, making the design and process of the silicon carbide super junction primitive cell structure more robust.

[0077] Optionally, in step S3, after manufacturing the first conductivity type high epitaxial layer 600 above the nth first conductivity type epitaxial layer, patterning the first conductivity type high epitaxial layer 600 and both sides of the n first conductivity type epitaxial layers to obtain two first vertical trenches 710, the manufacturing method further includes:

[0078] A second conductivity type base region 630 and a first conductivity type source region 620 are sequentially manufactured in the first conductivity type high epitaxial layer 600 above the nth junction region, so that the second conductivity type base region 630 is located below the first conductivity type source region 620 .

[0079] A second conductive type body region 610 is fabricated in the first conductive type high epitaxial layer 600 above the second conductive type source region 620, so that the side surface of the second conductive type body region 610 is connected to the side surfaces of the second conductive type base region 630 and the first conductive type source region 620. The obtained structural schematic diagram is shown in FIG. Figure 8 shown.

[0080] A mask layer 700 is manufactured above the first conductive type source region 620 so that both sides of the mask layer 700 cover a portion of the second conductive type body region 610. The resulting structural schematic diagram is shown in FIG. Fig. 9 shown.

[0081] In this embodiment, the height of the second conductive type base region 630 is the length of the channel. The height of the second conductive type base region 630 is not less than 0.3 micrometers and not more than 0.5 micrometers. The doping concentration is 1e 17 ~1e 19 cm -3 Under the mask of the mask layer 700 , the first conductivity type high epitaxial layer 600 and both sides of the n first conductivity type epitaxial layers are patterned to obtain two first vertical trenches 710 .

[0082] S4: A semi-insulating vertical structure 720 is manufactured in the first vertical trench 710. The obtained structural schematic diagram is shown in FIG. Fig.10 shown.

[0083] In this embodiment, a semi-insulating material is filled in the first vertical trench 710 by an epitaxial growth method. The band gap width of the semi-insulating material is not less than 3.2 eV, and it is an intrinsic semiconductor or a low-doped semiconductor, showing semi-insulating or high resistivity electrical properties. The semi-insulating material includes but is not limited to silicon carbide, gallium nitride, gallium oxide or diamond.

[0084] Optionally, after step S4 and before step S5, the manufacturing method further includes:

[0085] The second conductive type body region 610 is patterned, and the second conductive type source region 620 is patterned to obtain a second vertical trench 730 and a third vertical trench 740, so that the second vertical trench 730 extends to the first conductive type silicon carbide substrate 100, and the second vertical trench 730 is located on the side of the semi-insulating vertical structure 720, so that the third vertical trench 740 extends into the second conductive type shielding structure 520, and the obtained structural schematic diagram is as shown in FIG. Fig.11 shown.

[0086] A vertical dielectric structure 820 and a horizontal dielectric structure 810 are respectively manufactured in the second vertical trench 730 and at the bottom of the third vertical trench 740; then a gate dielectric layer 830 is manufactured on the sidewall of the third vertical trench 740, and a gate electrode 840 is manufactured in the third vertical trench 740. The obtained structural schematic diagram is shown in FIG. Fig.12 shown.

[0087] An interlayer dielectric layer 850 is fabricated on top of the gate electrode 840 .

[0088] In this embodiment, the materials of the vertical dielectric structure 820 and the horizontal dielectric structure 810 are both high dielectric constant, including but not limited to HfO 2 、TiO 2 、ZrO 2 、 2 O 5 The interlayer dielectric layer 850 can be manufactured by a self-oxidation process. The interlayer dielectric layer 850 includes a self-oxidation layer. The gap in the self-oxidation layer can be used as an ohmic contact hole. Compared with the contact hole obtained by the photolithography process in the traditional process, it can be more accurate and save cost and time, and is also conducive to reducing the size of the original cell structure.

[0089] The third vertical trench 740 extends into the second conductive type shielding structure 520 , which can reduce the control accuracy of the third vertical trench 740 .

[0090] S5: A source electrode 910 is manufactured on a side of the first conductive type high epitaxial layer 600 away from the first conductive type silicon carbide substrate 100. The obtained structure diagram is shown in FIG. Fig.13 shown.

[0091] In this embodiment, the source electrode 910 is in ohmic contact with both the second conductivity type source region 620 and the second conductivity type body region 610. The source electrode 910 is also in ohmic contact with the semi-insulating vertical structure.

[0092] Optionally, after step S5, the manufacturing method further includes: manufacturing a drain electrode 920 at the bottom of the first conductive type silicon carbide substrate 100, and the obtained structural schematic diagram is as shown in FIG. Figure 1 shown.

[0093] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, changed, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, changed, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the related art that are similar to those disclosed in this application may also be alternated, changed, rearranged, decomposed, combined, or deleted.

[0094] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.

[0095] The terms "first", "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0096] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0097] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0098] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A silicon carbide super junction cell structure, characterized in that: include: a first conductivity type silicon carbide substrate; n first conductivity type epitaxial layers are stacked on one side of the first conductivity type silicon carbide substrate; two second conductivity type doped regions are symmetrically arranged on the top of each first conductivity type epitaxial layer, and the upper surface of the second conductivity type doped region is flush with the upper surface of the first conductivity type epitaxial layer; the second conductivity type doped regions of each layer are opposite; wherein n is a positive integer greater than 1; A first conductivity type high epitaxial layer and a source electrode are sequentially arranged on a side of the nth first conductivity type epitaxial layer away from the first conductivity type silicon carbide substrate; Two semi-insulating vertical structures, each of which passes through the first conductive type high epitaxial layer and n first conductive type epitaxial layers, and simultaneously passes through n second conductive type doped regions located in the same column, one end of each semi-insulating vertical structure is connected to the source electrode, and the other end is connected to the first conductive type silicon carbide substrate.

2. The silicon carbide superjunction cell structure according to claim 1, characterized in that: Also includes: Two vertical media structures; The vertical dielectric structure is arranged on the outer side of the semi-insulating vertical structure.

3. The silicon carbide super junction cell structure according to claim 1, characterized in that: Also includes: n junction regions and horizontal dielectric structures; The junction region is arranged between two adjacent second conductivity type doped regions in the same first conductivity type epitaxial layer; a second conductivity type shielding structure is arranged in the nth junction region, and an upper surface of the second conductivity type shielding structure is flush with an upper surface of the nth first conductivity type epitaxial layer; The bottom of the horizontal dielectric structure is disposed within the top of the second conductive type shielding structure.

4. The silicon carbide super junction cell structure according to claim 3, characterized in that: It also includes a gate electrode, a gate dielectric layer disposed on the outer side of the gate electrode, and an interlayer dielectric layer disposed on the top of the gate electrode; The gate electrode is arranged in the first conductivity type high epitaxial layer and is located at a side of the horizontal dielectric structure away from the first conductivity type silicon carbide substrate.

5. The silicon carbide super junction cell structure according to claim 4, characterized in that: It also includes a second conductivity type base region, a first conductivity type source region and a second conductivity type body region arranged outside the gate dielectric layer, and a drain electrode arranged at the bottom of the first conductivity type silicon carbide substrate; The second conductive type base region and the first conductive type source region are located in the first conductive type high epitaxial layer above the junction region, the second conductive type base region is located below the first conductive type source region, the bottom surface of the second conductive type base region is farther away from the first conductive type silicon carbide substrate than the bottom surface of the gate electrode, and the first conductive type source region is connected to the source electrode; The second conductive type body region is located between the vertical dielectric structure and the first conductive type source region, the upper surface of the second conductive type body region is connected to the source electrode, and the lower surface thereof is flush with the lower surface of the second conductive type base region.

6. A silicon carbide super junction power device, characterized in that: The invention comprises the silicon carbide super junction primitive cell structure as claimed in any one of claims 1 to 5 arranged in an array.

7. A method for manufacturing a silicon carbide superjunction cell structure, characterized in that: include: S1: manufacturing a first first conductivity type epitaxial layer on one side of a first conductivity type silicon carbide substrate; Forming two first second conductivity type horizontal doping regions opposite to each other on the top of the first first conductivity type epitaxial layer by ion implantation, so that the upper surface of the first second conductivity type horizontal doping region is flush with the upper surface of the first first conductivity type epitaxial layer; S2: manufacturing an nth first conductivity type epitaxial layer above the first first conductivity type epitaxial layer, and forming two oppositely arranged nth second conductivity type horizontal doping regions on the top of the nth first conductivity type epitaxial layer by ion implantation; repeating this step until a set number of first conductivity type epitaxial layers is obtained, wherein n is a positive integer greater than 1; S3: manufacturing a first conductivity type high epitaxial layer above the nth first conductivity type epitaxial layer; patterning the first conductivity type high epitaxial layer and both sides of the n first conductivity type epitaxial layers to obtain two first vertical trenches, so that the first vertical trenches pass through the n second conductivity type doping regions in the same column and expose the first conductivity type silicon carbide substrate; S4: manufacturing a semi-insulating vertical structure in the first vertical trench; S5: manufacturing a source electrode on a side of the first conductive type high epitaxial layer away from the first conductive type silicon carbide substrate.

8. The manufacturing method according to claim 7, characterized in that: The manufacturing method comprises: manufacturing an nth first conductivity type epitaxial layer above the first first conductivity type epitaxial layer, and forming two oppositely arranged nth second conductivity type horizontal doping regions on the top of the nth first conductivity type epitaxial layer by ion implantation. A second conductive type shielding structure is manufactured in the nth junction region between two oppositely disposed nth second conductive type horizontal doping regions, so that the upper surface of the second conductive type shielding structure is flush with the upper surface of the nth epitaxial layer.

9. The manufacturing method according to claim 8, characterized in that: After manufacturing a first conductivity type high epitaxial layer above the nth first conductivity type epitaxial layer, and before patterning both sides of the first conductivity type high epitaxial layer and the n first conductivity type epitaxial layers to obtain two first vertical trenches, the manufacturing method further includes: Sequentially manufacturing a second conductivity type base region and a first conductivity type source region in the first conductivity type high epitaxial layer above the nth junction region, so that the second conductivity type base region is located below the first conductivity type source region; Manufacturing a second conductivity type body region in the first conductivity type high epitaxial layer above the second conductivity type source region, so that the side surface of the second conductivity type body region is in contact with the side surfaces of the second conductivity type base region and the first conductivity type source region; A mask layer is manufactured above the first conductive type source region, so that both sides of the mask layer cover a portion of the second conductive type body region.

10. The manufacturing method according to claim 9, characterized in that: After manufacturing a semi-insulating vertical structure in the first vertical trench and before manufacturing a source electrode on a side of the first conductive type high epitaxial layer away from the first conductive type silicon carbide substrate, the manufacturing method further includes: Patterning the second conductive type body region and the second conductive type source region to obtain a second vertical trench and a third vertical trench, so that the second vertical trench extends to the first conductive type silicon carbide substrate, the second vertical trench is located on the side of the semi-insulating vertical structure, and the third vertical trench extends into the second conductive type shielding structure; A vertical dielectric structure and a horizontal dielectric structure are respectively manufactured in the second vertical trench and at the bottom of the third vertical trench; then a gate dielectric layer is manufactured on the sidewall of the third vertical trench and a gate electrode is manufactured in the third vertical trench.

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