Semiconductor device, semiconductor structure and preparation method thereof
By covering the silicon oxide protective layer on the polycrystalline silicon gate structure, the damage problem of this structure in the chemical etching and cleaning process is solved, the stability of structural and electrical performance is achieved, and the production yield and reliability of semiconductor devices are improved.
Patent Information
- Application Number
- CN202510026140.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-07
- Publication Date
- 2025-04-22
AI Technical Summary
During semiconductor manufacturing, the polycrystalline silicon gate structure is easily damaged in the chemical etching and cleaning process, resulting in reduced feature size and deviation from the design value, which in turn affects electrical performance and reliability.
The silicon oxide protective layer is covered with the shape on the polycrystalline silicon gate structure, forming an undoped silicate glass layer, a silicon oxide-rich layer and/or a plasma-reinforced tetraethyl orthosilicate layer with a thickness ranging from 1 nm to 50 nm, and is formed by physical vapor deposition or tube furnace growth process.
Effectively isolate the polysilicon gate structure from the external chemical environment, avoid damage, ensure the stability of structural and electrical performance, and improve the production yield and reliability of semiconductor devices.
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Figure CN119866047A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device, a semiconductor structure and a method for preparing the same. Background Art
[0002] Polysilicon gate structures have many advantages in the manufacture of integrated circuits and embedded memory devices, including improving device performance, reducing manufacturing costs, expanding application scope, and improving reliability. With the continuous advancement of semiconductor processes, polysilicon gate structures will continue to play an important role in promoting the further development of integrated circuit and embedded memory device technologies. Therefore, the stability and feature size control of polysilicon gate structures are becoming increasingly critical.
[0003] However, in the production process, polysilicon gate structures often face the challenge of loss, especially in the chemical etching and cleaning process. This loss mainly comes from the oxidation of the polysilicon gate and the loss of material during the chemical etching process, which leads to the reduction of its feature size and the deviation of its morphology from the design value, thus causing the degradation of electrical performance and reliability problems.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0005] Based on this, the embodiments of the present application provide a semiconductor device, a semiconductor structure and a method for preparing the same, which can prevent the polysilicon gate structure from being damaged, and are beneficial to improving the production yield and reliability of the semiconductor device.
[0006] According to some embodiments, the present application provides, on one hand, a method for preparing a semiconductor structure, comprising:
[0007] Providing a substrate, on which a polysilicon gate structure is formed;
[0008] A silicon oxide protection layer is formed on the substrate, and the silicon oxide protection layer conformally covers the polysilicon gate structure.
[0009] In some embodiments, the silicon oxide protective layer includes an undoped silicate glass layer, a silicon rich oxide layer, and / or a plasma enhanced tetraethyl orthosilicate layer.
[0010] In some embodiments, the thickness of the silicon oxide protective layer ranges from 1 nm to 50 nm.
[0011] In some embodiments, forming a silicon oxide protective layer on the substrate includes:
[0012] The silicon oxide protective layer is deposited on the substrate by a physical vapor deposition process; or, the silicon oxide protective layer is grown on the substrate by a tube furnace.
[0013] In some embodiments, when the silicon oxide protective layer is deposited on the substrate using the physical vapor deposition process, the deposition temperature is less than or equal to 300° C.;
[0014] When the silicon oxide protective layer is grown on the substrate using the tube furnace, the growth temperature is less than or equal to 500°C.
[0015] In some embodiments, the preparation method further comprises:
[0016] removing the silicon oxide protective layer;
[0017] A gate sidewall is formed on the sidewall of the polysilicon gate structure.
[0018] In some embodiments, removing the silicon oxide protective layer includes:
[0019] The silicon oxide protective layer is removed by a wet cleaning process.
[0020] In some embodiments, the polysilicon gate structure includes a doped polysilicon layer and an intrinsic polysilicon layer sequentially stacked in a direction away from the substrate.
[0021] According to some embodiments, the present application further provides a semiconductor structure on the other hand, wherein the semiconductor structure is prepared by using the method for preparing a semiconductor structure provided by any of the aforementioned embodiments.
[0022] According to some embodiments, the present application provides a semiconductor device on another aspect, wherein the manufacturing process of the semiconductor device includes the steps of the method for preparing the semiconductor structure provided by any of the aforementioned embodiments; or includes the semiconductor structure provided by the aforementioned embodiments.
[0023] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application.
[0024] The embodiments of the present application may or at least have the following advantages:
[0025] The embodiment of the present application conformally covers the polysilicon gate structure with a silicon oxide protective layer, so that the surface of the polysilicon gate structure is isolated from the external chemical environment and is not affected by external processes, thereby avoiding damage to the polysilicon gate structure by subsequent wet cleaning processes, chemical etching processes or other semiconductor process processes, ensuring the stability of the shape structure and electrical properties of the polysilicon gate structure, and facilitating improving the production yield and reliability of semiconductor devices.
[0026] Since the silicon oxide protective layer has good chemical resistance and thermal stability, the silicon oxide protective layer is selected to protect the polysilicon gate structure. This can not only prevent the polysilicon gate structure from being corroded or damaged during the subsequent wet cleaning process, chemical etching process or other semiconductor process, but also can withstand various treatments at high temperatures (such as ion implantation and annealing operations) in subsequent processes, and can maintain structural stability under high temperature conditions, providing stable and reliable protection for the polysilicon gate structure.
[0027] Other advantages, objectives and features of the present application will be described in the following description to some extent, and will be apparent to those skilled in the art based on the following examination and study, or can be taught from the practice of the present application to some extent. The objectives and other advantages of the present application can be achieved and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings.
[0029] Figure 1 A schematic diagram of a process for preparing a semiconductor structure provided in some embodiments of the present application;
[0030] Figure 2 A schematic diagram of a process after forming a silicon oxide protective layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0031] Figure 3 A schematic diagram of a cross-sectional structure of a structure obtained after a polysilicon gate structure is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0032] Figure 4 This is a schematic diagram of the cross-sectional structure of a structure obtained after a silicon oxide protective layer is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application.
[0033] Description of reference numerals:
[0034] 10. Polysilicon gate structure; 10a. Doped polysilicon layer; 10b. Intrinsic polysilicon layer; 20. Silicon oxide protective layer. DETAILED DESCRIPTION
[0035] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0037] It should be understood that when an element or layer is referred to as being "on," it may be directly on other elements or layers, or there may be intervening elements or layers. Also, in addition to the orientations shown in the figures, spatial relational terms also include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "on" will be oriented "below" the other elements or features. Thus, the exemplary term "on" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0038] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0039] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Although the diagrams only show the layers related to the present application and are not drawn according to the number, shape and size of the layers in actual implementation, the type, quantity and proportion of each layer in actual implementation may be changed arbitrarily, and the layer layout may also be more complicated.
[0040] Polysilicon gate structures have many advantages in the manufacture of integrated circuits and embedded memory devices, including improving device performance, reducing manufacturing costs, expanding application scope, and improving reliability. With the continuous advancement of semiconductor processes, polysilicon gate structures will continue to play an important role in promoting the further development of integrated circuit and embedded memory device technologies. Therefore, the stability and feature size control of polysilicon gate structures are becoming increasingly critical.
[0041] However, in the production process, polysilicon gate structures often face the challenge of loss, especially in the chemical etching and cleaning process. This loss mainly comes from the oxidation of the polysilicon gate and the loss of material during the chemical etching process, which leads to the reduction of its feature size and the deviation of its morphology from the design value, thus causing the degradation of electrical performance and reliability problems.
[0042] Based on this, the present application hopes to provide a solution that can solve the above technical problems, which can avoid damage to the polysilicon gate structure and help improve the production yield and reliability of semiconductor devices. The details will be described in the subsequent embodiments.
[0043] According to some embodiments, the present application provides a method for preparing a semiconductor structure. Figure 1 The method for preparing the semiconductor structure may specifically include the following steps S100 to S200:
[0044] S100: providing a substrate, on which a polysilicon gate structure is formed.
[0045] S200: forming a silicon oxide protection layer on the substrate, wherein the silicon oxide protection layer conformally covers the polysilicon gate structure.
[0046] The embodiment of the present application conformally covers the polysilicon gate structure with a silicon oxide protective layer, so that the surface of the polysilicon gate structure is isolated from the external chemical environment and is not affected by external processes, thereby avoiding damage to the polysilicon gate structure by subsequent wet cleaning processes, chemical etching processes or other semiconductor process processes, effectively preventing the characteristic size of the polysilicon gate structure from being reduced, ensuring the stability of the shape structure and electrical properties of the polysilicon gate structure, and facilitating improving the production yield and reliability of semiconductor devices.
[0047] Since the silicon oxide protective layer has good chemical resistance and thermal stability, the silicon oxide protective layer is selected to protect the polysilicon gate structure. This can not only prevent the polysilicon gate structure from being corroded or damaged during the subsequent wet cleaning process, chemical etching process or other semiconductor process, but also can withstand various treatments at high temperatures (such as ion implantation and annealing operations) in subsequent processes, and can maintain structural stability under high temperature conditions, providing stable and reliable protection for the polysilicon gate structure.
[0048] See also Figure 2 In some embodiments, the method for preparing the semiconductor structure may further include the following steps S300 to S400:
[0049] S300: removing the silicon oxide protective layer;
[0050] S400: forming a gate sidewall on the sidewall of the polysilicon gate structure.
[0051] The following combination Figure 3 to Figure 4 The method for preparing the semiconductor structure provided in the embodiment of the present application is described in detail.
[0052] In step S100, refer to Figure 3, providing a substrate, on which a polysilicon gate structure 10 is formed.
[0053] In some embodiments, Figure 3 As shown, the polysilicon gate structure 10 may specifically include a doped polysilicon layer 10a and an intrinsic polysilicon layer 10b which are sequentially stacked in a direction away from the substrate.
[0054] The doped polysilicon layer 10a increases the conductivity of the polysilicon gate structure 10 by introducing impurity ions such as phosphorus or boron, thereby reducing the overall resistance of the polysilicon gate structure 10, which is beneficial to improving the conductivity of the semiconductor device, reducing signal transmission delay, and thus speeding up the switching speed of the semiconductor device.
[0055] The doped polysilicon layer 10a and the intrinsic polysilicon layer 10b are stacked to effectively reduce the capacitive coupling effect. Since the intrinsic polysilicon layer 10b is undoped, it has a lower conductivity and can act as a buffer layer between the doped polysilicon layer 10a and the gate dielectric layer, which is beneficial to reduce the capacitive coupling effect, reduce leakage current, and optimize the electrical characteristics of the semiconductor device.
[0056] In step S200, refer to Figure 4 , a silicon oxide protection layer 20 is formed on the substrate, and the silicon oxide protection layer 20 conformally covers the polysilicon gate structure 10 .
[0057] The embodiment of the present application does not specifically limit the constituent materials of the silicon oxide protection layer 20 , and the characteristics of the silicon oxide protection layer 20 can be adjusted according to different process requirements, as long as it can protect the polysilicon gate structure 10 from damage in the subsequent process flow.
[0058] In some embodiments, the silicon oxide protective layer 20 may specifically include any one or a combination of an undoped silicate glass (USG) layer, a silicon-rich oxide (SRO) layer, and a plasma-enhanced tetraethyl orthosilicate (PETEOS) layer. The aforementioned materials can provide excellent chemical stability to prevent the silicon oxide protective layer 20 from adverse reactions or falling off in subsequent process flows.
[0059] The embodiment of the present application does not specifically limit the thickness of the silicon oxide protective layer 20 , and the thickness of the silicon oxide protective layer 20 can be adjusted according to different process requirements.
[0060] In some embodiments, the thickness of the silicon oxide protection layer 20 may specifically range from 1 nm to 50 nm. For example, the thickness of the silicon oxide protection layer 20 may be 1 nm, 10 nm, 25 nm, 30 nm, or 50 nm.
[0061] In the above embodiment, the thickness of the silicon oxide protective layer 20 is controlled between 1 nm and 50 nm, ensuring that the silicon oxide protective layer 20 is thin enough to maintain process flexibility and thick enough to provide an effective physical and chemical barrier to prevent subsequent wet cleaning processes, chemical etching processes or other semiconductor process processes from damaging the polysilicon gate structure 10.
[0062] The embodiment of the present application does not specifically limit the method of forming the silicon oxide protection layer 20 on the substrate in step S200. In some embodiments, the silicon oxide protection layer 20 can be deposited on the substrate by a physical vapor deposition (PVD) process.
[0063] The physical vapor deposition rate is usually fast, and a uniform silicon oxide protective layer 20 can be obtained in a short time. It is also easy to control the thickness of the silicon oxide protective layer 20. For example, nanometer-level thickness control can be achieved, which can effectively cover the surface of the polysilicon gate structure 10 without increasing the layer thickness too much, which is conducive to meeting the miniaturization design requirements of semiconductor structures.
[0064] In addition, the physical vapor deposition equipment is compatible with a variety of different types of silicon oxide materials and can be applied to various substrates and structures at the same time. Therefore, the physical vapor deposition process is used to form the silicon oxide protective layer 20, which facilitates the flexible selection of silicon oxide materials according to different process requirements to meet a variety of application scenarios.
[0065] Optionally, when the silicon oxide protective layer 20 is deposited on the substrate by a physical vapor deposition process, the deposition temperature may be controlled to be 300° C. or less.
[0066] The lower deposition temperature (less than or equal to 300°C) further reduces the impact on the thermal load of the substrate, which is more suitable for processes of heat-sensitive materials or multi-layer structure devices, and helps to ensure the stability of the front-end process. In addition, the lower deposition temperature (less than or equal to 300°C) can also reduce the stress and deformation caused by temperature changes, thereby enabling better integration with other semiconductor materials.
[0067] In some other embodiments, a tube furnace may also be used to grow the silicon oxide protection layer 20 on the substrate.
[0068] By growing the silicon oxide protective layer 20 using a tube furnace, a dense and uniform silicon oxide protective layer 20 can be formed, which forms a good interface bonding with the polysilicon gate structure 10, thereby improving the electrical properties and stability of the interface, thereby helping to reduce the leakage current and interface defects of the semiconductor structure and improve the reliability of the semiconductor device.
[0069] Furthermore, since the tube furnace uses an atomic-level oxidation process, the formed silicon oxide protective layer 20 has a higher density and a lower impurity content. Therefore, for silicon oxide protective layers 20 that require high density and purity, the tube furnace growth method is more advantageous.
[0070] Optionally, when the silicon oxide protective layer 20 is grown on the substrate using a tube furnace, the growth temperature may be controlled to be 500° C. or less.
[0071] A relatively low growth temperature (less than or equal to 500° C.) can ensure the formation of a high-quality silicon oxide protection layer 20 without causing thermal damage to a relatively sensitive substrate.
[0072] Moreover, the silicon oxide protective layer 20 grown in a low-temperature (less than or equal to 500°C) tube furnace has a higher density, which can ensure that the silicon oxide protective layer 20 has stronger tolerance during wet cleaning processes, chemical etching processes or other semiconductor processes, and is therefore more suitable for the manufacture of semiconductor devices with high performance and high reliability requirements.
[0073] In some embodiments, the method for preparing the semiconductor structure may further include the following steps S300 to S400 .
[0074] In step S300, the silicon oxide protective layer 20 is removed. The schematic diagram of the cross-sectional structure of the structure obtained after removing the silicon oxide protective layer 20 can be referred to Figure 3 .
[0075] In step S400 , a gate spacer is formed on the sidewall of the polysilicon gate structure 10 .
[0076] That is, in the above embodiment, the silicon oxide protection layer 20 may be removed before forming the gate spacer on the sidewall of the polysilicon gate structure 10 .
[0077] As an example, a wet cleaning process may be used to remove the silicon oxide protective layer 20. In this way, the silicon oxide protective layer 20 can be removed efficiently and safely without adding additional process steps, which not only does not cause additional damage to the polysilicon gate structure 10, but also is simple and easy to implement.
[0078] In conventional semiconductor manufacturing processes, especially in a multi-layer polysilicon gate structure 10, there is a difference in etching rates between the doped polysilicon layer 10a and the intrinsic polysilicon layer 10b. Due to the influence of ion implantation, the doped polysilicon layer 10a after doping has a significantly faster loss rate than the undoped intrinsic polysilicon layer 10b. Especially during the wet cleaning process, the profiles of the doped and undoped regions often show step delamination, which further affects the performance stability of the semiconductor device.
[0079] In the embodiment of the present application, by conformally covering the surface of the polysilicon gate structure 10 with a silicon oxide protection layer 20, comprehensive protection of the doped polysilicon layer 10a and the intrinsic polysilicon layer 10b can be achieved, thereby avoiding step stratification of the contours of the two in subsequent processes, and ensuring that the performance stability of the semiconductor device is not affected.
[0080] According to some embodiments, the present application further provides a semiconductor structure. The semiconductor structure is prepared by the method for preparing the semiconductor structure provided by any of the above embodiments. Therefore, the technical effects that can be achieved by the above preparation methods can also be achieved by the semiconductor structure, which will not be described in detail here.
[0081] According to some embodiments, the present application further provides a semiconductor device on the other hand. The manufacturing process of the semiconductor device includes the steps of the method for preparing the semiconductor structure provided in any of the aforementioned embodiments; or includes the semiconductor structure provided in the aforementioned embodiments. Therefore, the technical effects that can be achieved by the aforementioned preparation method and semiconductor structure can also be achieved by the semiconductor device, which will not be described in detail here.
[0082] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0083] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, on which a polysilicon gate structure is formed; A silicon oxide protection layer is formed on the substrate, and the silicon oxide protection layer conformally covers the polysilicon gate structure.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The silicon oxide protective layer includes an undoped silicate glass layer, a silicon rich oxide layer and / or a plasma enhanced tetraethyl orthosilicate layer.
3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the silicon oxide protective layer ranges from 1 nm to 50 nm.
4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of forming a silicon oxide protective layer on the substrate comprises: The silicon oxide protective layer is deposited on the substrate by a physical vapor deposition process; or, the silicon oxide protective layer is grown on the substrate by a tube furnace.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that: When the silicon oxide protective layer is deposited on the substrate by the physical vapor deposition process, the deposition temperature is less than or equal to 300° C.; When the silicon oxide protective layer is grown on the substrate using the tube furnace, the growth temperature is less than or equal to 500°C.
6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The preparation method further comprises: removing the silicon oxide protective layer; A gate sidewall is formed on the sidewall of the polysilicon gate structure.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The removing of the silicon oxide protective layer comprises: The silicon oxide protective layer is removed by a wet cleaning process.
8. The method for preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that: The polysilicon gate structure includes a doped polysilicon layer and an intrinsic polysilicon layer which are sequentially stacked in a direction away from the substrate.
9. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1 to 8.
10. A semiconductor device, characterized in that: The manufacturing process of the semiconductor device includes the steps of the method for preparing a semiconductor structure according to any one of claims 1 to 8; or includes the semiconductor structure according to claim 9.