Thin film transistor and preparation method thereof, array substrate and display device

Abstract

The invention discloses a thin film transistor and a preparation method thereof, an array substrate and a display device.The preparation method of the thin film transistor comprises the steps that a first grid electrode protection layer and a first source / drain electrode protection layer are formed through chemical plating or sputtering film forming, and meanwhile the first protection layer serves as a catalyst of a copper metal layer in a grid electrode and a source / drain electrode; and the copper metal layer is chemically plated, and complicated vacuum deposition of the copper metal layer is not needed, so that the manufacturing cost of the copper metal layer is reduced. After the copper metal layer is formed, a blackening process is added in a chemical plating mode to form a second protection layer for the grid electrode metal layer and the source / drain electrode metal layer, so that the grid electrode metal layer and the source / drain electrode metal layer which are exposed outside are protected, and copper or copper alloy can be prevented from being in contact with external water and oxygen or copper ions can be prevented from being migrated; therefore, the oxidation corrosion of copper or copper alloy is reduced. Meanwhile, the first protection layer and the second protection layer contain palladium metal, reflection of grid electrode and source / drain electrode circuits is reduced, and reliability and contrast ratio of products are improved.

Description

Technical Field

[0001] The present invention relates to the field of light-emitting display technology, and in particular to a thin film transistor and a preparation method thereof, an array substrate and a display device. Background Art

[0002] Flat panel display technology plays a vital role in modern electronic products. Thin-film transistor liquid crystal displays and organic light-emitting diodes have become the mainstream choice in the market due to their advantages such as small size and diverse display effects. The core of these display technologies lies in driving the circuits and thin-film transistors on the backplane, which are key components for achieving high-resolution display and precise control.

[0003] In the process of manufacturing these core components, a series of thin film layers need to be constructed on the substrate, including gate electrode, gate insulation layer, active layer, source / drain electrode, etc., to finally form a complex circuit structure. Specifically, the existing array substrate preparation process usually involves sputtering to form a gate electrode on the substrate, followed by depositing a gate insulation layer, then depositing an active layer, then sputtering a source / drain electrode, and finally depositing a passivation layer and pixel electrode. This continuous process has extremely high requirements for accuracy and material properties.

[0004] In the existing process of making the gate electrode and source / drain electrode, a protective layer and copper or copper alloy metal are first vacuum deposited, and then lithography and etching are performed to obtain the copper or copper alloy circuits of the gate and source / drain electrodes. The process is long and requires more vacuum deposition equipment, lithography equipment and etching (dry or wet etching) equipment, with high investment cost and high material cost (expensive metal target material and low target material utilization rate) and other defects.

[0005] In addition, the copper or copper alloy materials used in the prior art for preparing the gate electrode and the source / drain electrode have some defects. Copper, as a relatively active metal, can easily react with oxygen in the environment, resulting in oxidation, or diffuse into the active layer. This uncontrolled copper diffusion can contaminate the active layer, affect the mobility of carriers, thereby reducing the performance of the display device and ultimately causing product defects. Copper surface oxidation can also lead to lead corrosion, resulting in a serious decline in product performance. In order to solve these problems, the industry usually adds at least one metal or non-metal protective layer on the upper and lower surfaces of copper or copper alloys to protect the copper leads from environmental influences.

[0006] Since the thickness of the copper layer is usually about 500 nanometers, the existing process of sputtering coating and then photolithography patterning is complicated and time-consuming. The existing manufacturing method will also cause some surfaces of some copper or copper alloy circuits to be unprotected, which may cause copper ions to diffuse into the active layer and cause changes in TFT performance, or oxidation reactions to cause corrosion. In fact, copper corrosion has become one of the most prominent defects in copper process flat panel display devices. Therefore, developing new protection technologies and manufacturing processes to effectively prevent copper oxidation and diffusion is of great significance to improving the reliability and life of flat panel display devices. Summary of the invention

[0007] The main purpose of the present invention is to provide a method for preparing a thin film transistor, which aims to solve the problem in the prior art that copper or copper metal lines are exposed, causing copper ions to migrate into the active layer or the copper metal surface is prone to oxidation corrosion and high reflectivity, so as to improve the reliability and contrast of the display device.

[0008] In order to achieve the above object, the present invention provides a method for preparing a thin film transistor, the method for preparing the thin film transistor comprising the following steps:

[0009] A pattern including a gate electrode is formed on a base substrate, wherein the gate electrode includes a first gate protection layer, a gate electrode metal layer and a second gate protection layer (blackening layer) formed sequentially on the base substrate; wherein the gate electrode metal layer is made of copper or a copper alloy;

[0010] forming a pattern including a gate insulating layer covering the gate electrode and the base substrate on the substrate on which the gate electrode is formed;

[0011] Forming a pattern including an active layer located above the gate electrode and a pattern including an etching stopper layer located above the active layer on the substrate on which the gate insulating layer is formed;

[0012] Forming a pattern including a source / drain electrode on the substrate on which the etching stop layer is formed, wherein the source / drain electrode includes a first source / drain protection layer, a source / drain electrode metal layer, and a second source / drain protection layer (blackening layer) sequentially formed on the base substrate, wherein the source / drain electrode metal layer is made of copper or a copper alloy;

[0013] forming a pattern including a passivation layer on the substrate on which the source / drain electrode pattern is formed;

[0014] A pattern including a pixel electrode is formed on the substrate on which the passivation layer pattern is formed.

[0015] In one embodiment, forming the gate electrode pattern comprises the following steps:

[0016] 1) Formation and patterning of the first gate protection layer:

[0017] A photoresist having a palladium metal nanoparticle catalyst is coated on the substrate as a base layer, and a pattern driving layer is formed after ultraviolet light exposure and development, and the pattern of the pattern driving layer is consistent with the gate circuit pattern;

[0018] On the pattern driving layer, a layer of metal for blackening is chemically plated according to the gate line pattern to form a first gate protection layer, wherein the first gate protection layer is palladium metal with a thickness of 20-100 nm, preferably 30-60 nm;

[0019] Preferably, the chemical plating is to immerse the substrate including the pattern driving layer in a chemical plating solution for 1 to 4 minutes, wherein the chemical plating solution comprises: 1.5 g / L palladium chloride, 6 g / L ethylenediamine, 5 g / L sodium hypophosphite, 10 g / L disodium ethylenediaminetetraacetate, 150 ml / L ammonia water, 0.7 g / L polyethylene glycol, pH value is 6, temperature is 60°C;

[0020] 2) Forming a patterned gate electrode metal layer:

[0021] Performing chemical copper plating to deposit metallic copper on the first gate protection layer with a thickness of 200-800 nm, preferably 400-600 nm, to form a gate metal layer and a gate line pattern including the first gate protection layer and the gate metal layer;

[0022] Preferably, copper salt, complexing agent, pH adjusting agent, reducing agent and stabilizer are mixed to prepare copper plating solution; the substrate including the gate circuit pattern composed of the first gate protection layer is placed in the copper plating solution for chemical copper plating, the copper plating time is 0.5 to 5 minutes, the temperature of the copper plating solution is 30 to 45° C., and metallic copper is deposited on the first gate protection layer to form a gate metal layer and a gate circuit pattern including the first gate protection layer and the gate metal layer;

[0023] 3) Forming a patterned second gate protection layer (blackened layer):

[0024] Plating a second gate protection layer (blackening layer) metal to form a blackening layer to protect the surface of the gate metal layer; the second gate protection layer (blackening layer) is metal palladium with a thickness of 20-100 nm, preferably 30-60 nm;

[0025] Preferably, 0.5g / L palladium chloride, 10g / L sodium citrate, 8g / L sodium acetate, 10ml / L formic acid, and 0.3g / L sodium dodecyl sulfonate are taken to prepare a blackening solution. The substrate including the gate circuit pattern including the first gate protection layer and the gate metal layer is immersed in the blackening solution for reaction, and the reaction conditions are pH 5, time 1~4min, temperature 40~60℃, and a second gate protection layer (blackening layer) is chemically deposited on the gate metal layer with a thickness of 30~80nm, preferably 30~60nm; a palladium metal layer is formed to protect the surface of the gate metal layer, and a complete gate pattern with the first and second protection layers is obtained;

[0026] Preferably, a substrate including a first gate protection layer, a gate metal layer and a second gate protection layer (blackening layer) is immersed in an aqueous solution consisting of nickel sulfate and sodium dihydrogen hypophosphite at a temperature of 25 to 60° C. for 0.5 to 2 minutes to form a nickel metal protection layer on the surface of the palladium metal layer as a second gate protection layer (blackening layer).

[0027] In one embodiment, forming the source / drain electrode pattern comprises the following steps:

[0028] 1) Formation and patterning of the first source / drain electrode protection layer:

[0029] A photoresist base layer having a palladium metal nanoparticle catalyst is coated on a substrate including an etching stop layer, and a pattern driving layer is formed through ultraviolet light exposure and development, wherein the pattern of the pattern driving layer is consistent with the source / drain electrode circuit pattern;

[0030] On the pattern driving layer, a layer of metal for blackening is chemically plated according to the source / drain electrode line pattern to form a first source / drain electrode protection layer, wherein the first source / drain electrode protection layer is palladium metal with a thickness of 20-100 nm, preferably 30-60 nm;

[0031] Preferably, the chemical plating is to immerse the substrate including the pattern driving layer in a chemical plating solution for 1 to 4 minutes, wherein the chemical plating solution comprises: 1.5 g / L palladium chloride, 6 g / L ethylenediamine, 5 g / L sodium hypophosphite, 10 g / L disodium ethylenediaminetetraacetate, 150 ml / L ammonia water, 0.7 g / L polyethylene glycol, pH value is 6, temperature is 60°C;

[0032] 2) Forming patterned source / drain electrode metal layers:

[0033] Performing chemical copper plating to deposit metallic copper on the first source / drain electrode protection layer with a thickness of 200-800 nm, preferably 400-600 nm, to form a source / drain electrode metal layer and a source / drain electrode circuit pattern including the first source / drain electrode protection layer and the source / drain electrode metal layer;

[0034] Preferably, copper salt, complexing agent, pH adjusting agent, reducing agent and stabilizer are mixed to prepare a copper plating solution; the substrate including the source / drain electrode circuit pattern composed of the first source / drain electrode protection layer is placed in the copper plating solution for chemical copper plating, the copper plating time is 0.5 to 5 minutes, the temperature of the copper plating solution is 30 to 45° C., and metallic copper is deposited on the first gate protection layer to form a source / drain electrode metal layer and a source / drain electrode circuit pattern including the first source / drain electrode protection layer and the gate metal layer;

[0035] 3) Forming a patterned second source / drain electrode protective layer (blackened layer):

[0036] Plating a second source / drain electrode protection layer (blackening layer) metal to form a blackening layer to protect the surface of the source / drain electrode metal layer; the second source / drain electrode protection layer (blackening layer) is metal palladium with a thickness of 20 to 100 nm, preferably 30 to 60 nm;

[0037] Preferably, 0.5g / L palladium chloride, 10g / L sodium citrate, 8g / L sodium acetate, 10ml / L formic acid, and 0.3g / L sodium dodecyl sulfonate are taken to prepare a blackening solution. The substrate including the source / drain electrode circuit pattern including the first source / drain electrode protection layer and the source / drain electrode metal layer is immersed in the blackening solution for reaction, and the reaction conditions are pH 5, time 1~4min, temperature 40~60℃, and a second source / drain electrode protection layer (blackening layer) is chemically deposited on the source / drain electrode metal layer with a thickness of 30~80nm, preferably 30~60nm; a palladium metal layer is formed to protect the surface of the source / drain electrode metal layer, and a complete source / drain electrode pattern with the first and second protection layers is obtained;

[0038] Preferably, a substrate including a first source / drain electrode protection layer, a source / drain electrode metal layer and a second source / drain electrode protection layer (blackening layer) is immersed in an aqueous solution consisting of nickel sulfate and sodium dihydrogen hypophosphite at a temperature of 25 to 60°C for 0.5 to 2 minutes to form a nickel metal protection layer on the surface of the palladium metal layer as a second source / drain electrode protection layer (blackening layer).

[0039] The present invention also provides a method for preparing a thin film transistor, comprising the following steps:

[0040] A pattern including a gate electrode is formed on a base substrate, wherein the gate electrode includes a first gate protection layer, a gate electrode metal layer and a second gate protection layer (blackening layer) formed sequentially on the base substrate; wherein the gate electrode metal layer is made of copper or a copper alloy;

[0041] forming a pattern including a gate insulating layer covering the gate electrode and the base substrate on the substrate on which the gate electrode is formed;

[0042] Forming a pattern including an active layer located above the gate electrode and a pattern including an etching stopper layer located above the active layer on the substrate on which the gate insulating layer is formed;

[0043] Forming a pattern including a source / drain electrode on the substrate on which the etching stop layer is formed, wherein the source / drain electrode includes a first source / drain protection layer, a source / drain electrode metal layer, and a second source / drain protection layer (blackening layer) sequentially formed on the base substrate, wherein the source / drain electrode metal layer is made of copper or a copper alloy;

[0044] forming a pattern including a passivation layer on the substrate on which the source / drain electrode pattern is formed;

[0045] A pattern including a pixel electrode is formed on the substrate on which the passivation layer pattern is formed.

[0046] In one embodiment, forming the gate electrode pattern comprises the following steps:

[0047] 1) Formation and patterning of the first gate protection layer:

[0048] Taking the processed substrate in a vacuum chamber, sputtering and depositing a palladium metal film layer thereon by physical vapor deposition (PVD) with a thickness of 20 to 100 nm, preferably 30 to 60 nm, as a first gate protection layer thin film;

[0049] The first gate protection layer film on the substrate is patterned by yellow light and etching process to form a first gate protection layer with a pattern consistent with the final gate line; the etching can be dry etching or wet etching;

[0050] 2) Forming a patterned gate electrode metal layer:

[0051] Performing chemical copper plating to deposit metallic copper on the first gate protection layer with a thickness of 200-800 nm, preferably 400-600 nm, to form a gate metal layer and a gate line pattern including the first gate protection layer and the gate metal layer;

[0052] Preferably, copper salt, complexing agent, pH adjusting agent, reducing agent and stabilizer are mixed to prepare copper plating solution; the substrate including the gate circuit pattern composed of the first gate protection layer is placed in the copper plating solution for chemical copper plating, the copper plating time is 0.5 to 5 minutes, the temperature of the copper plating solution is 30 to 45° C., and metallic copper is deposited on the first gate protection layer to form a gate metal layer and a gate circuit pattern including the first gate protection layer and the gate metal layer;

[0053] 3) Forming a patterned second gate protection layer (blackened layer):

[0054] Plating a second gate protection layer (blackening layer) metal to form a blackening layer to protect the surface of the gate metal layer; the second gate protection layer (blackening layer) is metal palladium with a thickness of 20-100 nm, preferably 30-60 nm;

[0055] Preferably, 0.5g / L palladium chloride, 10g / L sodium citrate, 8g / L sodium acetate, 10ml / L formic acid, and 0.3g / L sodium dodecyl sulfonate are taken to prepare a blackening solution. The substrate including the gate circuit pattern including the first gate protection layer and the gate metal layer is immersed in the blackening solution for reaction, and the reaction conditions are pH 5, time 1~4min, temperature 40~60℃, and a second gate protection layer (blackening layer) is chemically deposited on the gate metal layer with a thickness of 30~80nm, preferably 30~60nm; a palladium metal layer is formed to protect the surface of the gate metal layer, and a complete gate pattern with the first and second protection layers is obtained;

[0056] Preferably, a substrate including a first gate protection layer, a gate metal layer and a second gate protection layer (blackening layer) is immersed in an aqueous solution consisting of nickel sulfate and sodium dihydrogen hypophosphite at a temperature of 25 to 60° C. for 0.5 to 2 minutes to form a nickel metal protection layer on the surface of the palladium metal layer as a second gate protection layer (blackening layer).

[0057] In one embodiment, forming the source / drain electrode pattern comprises the following steps:

[0058] 1) Formation and patterning of the first source / drain electrode protection layer:

[0059] A substrate including an etching stop layer is placed in a vacuum chamber, and a palladium metal film layer is sputtered and deposited thereon by physical vapor deposition (PVD) with a thickness of 20 to 100 nm, preferably 30 to 60 nm, as a first gate protection layer thin film;

[0060] The first gate protection layer film on the substrate is patterned by yellow light and etching process to form a first gate protection layer with a pattern consistent with the final gate line; the etching can be dry etching or wet etching;

[0061] 2) Forming patterned source / drain electrode metal layers:

[0062] Performing chemical copper plating to deposit metallic copper on the first source / drain electrode protection layer with a thickness of 200-800 nm, preferably 400-600 nm, to form a source / drain electrode metal layer and a source / drain electrode circuit pattern including the first source / drain electrode protection layer and the source / drain electrode metal layer;

[0063] Preferably, copper salt, complexing agent, pH adjusting agent, reducing agent and stabilizer are mixed to prepare a copper plating solution; the substrate including the source / drain electrode circuit pattern composed of the first source / drain electrode protection layer is placed in the copper plating solution for chemical copper plating, the copper plating time is 0.5 to 5 minutes, the temperature of the copper plating solution is 30 to 45° C., and metallic copper is deposited on the first gate protection layer to form a source / drain electrode metal layer and a source / drain electrode circuit pattern including the first source / drain electrode protection layer and the gate metal layer;

[0064] 3) Forming a patterned second source / drain electrode protection layer (blackened layer):

[0065] Plating a second source / drain electrode protection layer (blackening layer) metal to form a blackening layer to protect the surface of the source / drain electrode metal layer; the second source / drain electrode protection layer (blackening layer) is metal palladium with a thickness of 20 to 100 nm, preferably 30 to 60 nm;

[0066] Preferably, 0.5g / L palladium chloride, 10g / L sodium citrate, 8g / L sodium acetate, 10ml / L formic acid, and 0.3g / L sodium dodecyl sulfonate are taken to prepare a blackening solution. The substrate including the source / drain electrode circuit pattern including the first source / drain electrode protection layer and the source / drain electrode metal layer is immersed in the blackening solution for reaction, and the reaction conditions are pH 5, time 1~4min, temperature 40~60℃, and a second source / drain electrode protection layer (blackening layer) is chemically deposited on the source / drain electrode metal layer with a thickness of 30~80nm, preferably 30~60nm; a palladium metal layer is formed to protect the surface of the source / drain electrode metal layer, and a complete source / drain electrode pattern with the first and second protection layers is obtained;

[0067] Preferably, a substrate including a first source / drain electrode protection layer, a source / drain electrode metal layer and a second source / drain electrode protection layer (blackening layer) is immersed in an aqueous solution consisting of nickel sulfate and sodium dihydrogen hypophosphite at a temperature of 25 to 60°C for 0.5 to 2 minutes to form a nickel metal protection layer on the surface of the palladium metal layer as a second source / drain electrode protection layer (blackening layer).

[0068] The present invention further provides a thin film transistor, comprising a gate electrode, an active layer and a source / drain electrode formed on a substrate, and a gate insulating layer located between the gate electrode and the active layer, wherein:

[0069] The gate electrode comprises a gate electrode metal layer and a first gate protection layer, wherein the first protection layer is located between the gate electrode metal layer and the substrate to isolate the substrate from the gate electrode metal layer;

[0070] The material of the first gate protection layer is metal palladium;

[0071] The gate electrode metal layer is made of copper or copper alloy;

[0072] The gate electrode further includes a second gate protection layer (blackened layer) located on the surface of the gate electrode metal layer away from the first protection layer and on both sides of the cross section of the gate electrode metal layer;

[0073] The material of the second gate protection layer (blackened layer) is metal palladium;

[0074] Preferably, the second gate protection layer (blackened layer) is palladium and nickel;

[0075] The thin film transistor is obtained by the above-mentioned method for preparing the thin film transistor.

[0076] In one embodiment, the source / drain electrode comprises a source / drain electrode metal layer and a first source / drain protection layer, wherein the first source / drain protection layer is located between the source / drain electrode metal layer and the active layer to isolate the source / drain electrode metal layer from the active layer;

[0077] The material of the first source / drain electrode protection layer is metal palladium;

[0078] The material of the source / drain electrode metal layer is copper or copper alloy;

[0079] The source / drain electrode further includes a second source / drain electrode protection layer (blackened layer), which is located on the surface of the source / drain electrode metal layer away from the first protection layer and on both sides of the cross section of the source / drain electrode metal layer;

[0080] The material of the second source / drain electrode protection layer (blackened layer) is metal palladium;

[0081] Preferably, the second source / drain electrode protective layer (blackening layer) is palladium and nickel.

[0082] The present invention further provides an array substrate, which includes the above-mentioned thin film transistor.

[0083] The present invention further provides a display device, which includes the above-mentioned array substrate.

[0084] The technical solution of the present invention changes the manufacturing method of the gate and source / drain electrode to first form the first gate protection layer and the first source / drain electrode protection layer by chemical plating or sputtering film formation. At the same time, the first protection layer also serves as a catalyst for the copper metal layer in the gate and source / drain electrode, and the copper metal layer is chemically plated without complicated vacuum deposition of the copper metal layer, thereby reducing the manufacturing cost of the copper metal layer. After the copper metal layer is formed, a blackening process is added by chemical plating to form a second protection layer for the gate metal layer and the source / drain electrode metal layer, which protects the gate metal layer and the source / drain electrode metal layer exposed to the outside, and can prevent copper or copper alloys from contacting with external water and oxygen or the migration of copper ions, thereby reducing the oxidation corrosion of copper or copper alloys. At the same time, the first and second protection layers contain palladium metal, which reduces the reflection of the gate and source / drain electrode circuits and improves the reliability and contrast of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] Figure 1 A schematic diagram of a manufacturing process of a thin film transistor array substrate according to an embodiment of the present application;

[0086] Figure 2 for Figure 5 An enlarged view of the structure of the gate electrode of the thin film transistor;

[0087] Figure 3 for Figure 5 A magnified structural diagram of the source / drain electrodes of the thin film transistor;

[0088] Figure 4 A schematic diagram of the manufacturing process of an array substrate of an existing thin film transistor;

[0089] Figure 5 This is a schematic diagram of the structure of the array substrate of the thin film transistor of the present application;

[0090] Figure 6 This is an embodiment of the present application Figure 5 An enlarged view of the structure of the gate electrode of the thin film transistor;

[0091] Figure 7 This is an embodiment of the present application Figure 5 A magnified structural diagram of the source / drain electrodes of the thin film transistor;

[0092] In the figure: 1-substrate, 2-gate electrode, 3-gate insulating layer, 4-active layer, 5-etching barrier layer, 6-source / drain electrode, 7-passivation layer, 8-pixel electrode, 21-first gate protection layer, 22-second gate protection layer, 23-second gate protection layer (blackening layer), 20-gate electrode metal layer, 61-first source / drain protection layer, 60-source / drain electrode metal layer, 62-second source / drain protection layer, 63-second source / drain protection layer (blackening layer). DETAILED DESCRIPTION

[0093] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0094] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0095] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0096] In the description of the present invention, it should be understood that the terms "upper", "lower", "inside", "outside", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use, or are directions or positional relationships commonly understood by those skilled in the art. These directions or positional relationships are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0097] Furthermore, the terms “first”, “second”, etc. are merely used for distinguishing descriptions and should not be understood as indicating or implying relative importance.

[0098] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms such as "setting" and "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0099] like Figure 1-7 As shown, the present application proposes a method for preparing a thin film transistor, comprising the following steps:

[0100] Step P1: Substrate processing.

[0101] Take a substrate (substrate), which can be a glass substrate 1 or a resin material substrate, and clean, dry and / or plasma treat it to ensure the cleanliness of the substrate. In order to increase the adhesion of the subsequent film layer to the substrate, an inorganic thin film such as silicon nitride or silicon oxide can be deposited on the substrate 1, or other inorganic insulating materials with the same or similar properties as silicon nitride or silicon oxide can be deposited, with a thickness of 10nm-300nm.

[0102] Step P2: Fabrication of gate electrode 2. This step includes three sub-steps P21 to P23.

[0103] P21: On the cleaned substrate 1, a first gate electrode protection layer 21 is formed and patterned.

[0104] A photoresist having a palladium metal nanoparticle catalyst is coated on the substrate 1 as a base layer, and a pattern driving layer is formed after ultraviolet light exposure and development, and the pattern of the pattern driving layer is consistent with the circuit pattern of the gate 2 .

[0105] On the pattern driving layer, a layer of metal for blackening is chemically plated according to the gate line pattern to form a first gate protection layer 21. The metal of the first gate protection layer 21 is palladium with a thickness of 50nm. The chemical plating is to immerse the substrate including the pattern driving layer in a chemical plating solution for reaction for 2 minutes. The chemical plating solution consists of: 1.5g / L palladium chloride, 6g / L ethylenediamine, 5g / L sodium hypophosphite, 10g / L disodium ethylenediaminetetraacetate, 150ml / L ammonia water, 0.7g / L polyethylene glycol 200, pH value is 6, temperature is 60°C.

[0106] P22: forming a patterned gate electrode metal layer 20, the material of the layer is copper or copper alloy, and the thickness is 500 nm.

[0107] Copper salt, complexing agent, pH adjusting agent, reducing agent and stabilizer are mixed to prepare copper plating solution; a substrate including the first gate protection layer 21 is placed in the copper plating solution for chemical copper plating, the copper plating time is 0.5min, the copper plating solution temperature is 30°C, and metallic copper is deposited on the first gate protection layer 21 to form a gate metal layer 20 and a gate 2 circuit pattern including the first gate protection layer 21 and the gate metal layer 20. The copper salt is copper sulfate, the complexing agent is disodium ethylenediaminetetraacetate, the pH adjusting agent is sodium hydroxide, the reducing agent is formaldehyde, and the stabilizer is 2-2 bipyridine. The chemical reaction of this step is: Pd + Cu2+ → Cu+ Pd2+.

[0108] P23: forming a patterned second gate protection layer (blackened layer) 23, whose material is palladium and has a thickness of 50 nm.

[0109] Take 0.5g / L palladium chloride, 10g / L sodium citrate, 8g / L sodium acetate, 10ml / L formic acid, and 0.3g / L sodium dodecyl sulfonate to prepare a blackening solution. The substrate including the gate 2 circuit pattern including the first gate protection layer 21 and the gate metal layer 20 is immersed in the blackening solution for reaction. The reaction conditions are pH 5, time 2min, temperature 50°C, and chemically deposit a second gate protection layer (blackening layer) 23 on the gate metal layer 20 with a thickness of 50nm. A palladium metal layer is formed to protect the surface of the gate metal layer to obtain a complete gate 2 pattern with the first and second protection layers. The chemical reaction of this step is: Cu + Pd2+ → Cu2+ +Pd.

[0110] Preferably, in order to further enhance the performance of the second gate protection layer (blackening layer) 23, a substrate including the first gate protection layer 21, the gate metal layer 20 and the second gate protection layer (blackening layer) 23 is taken, immersed in a mixed solution of 70g / L nickel sulfate and 0.1g / L sodium dihydrogen hypophosphite, the pH value is adjusted to 4 with boric acid, heated to 45°C for 2 minutes, and a nickel metal protection layer is formed on the surface of the palladium metal layer as the second gate protection layer (blackening layer) 23, and the total thickness of the two is 50nm. The chemical reaction of this step is: Ni2+ + H2PO2-+ H2O → H2PO3- + 2H+ + Ni.

[0111] Step P3: forming a pattern of the gate insulating layer 3 on the substrate 1 on which the gate electrode 2 is formed.

[0112] Deposit an insulating layer 3 thin film, wherein the insulating layer 3 is made of silicon nitride, silicon oxide, or other inorganic insulating materials with the same or similar properties as silicon nitride and silicon oxide. Form a pattern of the insulating layer 3 by a yellow light process.

[0113] Step P4: forming a pattern including an active layer 4 located above the gate electrode 2 on the substrate 1 with the gate insulating layer 3 formed thereon.

[0114] P41: depositing an active layer 4 thin film, wherein the active layer 4 is made of metal oxide semiconductor, crystalline silicon or amorphous silicon.

[0115] P42: The active layer 4 pattern is formed by yellow light process.

[0116] Step P5: forming a pattern of an etching stop layer 5 on the substrate 1 on which the active layer 4 is formed.

[0117] P51: Depositing an etching stop layer 5 thin film, wherein the etching stop layer 5 is made of silicon nitride, silicon oxide, or other inorganic insulating materials having the same or similar properties as silicon nitride and silicon oxide.

[0118] P52: The pattern of the etching stop layer 5 is formed by a yellow light process. The etching stop layer 5 is used to prevent the active layer from being etched when the data line layer forms a channel.

[0119] Step P6: forming a pattern including source / drain electrodes 6 on the substrate 1 on which the etching stop layer 5 is formed.

[0120] P61: forming a first source / drain electrode protection layer 61 and patterning.

[0121] A photoresist base layer containing palladium metal nanoparticle catalyst is coated on the substrate 1 including the etching stop layer 5 , and a pattern driving layer is formed after ultraviolet light exposure and development, and the pattern of the pattern driving layer is consistent with the line pattern of the source / drain electrode 6 .

[0122] On the pattern driving layer, a layer of metal for blackening is chemically plated according to the source / drain electrode line pattern to form a first source / drain electrode protection layer 61. The metal of the first source / drain electrode protection layer 61 is palladium with a thickness of 50nm. The chemical plating is to immerse the substrate including the pattern driving layer in a chemical plating solution for 2 minutes. The chemical plating solution consists of: 1.5g / L palladium chloride, 6g / L ethylenediamine, 5g / L sodium hypophosphite, 10g / L disodium ethylenediaminetetraacetate, 150ml / L ammonia water, 0.7g / L polyethylene glycol, pH value is 6, temperature is 60°C.

[0123] P62: forming a patterned source / drain electrode metal layer 60, the material of the layer is copper or copper alloy, and the thickness is 500 nm.

[0124] Copper salt, complexing agent, pH adjusting agent, reducing agent and stabilizer are mixed to prepare copper plating solution; a substrate including the first source / drain electrode protection layer 61 is placed in the copper plating solution for chemical copper plating, the copper plating time is 0.5min, the copper plating solution temperature is 30°C, and metal copper is deposited on the first source / drain electrode protection layer 61 to form a source / drain electrode metal layer 60 and a source / drain electrode 6 circuit pattern including the first source / drain electrode protection layer 61 and the source / drain electrode metal layer 60. The copper salt is copper sulfate, the complexing agent is disodium ethylenediaminetetraacetate, the pH adjusting agent is sodium hydroxide, the reducing agent is formaldehyde, and the stabilizer is 2-2 bipyridine. The chemical reaction of this step is: Pd + Cu2+ → Cu+ Pd2+.

[0125] P63: A patterned second source / drain electrode protection layer (blackened layer) 63 is formed, the material of which is palladium and the thickness is 50 nm.

[0126] Take 0.5g / L palladium chloride, 10g / L sodium citrate, 8g / L sodium acetate, 10ml / L formic acid, and 0.3g / L sodium dodecyl sulfonate to prepare a blackening solution. The substrate 1 including the source / drain electrode 6 circuit pattern including the first source / drain electrode protection layer 61 and the source / drain electrode metal layer 60 is immersed in the blackening solution for reaction. The reaction conditions are pH 5, time 2min, temperature 50°C, and chemically deposit a second source / drain electrode protection layer (blackening layer) 63 on the source / drain electrode metal layer 60 with a thickness of 50nm. A palladium metal layer is formed to protect the surface of the source / drain electrode metal layer to obtain a complete source / drain electrode 6 pattern with the first and second protection layers. The chemical reaction of this step is: Cu + Pd2+ → Cu2+ + Pd.

[0127] Preferably, in order to further enhance the performance of the second source / drain electrode protection layer (blackening layer) 63, a substrate including the first source / drain electrode protection layer 61, the source / drain electrode metal layer 60 and the second source / drain electrode protection layer (blackening layer) 63 is taken, immersed in a mixed solution of 70g / L nickel sulfate and 0.1g / L sodium dihydrogen hypophosphite, the pH value is adjusted to 4 with boric acid, heated to 45°C for 2 minutes, and a nickel metal protection layer is formed on the surface of the palladium metal layer as the second source / drain electrode protection layer (blackening layer) 63, and the total thickness of the two is 50nm. The chemical reaction of this step is: Ni2+ + H2PO2-+ H2O → H2PO3- + 2H+ + Ni.

[0128] Step P7: forming a pattern including a passivation layer 7 on the substrate 1 on which the source / drain electrodes 6 are formed.

[0129] P71: Deposit a passivation layer 7 thin film. The passivation layer material can be a thin film formed of silicon oxide, silicon nitride, or other inorganic insulating materials with the same or similar material properties as the above-mentioned materials. The optimization of the passivation layer can also be achieved by combining inorganic and organic insulating layer materials. Organic materials are usually resin-based materials or acrylic-based materials.

[0130] P72: Through the yellow light process and patterning process and making vias, the passivation layer 7 pattern is formed.

[0131] Step P8: forming a pattern including a pixel electrode 8 on the substrate 1 including the passivation layer 7 .

[0132] P81: Deposit pixel electrode 8 thin film. The pixel electrode layer usually uses transparent and conductive metal oxide or metal film materials such as ITO and IZO.

[0133] P82: A pixel electrode 8 pattern is formed by a yellow light process and a graphic process.

[0134] The present application proposes a method for preparing a thin film transistor. Compared with the method for preparing a thin film transistor in the previous embodiment, the method is different in step P21 of the gate 2 manufacturing process and step P61 of the source / drain electrode 6 manufacturing process, while the other steps are the same.

[0135] In P21 and P61 of this embodiment, the first gate protection layer 21 and the first source / drain protection layer are formed by the following method:

[0136] Formation and patterning of the first gate protection layer:

[0137] The processed substrate is placed in a vacuum chamber, and a palladium metal film layer with a thickness of 50 nm is sputtered and deposited thereon by physical vapor deposition (PVD) as the first gate protection layer 21 thin film.

[0138] The first gate protection layer 21 thin film on the substrate is patterned by yellow light and etching process to form the first gate protection layer 21 with a pattern consistent with the final gate line. The etching can be dry etching or wet etching.

[0139] Formation of the first source / drain electrode protection layer and patterning:

[0140] The substrate including the barrier layer 5 is placed in a vacuum chamber, and a palladium metal film layer with a thickness of 50 nm is sputtered thereon by physical vapor deposition (PVD) as a first source / drain electrode protection layer 61 thin film;

[0141] The first source / drain electrode protection layer 61 on the substrate is patterned by yellow light and etching process to form the first source / drain electrode protection layer 61 with a pattern consistent with the final source / drain electrode line. The etching can be dry etching or wet etching;

[0142] In this embodiment, the deposition process includes chemical vapor deposition (CVD) and / or physical sputtering deposition (PVD). Usually, the metal or metal oxide film layer is deposited by the PVD process, and the inorganic film layer is deposited by the CVD process. The graphical or patterned composition process usually includes cleaning, film formation, coating, exposure, development, dry or wet etching, photoresist stripping and other processes. In the embodiment of the present application, the method for manufacturing the gate 2 and the source / drain electrode first forms a first gate protection layer 21 or a first source / drain electrode protection layer 61 by chemical plating or sputtering film formation. At the same time, this first protection layer also serves as a catalyst for the copper metal layer in the gate 2 and the source / drain electrode 6, and the copper metal layer is chemically plated without complicated vacuum deposition of the copper metal layer, thereby reducing the production cost of the copper metal layer. After the copper metal layer is formed, a blackening process is added by chemical plating to form a second protective layer for the gate metal layer 20 and the source / drain electrode metal layer 60, which protects the gate metal layer 20 and the source / drain electrode metal layer 60 exposed to the outside, and can prevent copper or copper alloy from contacting with external water and oxygen or the migration of copper ions, thereby reducing the oxidation corrosion of copper or copper alloy. At the same time, the first and second protective layers contain palladium metal, which reduces the reflection of the gate 2 and the source / drain electrode 6 circuits, and improves the reliability and contrast of the product.

[0143] In one embodiment, the thin film transistor is a bottom-gate thin film transistor or a top-gate thin film transistor.

[0144] In one embodiment, the material of the active layer is metal oxide semiconductor, crystalline silicon or amorphous silicon.

[0145] Figure 5 Schematic diagram of the structure of an array substrate including a thin film transistor of the present application. The array substrate provided by the present application includes a plurality of thin film transistors arranged in an array. Figure 5 The thin film transistor in the array substrate is a bottom-gate type. The present application is also applicable to a top-gate thin film transistor. The thin film transistor of the present application includes a gate electrode 2, an active layer 4 and a source / drain electrode 6, a gate insulating layer 3 located between the gate electrode 2 and the active layer 4, an etching barrier layer 5 located on the active layer, a passivation layer 7 located on the etching barrier layer 5, the source / drain electrode 6 and the gate insulating layer 3, and a pixel electrode 8 located on the passivation layer 7 and connected to the source / drain.

[0146] like Figure 2-3As shown, the gate electrode 2 of the existing thin film transistor includes a gate electrode metal layer 20, a first gate protection layer 21 and a second gate electrode protection layer 22, wherein the gate electrode metal layer 20 is copper or a copper alloy. The first gate protection layer 21 and the second gate electrode protection layer 22 protect the gate electrode metal layer 20 to prevent it from oxidative corrosion or contact with the active layer causing copper ions to migrate to the active layer. The source / drain electrode 6 includes a source / drain electrode metal layer 60, a first source / drain protection layer 61 and a second source / drain protection layer 62, wherein the source / drain electrode metal layer 60 is copper or a copper alloy. The first source / drain protection layer 61 and the second source / drain protection layer 62 protect the source / drain electrode metal layer 60 to prevent it from oxidative corrosion or contact with the active layer causing copper ions to migrate to the active layer.

[0147] Its production method is as follows Figure 4 As shown, the process is performed in sequence: P1 substrate (substrate) 1 processing, P2 gate electrode 2 manufacturing, P3 gate insulation layer 3 manufacturing, P4 active layer 4 manufacturing, P5 etching barrier layer 5 manufacturing, P6 source / drain 6 manufacturing, P7 passivation layer 7 manufacturing, and P8 pixel electrode 8 manufacturing. The manufacturing of P2 gate electrode 2 and P6 source / drain 6 also includes the deposition and patterning of first protective layer 21, 61, gate metal layer 20, source / drain metal layer 60 and second protective layer 22, 62.

[0148] Although the first and second protective layers protect the upper and lower surfaces of the gate electrode 2 and the source / drain electrode 6, their cross sections are still exposed. In the subsequent manufacturing process and use, it is still easy to cause copper oxidation corrosion or copper ion migration on the cross-sectional surface, resulting in instability of the thin film transistor, thereby causing poor reliability of the array substrate or the display device using this array substrate. At the same time, the existing protective layer metal reflectivity is high, causing the display device to be uncontrollable in real light, resulting in poor display contrast. In the existing manufacturing process of the gate metal layer 20 and the source / drain electrode metal layer 60, vacuum deposition is used and then the pattern is formed by photolithography. The process flow is long and requires a lot of vacuum equipment, resulting in high cost.

[0149] like Figure 5-7 The present application also proposes a thin film transistor, which includes a gate electrode 2, an active layer 4 and a source / drain electrode 6 made on a substrate 1, a gate insulating layer 3 located between the gate electrode and the active layer, an etching stop layer 5 located on the active layer 4, a passivation layer 7 located on the etching stop layer 5, the source / drain electrode and the gate insulating layer 3, and a pixel electrode layer located on the passivation layer 7 and connected to the source / drain electrode.

[0150] In one embodiment, the gate electrode 2 includes a gate electrode metal layer 20, a first gate protection layer 21 and a second gate protection layer (blackening layer) 23. The first protection layer 21 is made of palladium metal with a thickness of 10~100nm, preferably 20~50nm, and is located between the gate electrode metal layer 20 and the substrate 3 to isolate the gate electrode metal layer 20 from the substrate 1; the gate electrode metal layer 20 is made of copper or copper alloy with a thickness of 100~800nm, preferably 300~600nm; the second gate protection layer (blackening layer) 23 is made of palladium metal with a thickness of 10~100nm, preferably 30~80nm, and is deposited on the surface of the gate metal layer 20 that is away from the first gate protection layer 21 to protect the gate metal layer 20 to prevent oxidation corrosion or copper ion migration.

[0151] Preferably, the second gate protection layer (blackening layer) 23 is made of palladium and nickel metals, and is deposited in sequence on the surface of the gate metal layer 20 that is away from the first gate protection layer 21 to protect the gate metal layer 20 from oxidation corrosion or copper ion migration. The total thickness is 10~100nm, preferably 30~80nm.

[0152] In one embodiment, the source / drain electrode 6 includes a source / drain electrode metal layer 60, a first source / drain electrode protection layer 61 and a second source / drain electrode protection layer (blackening layer) 63. The first source / drain electrode protection layer 61 is made of palladium metal with a thickness of 10-100 nm, preferably 20-50 nm, and is located between the source / drain electrode metal layer 60 and the active layer 4 to isolate the source / drain electrode metal layer 60 from the active layer 4 to prevent copper ions from migrating to the active layer; the source / drain electrode metal layer 60 is made of copper or copper alloy with a thickness of 100-800 nm, preferably 300-600 nm; the second source / drain electrode protection layer (blackening layer) 63 is made of palladium metal with a thickness of 10-100 nm, preferably 30-80 nm, and is deposited on the surface of the source / drain electrode metal layer 60 that is away from the first source / drain electrode protection layer 61 to protect the source / drain electrode metal layer 60 to prevent oxidation corrosion or copper ion migration.

[0153] Preferably, the second source / drain electrode protection layer (blackening layer) 63 is made of palladium and nickel metals, and is sequentially deposited on the surface of the source / drain electrode metal layer 60 that is away from the first source / drain electrode protection layer 61 to protect the source / drain electrode metal layer 60 to prevent oxidation corrosion or copper ion migration, and the total thickness is 10~100nm, preferably 30~80nm.

[0154] The present application also proposes an array substrate, including the above-mentioned thin film transistor; the specific structure of the thin film transistor refers to the above-mentioned embodiment. Since the array substrate adopts all the technical solutions of all the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here one by one.

[0155] The present application also provides a display device, comprising the above-mentioned array substrate.

[0156] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for preparing a thin film transistor, characterized in that: The method for preparing the thin film transistor comprises the following steps: A pattern including a gate electrode is formed on a base substrate, wherein the gate electrode includes a first gate protection layer, a gate electrode metal layer and a second gate protection layer (blackening layer) formed sequentially on the base substrate; wherein the gate electrode metal layer is made of copper or a copper alloy; forming a pattern including a gate insulating layer covering the gate electrode and the base substrate on the substrate on which the gate electrode is formed; Forming a pattern including an active layer located above the gate electrode and a pattern including an etching stopper layer located above the active layer on the substrate on which the gate insulating layer is formed; Forming a pattern including a source / drain electrode on the substrate on which the etching stop layer is formed, wherein the source / drain electrode includes a first source / drain protection layer, a source / drain electrode metal layer, and a second source / drain protection layer (blackening layer) sequentially formed on the base substrate, wherein the source / drain electrode metal layer is made of copper or a copper alloy; forming a pattern including a passivation layer on the substrate on which the source / drain electrode pattern is formed; A pattern including a pixel electrode is formed on the substrate on which the passivation layer pattern is formed.

2. The method for preparing a thin film transistor according to claim 1, characterized in that: The forming of the gate electrode pattern comprises the following steps: Forming a first gate protection layer and patterning: coating a photoresist base layer with a palladium metal nanoparticle catalyst on a substrate, and forming a pattern driving layer after ultraviolet exposure and development, wherein the pattern of the pattern driving layer is consistent with the gate line pattern; chemically plating a layer of metal for blackening on the pattern driving layer according to the gate line pattern to form a first gate protection layer, wherein the first gate protection layer is palladium metal with a thickness of 20 to 100 nm, preferably 30 to 60 nm; Forming a patterned gate electrode metal layer: performing chemical copper plating to deposit metal copper on the first gate protection layer with a thickness of 200-800 nm, preferably 400-600 nm, to form a gate metal layer and a gate line pattern including the first gate protection layer and the gate metal layer; Forming a patterned second gate protection layer (blackening layer): plating the second gate protection layer (blackening layer) metal to form a blackening layer to protect the surface of the gate metal layer; the second gate protection layer (blackening layer) is metal palladium with a thickness of 20~100nm, preferably 30~60nm.

3. The method for preparing a thin film transistor according to claim 1, characterized in that: The forming of the source / drain electrode pattern comprises the following steps: Forming a first source / drain electrode protection layer and patterning: coating a photoresist base layer having a palladium metal nanoparticle catalyst on a substrate including an etching stop layer, and forming a pattern driving layer through ultraviolet light exposure and development, wherein the pattern of the pattern driving layer is consistent with the source / drain electrode circuit pattern; chemically plating a layer of metal for blackening on the pattern driving layer according to the source / drain electrode circuit pattern to form a first source / drain electrode protection layer, wherein the first source / drain electrode protection layer is palladium metal with a thickness of 20 to 100 nm, preferably 30 to 60 nm; Forming a patterned source / drain electrode metal layer: performing chemical copper plating to deposit metal copper on the first source / drain electrode protection layer with a thickness of 200-800 nm, preferably 400-600 nm, to form a source / drain electrode metal layer and a source / drain electrode line pattern including the first source / drain electrode protection layer and the source / drain electrode metal layer; Forming a patterned second source / drain electrode protective layer (blackening layer): plating a second source / drain electrode protective layer (blackening layer) metal to form a blackening layer to protect the surface of the source / drain electrode metal layer; the second source / drain electrode protective layer (blackening layer) is metal palladium with a thickness of 20~100nm, preferably 30~60nm.

4. The method for preparing a thin film transistor according to claim 1, characterized in that: The method for preparing the thin film transistor further comprises the following steps: A pattern including a gate electrode is formed on a base substrate, wherein the gate electrode includes a first gate protection layer, a gate electrode metal layer and a second gate protection layer (blackening layer) formed sequentially on the base substrate; wherein the gate electrode metal layer is made of copper or a copper alloy; forming a pattern including a gate insulating layer covering the gate electrode and the base substrate on the substrate on which the gate electrode is formed; Forming a pattern including an active layer located above the gate electrode and a pattern including an etching stopper layer located above the active layer on the substrate on which the gate insulating layer is formed; Forming a pattern including a source / drain electrode on the substrate on which the etching stop layer is formed, wherein the source / drain electrode includes a first source / drain protection layer, a source / drain electrode metal layer, and a second source / drain protection layer (blackening layer) sequentially formed on the base substrate, wherein the source / drain electrode metal layer is made of copper or a copper alloy; forming a pattern including a passivation layer on the substrate on which the source / drain electrode pattern is formed; A pattern including a pixel electrode is formed on the substrate on which the passivation layer pattern is formed.

5. The method for preparing a thin film transistor according to claim 4, characterized in that: The forming of the gate electrode pattern comprises the following steps: Forming a first gate protection layer and patterning: taking the processed substrate in a vacuum chamber, sputtering and depositing a palladium metal film layer thereon by physical vapor deposition (PVD) with a thickness of 20 to 100 nm, preferably 30 to 60 nm, as a first gate protection layer film; patterning the first gate protection layer film on the substrate by yellow light and etching process to form a first gate protection layer with a pattern consistent with the final gate line; the etching can be dry etching or wet etching; Forming a patterned gate electrode metal layer: performing chemical copper plating to deposit metal copper on the first gate protection layer with a thickness of 200-800 nm, preferably 400-600 nm, to form a gate metal layer and a gate line pattern including the first gate protection layer and the gate metal layer; Forming a patterned second gate protection layer (blackening layer): plating the second gate protection layer (blackening layer) metal to form a blackening layer to protect the surface of the gate metal layer; the second gate protection layer (blackening layer) is metal palladium with a thickness of 20~100nm, preferably 30~60nm.

6. The method for preparing a thin film transistor according to claim 4, characterized in that: The forming of the source / drain electrode pattern comprises the following steps: Forming a first source / drain electrode protection layer and patterning: taking a substrate including an etching stop layer in a vacuum chamber, sputtering and depositing a palladium metal film layer thereon by physical vapor deposition (PVD) with a thickness of 20 to 100 nm, preferably 30 to 60 nm, as a first gate protection layer film; patterning the first gate protection layer film on the substrate by yellow light and etching process to form a first gate protection layer with a pattern consistent with the final gate line; the etching can be dry etching or wet etching; Forming a patterned source / drain electrode metal layer: performing chemical copper plating to deposit metal copper on the first source / drain electrode protection layer with a thickness of 200-800 nm, preferably 400-600 nm, to form a source / drain electrode metal layer and a source / drain electrode line pattern including the first source / drain electrode protection layer and the source / drain electrode metal layer; Forming a patterned second source / drain electrode protection layer (blackening layer): plating a second source / drain electrode protection layer (blackening layer) metal to form a blackening layer to protect the surface of the source / drain electrode metal layer; the second source / drain electrode protection layer (blackening layer) is metal palladium with a thickness of 20~100nm, preferably 30~60nm.

7. A thin film transistor, characterized in that: The thin film transistor comprises a gate electrode, an active layer and a source / drain electrode formed on a substrate, and a gate insulating layer located between the gate electrode and the active layer; The gate electrode comprises a gate electrode metal layer and a first gate protection layer, wherein the first protection layer is located between the gate electrode metal layer and the substrate to isolate the substrate from the gate electrode metal layer; The material of the first gate protection layer is metal palladium; The gate electrode metal layer is made of copper or copper alloy; The gate electrode further includes a second gate protection layer (blackened layer) located on the surface of the gate electrode metal layer away from the first protection layer and on both sides of the cross section of the gate electrode metal layer; The material of the second gate protection layer (blackened layer) is metal palladium; The thin film transistor is obtained by the method for preparing the thin film transistor according to any one of claims 1 to 6.

8. The thin film transistor according to claim 7, characterized in that: The source / drain electrode comprises a source / drain electrode metal layer and a first source / drain protection layer, wherein the first source / drain protection layer is located between the source / drain electrode metal layer and the active layer to isolate the source / drain electrode metal layer from the active layer; The material of the first source / drain electrode protection layer is metal palladium; The material of the source / drain electrode metal layer is copper or copper alloy; The source / drain electrode further includes a second source / drain electrode protection layer (blackened layer), which is located on the surface of the source / drain electrode metal layer away from the first protection layer and on both sides of the cross section of the source / drain electrode metal layer; The material of the second source / drain electrode protection layer (blackened layer) is metal palladium.

9. An array substrate, characterized in that: The array substrate comprises the thin film transistor as described in any one of claims 7 to 8.

10. A display device, characterized in that: The display device comprises the array substrate as claimed in claim 9.

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