Groove type power device
By changing the shape of the gate bus trench in the trench-type power device, optimizing the electric field distribution, and transferring the avalanche breakdown point from the terminal area to the cellular area, the problem of low voltage resistance of traditional devices is solved and the UIS capability and reliability of the device is improved.
Patent Information
- Application Number
- CN202411992226.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-04-22
AI Technical Summary
The avalanche breakdown point of traditional trench power devices appears near the terminal area, resulting in the device's voltage resistance is not high.
By changing the shape of the gate bus trench, the electric field in the terminal area is optimized, so that the avalanche breakdown point is transferred to the inside of the cell area. The specific implementation method is to adjust the width and depth of the groove to form a specific arc and groove shape.
By transferring the avalanche breakdown point to the cell region, the UIS capability of the power device is improved, damage caused by thermal breakdown is reduced, and the reliability of the device is enhanced.
Smart Images
Figure CN119866052A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of power devices, and in particular to a trench power device. Background Art
[0002] Power devices, also known as power electronic devices or power semiconductor devices, are vital components in electronic devices. They have the ability to handle high voltage and high current and are the core of power conversion and circuit control.
[0003] In the conventional trench power device, the gate bus trench is generally in the shape of a strip. In this structure, the avalanche breakdown point of the device appears near the terminal region, which is not conducive to improving the voltage withstand capability of the device. Summary of the invention
[0004] The purpose of the present application is to provide a trench power device, which can change the gate bus trench shape, optimize the terminal area electric field, and transfer the avalanche breakdown point to the inside of the cell area, thereby enhancing the UIS capability of the power device.
[0005] The embodiment of the present application provides a trench power device, including a substrate, the substrate having a first surface and a second surface, an interlayer dielectric being provided on the first surface; the substrate including a terminal region and a cell region, a gate metal being provided on the interlayer dielectric of the terminal region, and a source metal being provided on the interlayer dielectric of the cell region; a cell region trench being provided on the first surface of the cell region, a terminal trench being provided on the first surface of the terminal region, a gate bus trench being provided between the terminal trench and the cell region trench, polysilicon being provided in the terminal trench, the cell region trench and the gate bus trench respectively, the polysilicon in the gate bus trench being led out through the interlayer dielectric to be connected to the gate metal, and being led out on the first surface of the cell region to be connected to the source metal through the interlayer dielectric;
[0006] The longitudinal cross-sectional area in the middle of the gate bus groove is larger than the longitudinal cross-sectional areas at both ends of the gate bus groove.
[0007] Preferably, the middle width of the gate bus groove is larger than the widths of both ends of the gate bus groove.
[0008] Preferably, the middle groove depth of the gate bus groove is greater than the groove depths at both ends of the gate bus groove.
[0009] Preferably, the middle groove width of the gate bus groove is a preset width, the maximum groove depth is a preset depth, the groove width at the narrowest point at both ends is a preset multiple of the middle groove width, and the arc of the longitudinal section at both ends is a preset angle.
[0010] Preferably, one end of the gate bus trench is disposed below the gate metal, and the other end of the gate bus trench is disposed below the source metal.
[0011] Preferably, a first contact hole is provided in the interlayer dielectric between the gate metal and the gate bus trench, and the polysilicon in the gate bus trench is connected to the gate metal through the first contact hole.
[0012] Preferably, a first impurity layer is provided between the interlayer dielectric of the cell region and the first surface, the first impurity layer is led out, penetrates the interlayer dielectric, and is connected to the source metal, and the first impurity layer is adjacent to the gate bus groove.
[0013] Preferably, a source contact layer is provided between the interlayer dielectric of the cell region and the first impurity layer, the first impurity layer is led out, passes through the source contact layer and the interlayer dielectric, is connected to the source metal, and the source contact layer is adjacent to the gate bus groove.
[0014] Preferably, a second contact hole is provided between the first impurity layer and the source metal, the second contact hole penetrates the source contact layer and the interlayer dielectric, the first impurity layer is connected to the source metal through the second contact hole, the source metal is grounded, and the cell region trench is provided between adjacent second contact holes.
[0015] Preferably, the substrate includes a body region, an epitaxial layer, a substrate and a substrate contact layer, the epitaxial layer is arranged between the body region and the substrate contact layer, the substrate is arranged between the epitaxial layer and the substrate contact layer, the surface of the body region in contact with the interlayer dielectric is the first surface, and the surface of the substrate contact layer facing away from the substrate is the second surface; the bottom of the terminal groove, the bottom of the gate bus groove and the bottom of the cell region groove are respectively connected to the epitaxial layer.
[0016] The beneficial effects of the present application are as follows: the present application provides a trench-type power device, wherein the longitudinal cross-sectional area in the middle of the gate bus trench is larger than the longitudinal cross-sectional area at both ends of the gate bus trench, and in the case of an external reverse bias voltage, the migration of the high electric field region is achieved by changing the shape of the gate bus trench, so that the avalanche breakdown point of the trench-type power device is migrated from the terminal region to the inside of the cell region, and the power device is mainly thermally damaged by avalanche breakdown when a UIS (unclamped inductive load switch) state occurs. When the avalanche breakdown point is transferred to the cell region, due to the large area of the cell region, when the avalanche breakdown point is transferred to the cell region, the temperature dissipates faster, and the device is less likely to be damaged by thermal breakdown, thereby effectively improving the UIS capability of the power device and enhancing the reliability of the power device;
[0017] The present invention has a simple structure and can be realized under the traditional trench power device manufacturing process, without introducing additional processes and injection conditions and without increasing additional costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0019] Figure 1 A top view of a trench power device in an embodiment of the present application;
[0020] Figure 2 A cross-sectional view of a trench-type power device along the AA' plane in an embodiment of the present application;
[0021] Figure 3 Avalanche breakdown cross-section diagram of a conventional trench power device along the AA' plane;
[0022] Figure 4 This is a cross-sectional view of an avalanche breakdown of a trench power device along the AA' plane in an embodiment of the present application.
[0023] Figure numerals: 1-cell region, 2-terminal region, 3-cell region trench, 4-terminal region trench, 5-first contact hole, 6-second contact hole, 7-gate metal, 8-source metal, 9-gate bus trench, 10-P-type body region, 11-first impurity layer, 12-source contact N+ layer, 13-interlayer dielectric, 14-polysilicon, 15-N-type epitaxial layer, 16-N-type substrate, 17-substrate contact layer, 18-first surface, 19-second surface. DETAILED DESCRIPTION
[0024] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, in the description of the present application, the term "including" means "including but not limited to". The terms first, second, third, etc. are used only as labels, and no numerical requirements are imposed or order is established. Various embodiments of the present application may exist in the form of a range; it should be understood that the description in the form of a range is only for convenience and simplicity, and should not be understood as a hard limit to the scope of the present application; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single values within the range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the numbered range, such as 1, 2, 3, 4, 5 and 6, which are applicable regardless of the range. Additionally, whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range.
[0025] In order to transfer the avalanche breakdown point of the trench power device to the inside of the cell region, thereby enhancing the UIS capability of the power device. The present application provides the following implementation methods:
[0026] In some embodiments, a trench-type power device includes a substrate, the substrate having a first surface and a second surface, an interlayer dielectric is disposed on the first surface; the substrate includes a terminal region and a cell region, a gate metal is disposed on the interlayer dielectric of the terminal region, and a source metal is disposed on the interlayer dielectric of the cell region; a cell region trench is disposed on the first surface of the cell region, a terminal trench is disposed on the first surface of the terminal region, a gate bus trench is disposed between the terminal trench and the cell region trench, polysilicon is disposed in the terminal trench, the cell region trench, and the gate bus trench respectively, the polysilicon in the gate bus trench is led out through the interlayer dielectric to be connected to the gate metal, and the first surface of the cell region is led out through the interlayer dielectric to be connected to the source metal;
[0027] The longitudinal cross-sectional area in the middle of the gate bus groove is larger than the longitudinal cross-sectional areas at both ends of the gate bus groove.
[0028] Preferably, the middle width of the gate bus groove is larger than the widths of both ends of the gate bus groove.
[0029] Preferably, the middle groove depth of the gate bus groove is greater than the groove depths at both ends of the gate bus groove.
[0030] Preferably, the middle groove width of the gate bus groove is a preset width, the maximum groove depth is a preset depth, the groove width at the narrowest point at both ends is a preset multiple of the middle groove width, and the arc of the longitudinal section at both ends is a preset angle.
[0031] Preferably, one end of the gate bus trench is disposed below the gate metal, and the other end of the gate bus trench is disposed below the source metal.
[0032] Preferably, a first contact hole is provided in the interlayer dielectric between the gate metal and the gate bus trench, and the polysilicon in the gate bus trench is connected to the gate metal through the first contact hole.
[0033] Preferably, a first impurity layer is provided between the interlayer dielectric of the cell region and the first surface, the first impurity layer is led out, penetrates the interlayer dielectric, and is connected to the source metal, and the first impurity layer is adjacent to the gate bus groove.
[0034] Preferably, a source contact layer is provided between the interlayer dielectric of the cell region and the first impurity layer, the first impurity layer is led out, passes through the source contact layer and the interlayer dielectric, is connected to the source metal, and the source contact layer is adjacent to the gate bus groove.
[0035] Preferably, a second contact hole is provided between the first impurity layer and the source metal, the second contact hole penetrates the source contact layer and the interlayer dielectric, the first impurity layer is connected to the source metal through the second contact hole, the source metal is grounded, and the cell region trench is provided between adjacent second contact holes.
[0036] Preferably, the substrate includes a body region, an epitaxial layer, a substrate and a substrate contact layer, the epitaxial layer is arranged between the body region and the substrate contact layer, the substrate is arranged between the epitaxial layer and the substrate contact layer, the body region is the first surface, and the substrate contact layer is the second surface; the bottom of the terminal groove, the bottom of the gate bus groove and the bottom of the cell region groove are respectively connected to the epitaxial layer.
[0037] In the above embodiment, the first impurity layer and the body region have a first type of majority carriers, and the majority carriers of the first impurity layer have a first concentration. The majority carriers of the first concentration can form an ohmic contact with the conductor connected thereto when the power device is working.
[0038] The source contact layer, the epitaxial layer, the substrate, and the substrate contact layer have the second type of majority carriers. The second type of majority carrier concentrations of the source contact layer and the substrate contact layer can form ohmic contact with the conductor connected thereto when the power device is working.
[0039] Illustratively, the majority carriers of the first type are holes, and the majority carriers of the second type are electrons.
[0040] The settings of the preset width, preset depth, preset multiple and preset angle can make the avalanche breakdown point of the trench power device UIS appear within the cell area.
[0041] Preferably, the preset width is 0.25-0.28 μm.
[0042] Preferably, the preset depth is 1.4 μm.
[0043] Preferably, the preset multiple is 0.5.
[0044] The default angle is 26°.
[0045] The technical solution of the present invention is described below by taking N-channel MOSFET as an example.
[0046] Embodiment 1
[0047] like Figures 1 to 4 As shown, an embodiment of the present application provides a trench power device, including a substrate, which includes a P-type body region 10, an N-type epitaxial layer 15, an N-type substrate 16 and a substrate contact layer 17 in sequence, wherein the substrate contact layer 17 is a highly doped N+ layer, the N-type epitaxial layer 15 is respectively connected to the P-type body region 10 and the N-type substrate 16, and the N-type substrate 16 is respectively connected to the N-type epitaxial layer 15 and the substrate contact layer 17, and the substrate is provided with a first surface 18 and a second surface 19, wherein the P-type body region 10 is the first surface 18, the substrate contact layer 17 is the second surface 19, and an interlayer dielectric 13 is provided on the first surface 18.
[0048] The substrate includes a terminal region 20 and a cell region 21. A gate metal 7 is provided on the interlayer dielectric 13 of the terminal region 20. A source metal 8 is provided on the interlayer dielectric 13 of the cell region 21. A source contact N+ layer 12 is provided between the interlayer dielectric 13 of the cell region 21 and the P-type body region 10. A first impurity layer 11 is provided between the source contact N+ layer 12 and the P-type body region 10. The first impurity layer 11 is a highly doped P+ layer. The source contact N+ layer 12 and the first impurity layer 11 are respectively pressed into the first surface 18.
[0049] A cell region groove 3 is provided on the first surface 18 of the cell region 21, a terminal groove 4 is provided on the first surface 18 of the terminal region 20, a gate bus groove 9 is provided between the terminal groove 4 and the cell region groove 3, one end of the gate bus groove 9 is provided below the gate metal 7, and the other end of the gate bus groove 9 is provided below the source metal 8, the bottom of the terminal groove 4, the bottom of the gate bus groove 9 and the bottom of the cell region groove 3 are respectively connected to the N-type epitaxial layer 15, and the first impurity layer 11 and the source contact N+ layer 12 are respectively adjacent to the gate bus groove 9.
[0050] Polysilicon 14 is respectively provided in the terminal groove 4, the cell area groove 3 and the gate bus groove 9, and a first contact hole 5 is opened in the interlayer dielectric 13 between the gate metal 7 and the gate bus groove 9, and the polysilicon 14 in the gate bus groove 9 is connected to the gate metal 7 through the first contact hole 5; a second contact hole 6 is provided between the first impurity layer 11 and the source metal 8, and the second contact hole 6 penetrates the source contact N+ layer 9 and the interlayer dielectric 13, and the first impurity layer 11 is connected to the source metal 8 through the second contact hole 6, and the source metal 8 is grounded, and the cell area groove 3 is arranged between adjacent second contact holes 6.
[0051] The middle width of the gate bus groove is 0.25μm, the maximum groove depth is 1.4μm, the narrowest groove width at both ends is 0.5 times the middle groove width, and the arc of the longitudinal section at both ends is 26°.
[0052] Embodiment 2
[0053] like Figures 1 to 4 As shown, an embodiment of the present application provides a trench power device, including a substrate, which includes a P-type body region 10, an N-type epitaxial layer 15, an N-type substrate 16 and a substrate contact layer 17 in sequence, wherein the substrate contact layer 17 is a highly doped N+ layer, the N-type epitaxial layer 15 is respectively connected to the P-type body region 10 and the N-type substrate 16, and the N-type substrate 16 is respectively connected to the N-type epitaxial layer 15 and the substrate contact layer 17, and the substrate is provided with a first surface 18 and a second surface 19, wherein the P-type body region 10 is the first surface 18, the substrate contact layer 17 is the second surface 19, and an interlayer dielectric 13 is provided on the first surface 18.
[0054] The substrate includes a terminal region 20 and a cell region 21. A gate metal 7 is provided on the interlayer dielectric 13 of the terminal region 20. A source metal 8 is provided on the interlayer dielectric 13 of the cell region 21. A source contact N+ layer 12 is provided between the interlayer dielectric 13 of the cell region 21 and the P-type body region 10. A first impurity layer 11 is provided between the source contact N+ layer 12 and the P-type body region 10. The first impurity layer 11 is a highly doped P+ layer. The source contact N+ layer 12 and the first impurity layer 11 are respectively pressed into the first surface 18.
[0055] A cell region groove 3 is provided on the first surface 18 of the cell region 21, a terminal groove 4 is provided on the first surface 18 of the terminal region 20, a gate bus groove 9 is provided between the terminal groove 4 and the cell region groove 3, one end of the gate bus groove 9 is provided below the gate metal 7, and the other end of the gate bus groove 9 is provided below the source metal 8, the bottom of the terminal groove 4, the bottom of the gate bus groove 9 and the bottom of the cell region groove 3 are respectively connected to the N-type epitaxial layer 15, and the first impurity layer 11 and the source contact N+ layer 12 are respectively adjacent to the gate bus groove 9.
[0056] Polysilicon 14 is respectively provided in the terminal groove 4, the cell area groove 3 and the gate bus groove 9, and a first contact hole 5 is opened in the interlayer dielectric 13 between the gate metal 7 and the gate bus groove 9, and the polysilicon 14 in the gate bus groove 9 is connected to the gate metal 7 through the first contact hole 5; a second contact hole 6 is provided between the first impurity layer 11 and the source metal 8, and the second contact hole 6 penetrates the source contact N+ layer 9 and the interlayer dielectric 13, and the first impurity layer 11 is connected to the source metal 8 through the second contact hole 6, and the source metal 8 is grounded, and the cell area groove 3 is arranged between adjacent second contact holes 6.
[0057] The middle width of the gate bus groove is 0.26μm, the maximum groove depth is 1.4μm, the narrowest groove width at both ends is 0.5 times the middle groove width, and the curvature of the longitudinal section at both ends is 26°.
[0058] Embodiment 3
[0059] like Figures 1 to 4 As shown, an embodiment of the present application provides a trench power device, including a substrate, which includes a P-type body region 10, an N-type epitaxial layer 15, an N-type substrate 16 and a substrate contact layer 17 in sequence, wherein the substrate contact layer 17 is a highly doped N+ layer, the N-type epitaxial layer 15 is respectively connected to the P-type body region 10 and the N-type substrate 16, and the N-type substrate 16 is respectively connected to the N-type epitaxial layer 15 and the substrate contact layer 17, and the substrate is provided with a first surface 18 and a second surface 19, wherein the P-type body region 10 is the first surface 18, the substrate contact layer 17 is the second surface 19, and an interlayer dielectric 13 is provided on the first surface 18.
[0060] The substrate includes a terminal region 20 and a cell region 21. A gate metal 7 is provided on the interlayer dielectric 13 of the terminal region 20. A source metal 8 is provided on the interlayer dielectric 13 of the cell region 21. A source contact N+ layer 12 is provided between the interlayer dielectric 13 of the cell region 21 and the P-type body region 10. A first impurity layer 11 is provided between the source contact N+ layer 12 and the P-type body region 10. The first impurity layer 11 is a highly doped P+ layer. The source contact N+ layer 12 and the first impurity layer 11 are respectively pressed into the first surface 18.
[0061] A cell region groove 3 is provided on the first surface 18 of the cell region 21, a terminal groove 4 is provided on the first surface 18 of the terminal region 20, a gate bus groove 9 is provided between the terminal groove 4 and the cell region groove 3, one end of the gate bus groove 9 is provided below the gate metal 7, and the other end of the gate bus groove 9 is provided below the source metal 8, the bottom of the terminal groove 4, the bottom of the gate bus groove 9 and the bottom of the cell region groove 3 are respectively connected to the N-type epitaxial layer 15, and the first impurity layer 11 and the source contact N+ layer 12 are respectively adjacent to the gate bus groove 9.
[0062] Polysilicon 14 is respectively provided in the terminal groove 4, the cell area groove 3 and the gate bus groove 9, and a first contact hole 5 is opened in the interlayer dielectric 13 between the gate metal 7 and the gate bus groove 9, and the polysilicon 14 in the gate bus groove 9 is connected to the gate metal 7 through the first contact hole 5; a second contact hole 6 is provided between the first impurity layer 11 and the source metal 8, and the second contact hole 6 penetrates the source contact N+ layer 9 and the interlayer dielectric 13, and the first impurity layer 11 is connected to the source metal 8 through the second contact hole 6, and the source metal 8 is grounded, and the cell area groove 3 is arranged between adjacent second contact holes 6.
[0063] The middle width of the gate bus groove is 0.27μm, the maximum groove depth is 1.4μm, the narrowest groove width at both ends is 0.5 times the middle groove width, and the arc of the longitudinal section at both ends is 26°.
[0064] Embodiment 4
[0065] like Figures 1 to 4 As shown, an embodiment of the present application provides a trench power device, including a substrate, which includes a P-type body region 10, an N-type epitaxial layer 15, an N-type substrate 16 and a substrate contact layer 17 in sequence, wherein the substrate contact layer 17 is a highly doped N+ layer, the N-type epitaxial layer 15 is respectively connected to the P-type body region 10 and the N-type substrate 16, and the N-type substrate 16 is respectively connected to the N-type epitaxial layer 15 and the substrate contact layer 17, and the substrate is provided with a first surface 18 and a second surface 19, wherein the P-type body region 10 is the first surface 18, the substrate contact layer 17 is the second surface 19, and an interlayer dielectric 13 is provided on the first surface 18.
[0066] The substrate includes a terminal region 20 and a cell region 21. A gate metal 7 is provided on the interlayer dielectric 13 of the terminal region 20. A source metal 8 is provided on the interlayer dielectric 13 of the cell region 21. A source contact N+ layer 12 is provided between the interlayer dielectric 13 of the cell region 21 and the P-type body region 10. A first impurity layer 11 is provided between the source contact N+ layer 12 and the P-type body region 10. The first impurity layer 11 is a highly doped P+ layer. The source contact N+ layer 12 and the first impurity layer 11 are respectively pressed into the first surface 18.
[0067] A cell region groove 3 is provided on the first surface 18 of the cell region 21, a terminal groove 4 is provided on the first surface 18 of the terminal region 20, a gate bus groove 9 is provided between the terminal groove 4 and the cell region groove 3, one end of the gate bus groove 9 is provided below the gate metal 7, and the other end of the gate bus groove 9 is provided below the source metal 8, the bottom of the terminal groove 4, the bottom of the gate bus groove 9 and the bottom of the cell region groove 3 are respectively connected to the N-type epitaxial layer 15, and the first impurity layer 11 and the source contact N+ layer 12 are respectively adjacent to the gate bus groove 9.
[0068] Polysilicon 14 is respectively provided in the terminal groove 4, the cell area groove 3 and the gate bus groove 9, and a first contact hole 5 is opened in the interlayer dielectric 13 between the gate metal 7 and the gate bus groove 9, and the polysilicon 14 in the gate bus groove 9 is connected to the gate metal 7 through the first contact hole 5; a second contact hole 6 is provided between the first impurity layer 11 and the source metal 8, and the second contact hole 6 penetrates the source contact N+ layer 9 and the interlayer dielectric 13, and the first impurity layer 11 is connected to the source metal 8 through the second contact hole 6, and the source metal 8 is grounded, and the cell area groove 3 is arranged between adjacent second contact holes 6.
[0069] The middle width of the gate bus groove is 0.28μm, the maximum groove depth is 1.4μm, the narrowest groove width at both ends is 0.5 times the middle groove width, and the arc of the longitudinal section at both ends is 26°.
[0070] The above is a detailed introduction to a separation and purification system and method provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technicians in this field, according to the ideas of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. A trench power device, characterized in that: The invention comprises a substrate, wherein the substrate has a first surface and a second surface, an interlayer dielectric is arranged on the first surface; the substrate comprises a terminal region and a cell region, a gate metal is arranged on the interlayer dielectric of the terminal region, and a source metal is arranged on the interlayer dielectric of the cell region; a cell region groove is arranged on the first surface of the cell region, a terminal groove is arranged on the first surface of the terminal region, a gate bus groove is arranged between the terminal groove and the cell region groove, polysilicon is arranged in the terminal groove, the cell region groove and the gate bus groove respectively, the polysilicon in the gate bus groove is led out through the interlayer dielectric to be connected to the gate metal, and the first surface of the cell region is led out through the interlayer dielectric to be connected to the source metal; Wherein, the longitudinal cross-sectional area in the middle of the gate bus groove is larger than the longitudinal cross-sectional areas at both ends of the gate bus groove.
2. The trench power device according to claim 1, characterized in that: The middle groove width of the gate bus groove is larger than the groove widths at both ends of the gate bus groove.
3. The trench power device according to claim 1, characterized in that: The middle groove depth of the gate bus groove is greater than the groove depths at both ends of the gate bus groove.
4. The trench power device according to claim 1, characterized in that: The middle groove width of the gate bus groove is a preset width, the maximum groove depth is a preset depth, the groove width at the narrowest point at both ends is a preset multiple of the middle groove width, and the arc of the longitudinal section at both ends is a preset angle.
5. The trench power device according to claim 1, characterized in that: One end of the gate bus groove is arranged below the gate metal, and the other end of the gate bus groove is arranged below the source metal.
6. The trench power device according to claim 1, characterized in that: A first contact hole is provided in the interlayer dielectric between the gate metal and the gate bus groove, and the polysilicon in the gate bus groove is connected to the gate metal through the first contact hole.
7. The trench power device according to claim 1, characterized in that: A first impurity layer is provided between the interlayer dielectric of the cell region and the first surface. The first impurity layer is led out, penetrates the interlayer dielectric, and is connected to the source metal. The first impurity layer is adjacent to the gate bus groove.
8. The trench power device according to claim 7, characterized in that: A source contact layer is provided between the interlayer dielectric of the cell region and the first impurity layer. The first impurity layer is led out, passes through the source contact layer and the interlayer dielectric, and is connected to the source metal. The source contact layer is adjacent to the gate bus groove.
9. The trench power device according to claim 7, characterized in that: A second contact hole is provided between the first impurity layer and the source metal, the second contact hole penetrates the source contact layer and the interlayer dielectric, the first impurity layer is connected to the source metal through the second contact hole, the source metal is grounded, and the cell region trench is provided between adjacent second contact holes.
10. The trench power device according to claim 1, characterized in that: The substrate includes a body region, an epitaxial layer, a substrate and a substrate contact layer, the epitaxial layer is arranged between the body region and the substrate contact layer, the substrate is arranged between the epitaxial layer and the substrate contact layer, the surface of the body region in contact with the interlayer dielectric is the first surface, and the surface of the substrate contact layer facing away from the substrate is the second surface; the bottom of the terminal groove, the bottom of the gate bus groove and the bottom of the cell region groove are respectively connected to the epitaxial layer.