Circuit arrangement for monitoring battery cell
By designing a circuit device with a main monitoring channel and a redundant monitoring channel in the battery cell monitoring circuit, and comparing it with common reference voltage, the high-precision and economical battery voltage monitoring problem in the prior art is solved, and a high-precision and low-cost monitoring effect is achieved.
Patent Information
- Application Number
- CN202380059343.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-08-17
- Filing Date
- 2023-08-02
- Publication Date
- 2025-04-22
AI Technical Summary
The prior art is difficult to achieve high-precision and economical measurements when monitoring battery cell voltages, especially in the case of high safety requirements, resulting in partial redundancy of the measurement circuit and increasing costs.
A circuit device is designed including a main monitoring channel with a first analog-to-digital converter (ADC) and a redundant monitoring channel with a second ADC, and the two are compared by a comparison unit to determine the cell voltage and save space and cost through a common reference voltage.
It realizes high-precision and economical monitoring of battery cell voltage under high safety requirements, avoids the increase in cost caused by redundant measures, and further improves measurement accuracy by identifying common mode errors.
Smart Images
Figure CN119866445A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a circuit arrangement for monitoring a battery cell. The battery cell is arranged in a battery, in particular in a traction battery of an electric vehicle. The invention also relates to a battery system and a motor vehicle. Background Art
[0002] In the process of electrification of the drive train, the requirements for accuracy of battery monitoring are becoming increasingly higher in order to improve the range and operating safety of electric vehicles, such as hybrid electric vehicles (HEV), plug-in hybrid electric vehicles (PHEV) and full electric vehicles (BEV). An important aspect here is the measurement accuracy of the cell voltage monitoring. In the case of high automotive safety integrity levels (ASIL) of class C or D, it is required that the cell voltage is provided as a measured value with high accuracy even in the case of unrecognized faults. With higher measurement accuracy of the cell voltage, the traction battery can be operated almost up to the cell voltage limit without risk, thereby increasing the achievable range with the same battery capacity. In recent years, the performance of semiconductor components for performing battery monitoring has been significantly improved. However, due to the high safety requirements, the measuring circuits, such as analog-to-digital converters for converting the detected voltage sensor signals, must be implemented partially redundantly, which leads to high costs. Summary of the invention
[0003] The object of the present invention is to provide a circuit arrangement for monitoring a battery cell which allows a precise and economical determination of the cell voltage of a battery cell.
[0004] This object is achieved by the features of the independent claim. Advantageous developments of the invention are described in the dependent claims.
[0005] According to a first aspect, the above-mentioned task is solved by a circuit arrangement for monitoring a battery cell. The circuit arrangement has a main monitoring channel with a first analog-to-digital converter (ADC), a redundant monitoring channel with a second ADC and a comparison unit. The first ADC is configured to perform an analog-to-digital conversion on a provided signal to thereby obtain a first digital cell voltage signal, the provided signal representing the cell voltage of the battery cell. The second ADC is configured to perform an analog-to-digital conversion on a differential signal to thereby obtain a second digital level-shifted cell voltage signal, the differential signal representing the difference between a reference voltage used by the two ADCs for the analog-to-digital conversion and the signal. Alternatively, the second ADC is configured to perform an analog-to-digital conversion on the differential signal to thereby obtain a second digital level-shifted cell voltage signal, the differential signal representing the difference between a supply voltage of the second ADC and the signal.
[0006] The first ADC and the second ADC are configured to perform analog-to-digital conversion of the signal or the differential signal according to a reference voltage, wherein the reference voltage of the first ADC is equal to the reference voltage of the second ADC.
[0007] The comparison unit is configured to determine a comparison value based on the first digital cell voltage signal and the second digital level-shifted cell voltage signal according to a preset function. The comparison unit is further configured to provide the comparison value at an output of the comparison unit and / or compare the comparison value with a preset threshold value, and provide a fault signal at an output of the comparison unit if the comparison value exceeds the preset threshold value.
[0008] The fault signal and / or the comparison signal is supplied, for example, to an evaluation unit or a higher-level computing unit.
[0009] The comparison value of the first digital cell voltage signal and the second digital level-shifted cell voltage signal is preferably re-determined at preset time intervals.
[0010] The use of a common reference voltage by the first and second ADCs makes it possible to save space and costs when implementing the two ADCs. However, since the first and second ADCs have a common reference voltage, common-mode errors of the reference voltage have the same effect on the first ADC and the second ADC. The circuit arrangement makes it possible to identify such common-mode errors by means of a special comparison, and no further safety mechanisms are required. As a result, the measurement accuracy can be significantly improved.
[0011] In at least one advantageous embodiment of the first aspect, the circuit arrangement is designed as an integrated circuit. This allows a compact and economical implementation. Since the comparison of the output signals of the first ADC and the second ADC is carried out in the same integrated circuit, delay differences between the two measurement results can be avoided very simply, thereby achieving a significantly more accurate comparison and thus a significantly more reliable verification of the first ADC.
[0012] In at least one advantageous embodiment of the first aspect, the circuit arrangement has a reference voltage source which provides a reference voltage for the first ADC and the second ADC. The use of a common reference voltage source allows the circuit arrangement to be manufactured more economically and space-savingly.
[0013] In at least one advantageous design solution according to the first aspect, the first ADC and the second ADC each have a first input terminal for receiving a first measurement signal, which represents the potential of the positive electrode of the battery cell. In addition, the first ADC and the second ADC each have a second input terminal for receiving a second measurement signal, which represents the potential of the negative electrode of the battery cell.
[0014] The first ADC has a first level converter on the input side, which is designed to form a first cell potential difference between a first measurement signal, which represents a minuend, and a second measurement signal, which represents a subtrahend. The first cell potential difference thus corresponds to or is equal to the cell voltage of the battery cell.
[0015] The second ADC has a second level converter on the input side, the second level converter is configured to form a second cell potential difference between the second measurement signal and the first measurement signal, wherein the second measurement signal represents the minuend and the first measurement signal represents the subtrahend. The second level converter is also configured to provide a differential signal to the second ADC by adding the second cell potential difference to the reference voltage when the differential signal represents the difference between the reference voltage and the signal, and to provide a differential signal to the second ADC by adding the second cell potential difference to the supply voltage of the second ADC when the differential signal represents the difference between the supply voltage of the second ADC and the signal.
[0016] Preferably, the first ADC and the second ADC have the same supply voltage.
[0017] In at least one design solution according to the first aspect, when the differential signal is determined according to the reference voltage, the comparison function represents the sum of the first digital cell voltage signal and the second digital level-shifted cell voltage signal minus the reference voltage. When the differential signal is determined according to the supply voltage of the second ADC, the comparison function represents the sum of the first digital cell voltage signal and the second digital level-shifted cell voltage signal minus a target value of the supply voltage of the second ADC.
[0018] In at least one embodiment of the first aspect, the circuit arrangement comprises a first analog filter connected upstream of the first ADC and / or a second analog filter connected upstream of the second ADC. Preferably, the first filter and the second filter are part of an integrated circuit and / or the first filter and the second filter have different frequency responses.
[0019] Different frequency responses have the advantage that differences in frequency responses that may occur due to pre-processing can be at least partially compensated.
[0020] In at least one refinement of the first aspect, the first ADC and the second ADC differ in their resolution and / or their settling time.
[0021] According to a second aspect, the above-mentioned object is achieved by a battery system having a battery with at least one battery cell. Furthermore, the battery system has a circuit arrangement according to the first aspect for all or at least some of the battery cells.
[0022] According to a third aspect, the above-mentioned object is achieved by a motor vehicle having a battery system according to the second aspect.
[0023] The optional design solutions of the first aspect may also exist in other aspects accordingly and have corresponding effects. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The following is a detailed description of an embodiment of the present invention by means of schematic diagrams. In the drawings, the same reference numerals are used for elements having substantially the same function, but these elements are not necessarily identical in all details.
[0025] The description of the subject matter described herein is not limited to individual specific implementation forms. As long as it is technically reasonable, the features of different embodiments can be combined with each other to form other embodiments. For example, the variant or modification described for one of the embodiments may also be applicable to other embodiments, unless otherwise specified.
[0026] Figure 1 shows an exemplary block diagram of a circuit arrangement for monitoring a battery cell,
[0027] Figure 2 An exemplary equivalent circuit diagram of a first level converter is shown, and
[0028] Figure 3 An exemplary equivalent circuit diagram of a second level shifter is shown. DETAILED DESCRIPTION
[0029] It should be noted that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "coupled" to another element, there are no intervening elements. Other expressions used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).
[0030] The functions of the circuit arrangement for monitoring battery cells are combined in the following Figure 1 To explain, the Figure is a simplified diagram of a circuit according to the present invention, in which many essential components are omitted for the sake of clarity.
[0031] Figure 1 An exemplary block diagram of an embodiment of a circuit arrangement 10 for monitoring a battery cell of a battery is shown. Figure 1 The battery is preferably configured as a traction battery of a vehicle, for example.
[0032] The battery cells are connected to the circuit arrangement 10 , and the circuit arrangement receives a first cell potential signal Ucell_p and a second cell potential signal Ucell_c on the input side from the battery cells directly or indirectly via a preprocessing unit.
[0033] The circuit arrangement 10 has a main monitoring channel 20 with a first analog-to-digital converter (ADC) 24 and a redundant monitoring channel 30 with a second ADC 34. The circuit arrangement 10 also has a comparison unit 40.
[0034] The circuit arrangement 10 is preferably designed as an integrated circuit in a semiconductor chip. In particular, a semiconductor chip can have a plurality of such circuit arrangements 10 , so that a plurality of battery cells can be monitored with the semiconductor chip.
[0035] The main monitoring channel 20 has, for example, a first analog filter 22 on the input side. The first ADC 24 is connected downstream of the first filter 22. For example, the first analog filter 22 of the main monitoring channel 20 is directly or indirectly connected to the battery cell. The first analog filter 22 is used to perform signal processing on the cell potential signals Ucell_p and Ucell_n received from the battery cell.
[0036] A digital low-pass filter 26 is connected downstream of the first ADC 24, for example. For example, a filtered digital cell voltage signal UC representing the cell voltage of the connected battery cell is provided at the output of the digital low-pass filter 26 to an evaluation unit 50. The evaluation unit 50 can be a control unit associated with the circuit arrangement or a higher-level computing unit.
[0037] The redundant monitoring channel 30 of the circuit arrangement 10 has, for example, a second analog filter 32 on the input side. The second ADC 34 is connected downstream of the second filter 32. The second analog filter 32 of the redundant monitoring channel 30 is, for example, directly or indirectly connected to the battery cell. The second analog filter 32 is used to perform signal processing on the cell potential signals Ucell_p and Ucell_n received from the battery cell.
[0038] In an optional design scheme, a first discrete hardware filter 28 and a second discrete hardware filter 38 are connected upstream of the circuit device, wherein the first discrete hardware filter 28 is connected upstream of the first filter of the main monitoring path 20, and the second discrete hardware filter 38 is connected upstream of the second filter 32 of the redundant monitoring path.
[0039] The input of the first ADC 24 has a first input terminal for receiving a first measurement signal Uin_p representative of the potential at the positive pole of the battery cell and a second input terminal for receiving a second measurement signal Uin_n representative of the potential at the negative pole of the battery cell.
[0040] The first ADC 24 includes a first level converter 241 . Figure 2 An exemplary equivalent circuit diagram of the first level converter 241 of the first ADC 24 is shown.
[0041] The first level converter 241 is configured to form a first cell potential difference between the first measurement signal Uin_p and the second measurement signal Uin_n. The first cell potential difference may also be referred to as a cell voltage Ucell.
[0042] The first ADC 24 (see Figure 1 ) also has a converter unit, which is configured to perform an actual analog-to-digital conversion of the cell voltage Ucell and to provide a first digital cell voltage signal U_MAIN at an output of the converter unit.
[0043] The input of the second ADC 34 has a first input terminal for receiving a first measurement signal Uin_p representative of the potential at the positive pole of the battery cell, and a second input terminal for receiving a second measurement signal Uin_n representative of the potential at the negative pole of the battery cell.
[0044] The second ADC 34 includes a second level converter 341 . Figure 3 A simplified exemplary equivalent circuit diagram of the second level shifter 341 of the second ADC 34 is shown.
[0045] The second level converter 341 is configured to form a second cell potential difference between the second measurement signal Uin_n and the first measurement signal Uin_n, wherein the second measurement signal forms the minuend and the first measurement signal forms the subtrahend. The second level converter 341 is also configured to provide a differential signal Uin_n of the second ADC 34 by adding the supply voltage VCC of the second ADC to the second cell potential difference. diff .
[0046] Alternatively, the second level converter 341 is configured to provide a differential signal U of the second ADC 34 by adding a reference voltage VREF used for analog-to-digital conversion by the two ADCs to the second cell potential difference. diff .
[0047] The second ADC 34 (see Figure 1 ) comprises a converter unit, the converter unit being configured to perform a differential signal U diff The actual analog-to-digital conversion is performed and a second digital battery cell voltage signal U_AUX is provided at the output of the converter unit.
[0048] The converter units of the first ADC 24 and the second ADC 34 can be constructed identically or differently. In particular, the second ADC 34 can have a lower resolution and / or a longer settling time, since it is sufficient to perform the comparison only at certain time intervals. This allows an economical implementation and still ensures the required reliability.
[0049] The first ADC 24 and the second ADC 34 are configured to perform cell voltage U according to the same reference voltage VREF for the two ADCs 24 and 34. cell Or differential signal U diff In particular, the first ADC 24 and the second ADC 34 use the same reference voltage source.
[0050] The comparison unit 40 of the circuit arrangement (see Figure 1 ) is configured to determine comparison values according to the first digital cell voltage signal U_MAIN and the second digital level-shifted cell voltage signal U_AUX respectively according to a preset comparison function, and provide a fault signal SERR at the output end of the comparison unit when the comparison value exceeds a preset threshold value TH.
[0051] When the supply voltage VCC is used for the level shift of the second ADC 34 , the comparison function specifically includes the sum of the first digital cell voltage signal U_MAIN and the second digital level-shifted cell voltage signal U_AUX minus the target value VCC_target of the supply voltage of the second ADC 34 .
[0052] Therefore, the numeric comparison mechanism provides the following comparison values as results respectively
[0053] U_delta=U_MAIN+U_AUX-VCC formula (1a)
[0054] When the reference voltage VREF is used for the level shift of the second ADC 34 , the comparison function specifically includes the sum of the first digital cell voltage signal U_MAIN and the second digital level-shifted cell voltage signal U_AUX minus the reference voltage VREF.
[0055] In this case, the numeric comparison mechanism provides the following comparison values as results, respectively.
[0056] U_delta=U_MAIN+U_AUX-VREF formula (1b)
[0057] Furthermore, the comparison unit is designed to provide an error signal at an output of the comparison unit when the comparison value exceeds a predefined threshold value.
[0058] The first ADC 24 and the second ADC 34 use the same reference voltage VREF. When the reference voltage VREF deviates upward by 10% due to an error, the first ADC 24 determines the cell voltage for the battery cell to be
[0059] U_MAIN=1.1*U cell Formula (2)
[0060] And the second ADC 34 determines the level shift cell voltage as
[0061] U_AUX=1.1*VCC_ist-1.1*U cell , formula (3a)
[0062] Among them U cell is the measured cell voltage of the battery cell, and VCC_ist is the actual value or actual value of the supply voltage.
[0063] When the reference voltage VREF is used for level shifting, the second ADC 34 determines the level shifting cell voltage as
[0064] U_AUX=1.1*VREF-1.1*U cell Formula (3b)
[0065] In the case of using the supply voltage VCC to perform level shifting in the second ADC 34, and assuming that the target value VCC_soll and the actual value VCC_ist of the supply voltage are equal, that is,
[0066] VCC_soll=VCC_ist=VCC, formula (4)
[0067] The comparison unit 40 determines the comparison value to be
[0068] U_delta=U_MAIN+U_AUX-VCC=0.1*VCC. Formula (5a)
[0069] In the case of a supply voltage of VCC=5V, for example, this corresponds to 0.5V.
[0070] When the reference voltage VREF is used to level-shift the second ADC 34, the comparison value is:
[0071] U_delta=U_MAIN+U_AUX-VREF=0.1*VREF. Formula (5b)
[0072] If the comparison value U_delta, in particular the value of the comparison value U_delta exceeds a preset threshold value TH, it can be considered that the reference voltage VREF has a fault.
[0073] The threshold value TH can be, for example, 0 V. However, for fault determination, a threshold value that takes into account a certain tolerance range can be selected. In particular, the threshold value TH can also be preset according to temperature, for example, according to the temperature of the battery cell. The threshold value TH is preset, for example, by a microcontroller connected to the comparison unit or a higher-level calculation unit.
[0074] Alternatively, the comparison with the threshold value can be carried out in the microcontroller or in a higher-level computing unit.
[0075] Reference numerals list
[0076] 10 Circuit Devices
[0077] 20 Main monitoring channels
[0078] 22 First analog filter
[0079] 24 First ADC
[0080] 241 First level converter
[0081] 26 Digital Filter
[0082] 30 redundant monitoring channels
[0083] 32 Second analog filter
[0084] 34 Second ADC
[0085] 341 Second level converter
[0086] 40 Comparison unit
[0087] 50 evaluation units
[0088] ERR fault signal
[0089] UC cell voltage
[0090] U_MAIN The first cell voltage signal
[0091] U_AUX Second level shift cell voltage signal
[0092] TH Threshold
[0093] VCC supply voltage
[0094] VREF reference voltage
Claims
1. A circuit arrangement (10) for monitoring a battery cell of a battery, wherein The circuit arrangement (10) comprises a main monitoring channel (20) with a first analog-to-digital converter ADC (24), a redundant monitoring channel (30) with a second ADC (34) and a comparison unit (40), - the first ADC (24) is configured to perform an analog-to-digital conversion on a provided signal (Ucell) in order to obtain a first digital cell voltage signal (U_MAIN), the provided signal being representative of the cell voltage of the battery cell, - the second ADC (34) is configured to perform an analog-to-digital conversion on a differential signal (Udiff) in order to obtain a second digital level-shifted cell voltage signal (U_AUX), the differential signal representing the difference between a reference voltage (VREF) or a supply voltage (VDD) of the second ADC (34) and the provided signal (Ucell), - the first ADC (24) and the second ADC (34) are configured to perform analog-to-digital conversion of the signal (Ucell) or the differential signal (Udiff) according to the reference voltage (VREF), and the reference voltage (VREF) of the first ADC (24) is equal to the reference voltage (VREF) of the second ADC (34), and - the comparison unit (40) is configured to determine a comparison value (U_delta) according to the first digital cell voltage signal (U_MAIN) and the second digital level-shifted cell voltage signal (U_AUX) according to a preset comparison function, and provide the comparison value (U_delta) at an output end of the comparison unit (40) and / or compare the comparison value (U_delta) with a preset threshold value (TH), and if the comparison value (U_delta) exceeds the preset threshold value (TH), provide a fault signal at the output end of the comparison unit (40).
2. The circuit arrangement (10) as claimed in claim 1, wherein the circuit arrangement (10) is designed as an integrated circuit.
3. The circuit arrangement (10) according to claim 1 or 2, wherein the circuit arrangement (10) has a reference voltage source, which provides the reference voltage (VREF) for the first ADC (24) and the second ADC (34).
4. The circuit arrangement (10) as claimed in claim 1, wherein - the first ADC (24) has a first level converter (241), and The first ADC (24) has an input terminal for receiving a first measurement signal (U) representative of the potential at the positive pole of the battery cell. in_P ) and for receiving a second measurement signal (U) representative of the potential at the negative pole of the battery cell. in_n )'s second input terminal, and The first level converter (241) is configured to form the first measurement signal (U in_P ) and the second measurement signal (U in_n ) between the first and second cells, thereby providing the signal (Ucell) to the first ADC (24).
5. The circuit arrangement (10) as claimed in claim 1, wherein - the second ADC (34) has a second level converter (341), and The second ADC (34) has an input terminal for receiving a first measurement signal (U) representative of the potential at the positive pole of the battery cell. in-P ) and for receiving a second measurement signal (U) representative of the potential at the negative pole of the battery cell. in_n )'s second input terminal, and the second level converter (341) is designed to form a second cell potential difference between the second measurement signal and the first measurement signal, wherein the second measurement signal forms the minuend and the first measurement signal forms the subtrahend, The second level converter (341) is configured to provide a differential signal (U) of the second ADC (34) by adding the second cell potential difference and a reference voltage (VREF) or a supply voltage (VCC) of the second ADC (34). diff ).
6. A circuit arrangement (10) according to any one of the preceding claims, wherein the comparison function (40) represents the sum of the first digital cell voltage signal (U_MAIN) and the second digital level-shifted cell voltage signal (U_AUX) minus the reference voltage (VREF) or minus a target value (VCC_soll) of the supply voltage of the second ADC (34).
7. The circuit arrangement (10) according to any one of the preceding claims, comprising a first analog filter (22) connected upstream of the first ADC (24) and / or a second analog filter (32) connected upstream of the second ADC (34).
8. The circuit arrangement (10) of claim 7, wherein the first filter (22) and the second filter (32) have different frequency responses.
9. The circuit arrangement (10) as claimed in claim 1, wherein the first ADC (24) and the second ADC (34) differ in their resolution and / or settling time.
10. A battery system comprising a battery with at least one battery cell and comprising a circuit arrangement (10) according to any one of the preceding claims 1 to 9 for all battery cells or at least some of the battery cells.
11. A motor vehicle comprising the battery system according to claim 10.