Controller for switching converter

Abstract

A controller circuit (1012) is configured to receive a measurement signal (1040, 1050, 1072) representative of a state of a power converter and to receive a control signal (1062) representative of a resonance period of the power converter. Based on the power converter state and the power converter resonance period, the controller circuit (1012) determines a charging interval, a first dead time interval, a discharging interval, and a second dead time interval for a switching cycle. The first dead time interval is after the charging interval. The discharge interval is after the first dead time interval. The second dead time interval is after the discharge interval. The controller circuit (1012) provides a first drive signal (1030) and a second drive signal (1032) based on the charging interval, the first dead time interval, the discharging interval, and the second dead time interval.

Description

Background Art

[0001] The power supply system can transmit electric power from an alternating current (AC) source to a load. The power supply system can rectify the AC voltage to generate a direct current (DC) voltage. The power supply system can also include a power converter, such as a switching power converter, to regulate the DC voltage at a target DC voltage and provide the regulated DC voltage to the load. The power supply system can use various techniques to improve the efficiency of electric power transmission, such as reducing the phase delay between the AC current drawn from the AC source and the AC voltage, and reducing power losses during power converter switching. Summary of the invention

[0002] In one example, a device includes a controller circuit having a first control input and a second control input and a first control output and a second control output. The controller circuit is configured to: 1) receive a measurement signal representing a power converter state at the first control input; 2) receive a control signal representing a power converter resonant period at the second control input; 3) determine based on the power converter state and the power converter resonant period: a charging interval of a switching cycle; a first idle time interval of a switching cycle; a discharge interval of a switching cycle; and a second idle time interval of a switching cycle, wherein the first idle time interval is after the charging interval, the discharge interval is after the first idle time interval, and the second idle time interval is after the discharge interval; 4) within the switching cycle, provide a first drive signal at the first control output and provide a second drive signal at the second control output. During the charging interval, the first drive signal has a first state and the second drive signal has a second state. During the first idle time interval and the second idle time interval, the first drive signal and the second drive signal have a second state. During the discharge interval, the first drive signal has a second state and the second drive signal has a first state.

[0003] In another example, a method includes: 1) receiving a measurement signal representing a power converter state; 2) receiving a control signal representing a resonant period of the power converter; 3) determining based on the power converter state and the resonant period of the power converter: a charging interval of a switching cycle; a first dead time interval of the switching cycle; a discharge interval of the switching cycle; and a second dead time interval of the switching cycle, wherein the first dead time interval is after the charging interval, the discharge interval is after the first dead time interval, and the second dead time interval is after the discharge interval; and 4) providing a first drive signal and a second drive signal within the switching cycle. During the charging interval, the first drive signal has a first state and the second drive signal has a second state. During the first dead time interval and the second dead time interval, the first drive signal and the second drive signal have a second state. During the discharge interval, the first drive signal has a second state and the second drive signal has a first state.

[0004] In another example, a device includes a power converter and a controller circuit. The power converter has a positive input, a negative input, a positive output, and a negative output. The power converter includes a first switch, a second switch, and an inductor. The first switch and the second switch are coupled in series between the positive output and the negative output. The first current terminal of the first switch is coupled to the second current terminal of the second switch and the inductor. The controller circuit is configured to: 1) receive a measurement signal representing the state of the power converter; 2) receive a control signal representing the resonant period of the power converter; 3) determine based on the state of the power converter and the resonant period of the power converter: a charging interval of a switching cycle of the power converter; a first idle time interval of the switching cycle; a discharge interval of the switching cycle; and a second idle time interval of the switching cycle, wherein the first idle time interval is after the charging interval, the discharge interval is after the first idle time interval, and the second idle time interval is after the discharge interval; and 4) within the switching cycle, provide a first drive signal to the first switch, and provide a second drive signal to the second switch. In the charging interval, the first drive signal has a first state, and the second drive signal has a second state. In the first idle time interval and the second idle time interval, the first drive signal and the second drive signal have a second state. During the discharge interval, the first drive signal has the second state, and the second drive signal has the first state. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a schematic diagram of an example electrical power delivery system.

[0006] Figure 2 To show Figure 1 A waveform diagram of an example of a phase relationship between an input voltage and an input current of an electric power transmission system.

[0007] Figure 3 For what can be done Figure 1 Schematic diagram of an example power supply system of a portion of an electrical power delivery system.

[0008] Figure 4 and Figure 5 Contains shown Figure 3 A waveform diagram of an example operation of the power supply system.

[0009] Figure 6 For what can be done Figure 1 Schematic diagram of an example power supply system of a portion of an electrical power delivery system.

[0010] Figures 7 to 9 To show Figure 3 and Figure 6 A waveform diagram of an example operation of the power supply system.

[0011] Fig.10 For what can be done Figure 1 Schematic diagram of an example power supply system of a portion of an electrical power delivery system.

[0012] Fig.11 To show Fig.10 A block diagram of an example of the internal components of a power supply system.

[0013] Fig. 12A Contains shown Fig.10 Waveform diagram of current and voltage in the power supply system.

[0014] Fig. 12B To show Fig. 12A State plane diagram of the relationship between the voltage waveform and the current waveform.

[0015] Fig.13 for Fig.11 A block diagram of an example of a general interval calculation circuit is shown in FIG.

[0016] Fig.14 is a block diagram of an example interval calculation circuit including switching frequency compensation.

[0017] Fig.15 For what can be done Fig.14 A block diagram of an example compensation circuit of a portion of an interval compensation circuit.

[0018] Fig.16 is a block diagram of an example interval calculation circuit including an example switching frequency compensation circuit.

[0019] Fig.17 For what can be done Fig.14 An example of a portion of an interval compensation circuit is a block diagram of a switching frequency compensation circuit.

[0020] Fig.18 For Fig.11 Flowchart of an example method of switching period adjustment implemented by an interval calculation circuit.

[0021] Fig.19 For Fig.11 Flowchart of an example method of adaptive gain adjustment implemented by an interval calculation circuit.

[0022] Fig. 20 For what can be done Fig.11 A block diagram of an example compensation circuit system 2000 of a portion of an interval calculation circuit.

[0023] Fig.21 is a block diagram of an example interval calculation circuit including an example inductor current compensation circuit.

[0024] Fig. 22 and 23 To be available in Fig.21A block diagram of an example inductor current compensation circuit system used in an interval calculation circuit.

[0025] Fig.24 To provide input to Fig.11 A block diagram of an example time constant estimator circuit for an example interval calculation circuit of FIG.

[0026] Figure 25-27 Contains shown Fig.10 Schematic waveform diagram of an example of the internal components of a power supply system and their operation.

[0027] Fig.28 To show Fig.10 A graph of an example operation of a power supply system.

[0028] Fig.29 To show Figures 1 to 25 A block diagram of an example hardware system of portions of an example power supply system.

[0029] Fig.30 is a flow chart illustrating an example method of controlling a power converter. DETAILED DESCRIPTION

[0030] Figure 1 1 is a schematic diagram illustrating an example of an electrical power transmission system 100. The electrical power transmission system 100 may include an AC power source 102, a power supply system 104, and a load 106. The power supply system 104 may include a positive input 105a, a negative input 105b, a positive output 107a, and a negative output 107b. The AC power source 102 may provide an AC input voltage signal 108 (labeled as V in 105a). The AC input voltage signal 108 may have a positive half cycle when the voltage signal is positive (e.g., between T0 and T1 and between T2 and T3), and may have a negative half cycle when the voltage signal is negative (e.g., between T1 and T2). In the positive half cycle, the positive input 105a may receive a higher voltage than the negative input 105b, and in the negative half cycle, the polarity is reversed and the positive input 105a may receive a lower voltage than the negative input 105b. The AC input current signal 110 (labeled I in (t)) can also flow into the positive input 105a and return from the negative input 105b to the AC power supply 102 in the positive half cycle of the AC input voltage signal 108. The AC input current signal can also flow into the negative input 105b and return from the positive input 105a to the AC power supply 102 in the negative half cycle of the AC input voltage signal 108.

[0031] Based on the AC input voltage signal 108, the power supply system 104 can generate a DC output voltage signal 112 (labeled as Vout (t)). Positive output 107a can provide a positive supply rail, and negative output 107b can provide a negative supply rail. Power supply system 104 can supply a DC output voltage signal 112 to load 106, which can include electronic components that operate on a DC voltage. Power supply system 104 can also provide an output DC current signal 114 (labeled I out (t)), the DC current signal may flow from the positive output 107a, through the load 106, and back to the negative output 107b. The electrical power transmission system 100 may include a capacitor 118 to perform a filtering operation to reduce ripple in the DC output voltage signal 112 and the output DC current signal 114.

[0032] In order to generate the DC output voltage signal 112 according to the AC input voltage signal 108, the power supply system 104 may include a rectifier circuit 120 and a power converter circuit 122. The rectifier circuit 120 may perform a rectification operation to convert the AC input voltage signal 108 into a DC input voltage signal 130. As part of the rectification operation, the rectifier circuit 120 may pass the positive voltage of the AC input voltage signal 108 during the positive half cycle as the DC input voltage signal 130. The rectifier circuit 120 may also block the negative voltage of the AC input voltage signal 108 during the negative half cycle in a half-wave rectification operation, or convert the negative voltage to a positive voltage in a full-wave rectification operation, and generate a pulsating DC input voltage signal 130. The power converter circuit 122 may then generate the DC output voltage signal 112 according to the DC input voltage signal 130 based on a conversion ratio. In the case where the power converter circuit 122 is a step-up converter (e.g., a boost converter), the conversion ratio may be higher than one, and the DC output voltage signal 112 may become higher than the DC input voltage signal 130. In the case where the power converter circuit 122 is a step-down converter (eg, a buck converter), the conversion ratio may be lower than one, and the DC output voltage signal 112 may become lower than the DC input voltage signal 130 .

[0033] In addition to generating the DC output voltage signal 112, the power converter circuit 122 may also perform a power factor correction operation. The power factor may be defined as the ratio of the measured real power in Watts (W) consumed by the load 106 divided by the measured total apparent power in Volt-Amps (VA) circulating between the AC power source 102 and the load 106. A high power factor (close to one) may indicate that most of the power (apparent power) supplied by the AC power source 102 is delivered to and consumed by the load 106. A power factor correction operation may be performed to increase the power factor to one.

[0034] The power factor (PF) can be calculated from the phase relationship between the AC input voltage signal 108 and the AC input current signal 110 according to the following equation: gives:

[0035]

[0036] Figure 2 An example phase relationship between the AC input voltage signal 108 and the AC input current signal 110 and the corresponding power correction factor is shown. Graphs 202 and 204 of FIG. 202 show that the AC input voltage signal 108 and the AC input current signal 110 have a zero phase difference, which can result in a power factor of unity. Graph 204 shows that the AC input voltage signal 108 and the AC input current signal 110 have a phase difference of And the power factor may become less than unity. Figure 2 As shown, the amplitude of AC input current signal 110 in graph 204 increases (wherein the power factor decreases), so that load 106 can consume the same amount of power as in graph 202 where the power factor is unity. Therefore, increasing the power factor can improve the power transfer efficiency of power supply system 104.

[0037] Figure 3 is a schematic diagram of an example power supply system 104. Figure 3 , the power supply system 104 may include diodes 302a, 302b, 302c, and 302d coupled between the positive input 105a and the negative input 105b to form a diode bridge 304. The diode bridge 304 may be part of the rectifier circuit 120, and may perform a full-wave rectification operation to generate a pulsating DC input voltage signal 130 based on the AC input voltage signal 108. Also, the power converter circuit 122 may include an inductor 306, a switch 308, a switch 310, and may be coupled to a controller 312 that controls the switches 308 and 310. The inductor 306 and the switches 308 and 310 may be coupled at a node 314, and the switches 308 and 310 may be coupled in series between the positive output 107a and the negative output 107b. The voltage of the node 314 may switch between the positive supply rail and the negative supply rail within a switching cycle, and may be a switching node. Figure 3 In other examples, the negative output 107b can be coupled to a low impedance voltage source to provide a reference voltage and provide a return path for the output DC current signal 114.

[0038] Inductor 306 and switches 308 and 310 may be configured as a boost converter. Switch 308 may be a main switch used to control the AC input current signal 110 to flow through inductor 306 to store magnetic energy in the inductor. Switch 310 may be a synchronous rectifier (SR). When enabled, switch 310 allows inductor 306 to discharge to supply current to load 106. And, when switch 310 is disabled, the body diode of switch 310 may prevent current from flowing back from load 106 to inductor 306. Each of switches 308 and 310 may include a transistor, such as a silicon field effect transistor (FET) or a gallium nitride (GaN) high electron mobility transistor (HEMT). In Figure 3 In the example shown in , each of switches 308 and 310 may be an n-channel FET (NFET). Each switch may include a body diode and parasitic capacitance. Figure 3 , diode 316 and capacitor 318 may represent the respective body diode and parasitic capacitance of switch 308 , and diode 326 and capacitor 328 may represent the respective body diode and parasitic capacitance of switch 310 .

[0039] The controller 312 may generate a control signal 330 (in Figure 3 Marked as V M ). The controller 312 may also generate a control signal 332 (in Figure 3 Marked as V SR ). The controller 312 may receive a DC output voltage signal 112 (V out (t))(See Figure 1 ), receiving a DC input voltage signal 130 (V in,dc (t)) and receives a reference DC output voltage 360. The controller 312 may control the control signal V based on the measurement result and the reference. M and V SR The timing and duration of the control signal V may be adjusted to achieve the target value of the DC output voltage signal 112. Furthermore, the controller 312 may determine the control signal V based on the measurement result of the AC input voltage signal 108. M and V SR The duration of the switching operation is to reduce the phase difference between the AC input voltage signal 108 and the AC input current signal 110, reduce the harmonic distortion in the AC input current signal 110, and improve the power factor. During the entire switching cycle, a voltage V may be generated across the inductor 306. L, which may affect the AC input current signal 110 and the DC output voltage signal 112 .

[0040] Figure 4 Contains shown Figure 3 1 is a waveform diagram of an example operation of the power converter circuit 122. Figure 4 The graph includes curves 402, 404, 406 and 408. Curve 402 shows the control signal 330 (V M ) with respect to time, and curve 404 shows the control signal 332 (V SR ) with respect to time, both of which are controlled by the controller 312. Also, curve 406 shows the change of the inductor current flowing through the inductor 306 with respect to time, and curve 408 shows the change of the voltage of the node 314 with respect to time.

[0041] The first switching cycle (sw1) begins at time T0. T0 to T1 may be a first charging interval in which the controller 312 provides V in a first state. M signal to enable the main switch 308 and provide V SR The first state may be opposite to the second state. In the case where the main switch and the SR switch 310 are NFETs, V M and V SR The signals may each be a gate voltage that is at least greater than the source voltage by a conduction threshold of the NFET, and V M and V SR The signals may each be a gate voltage lower than the sum of the source voltage and the conduction threshold. When the main switch 308 is enabled, the voltage at the node 314 may be grounded, and the voltage V across the inductor 306 may be L Can be equal to the DC input voltage signal 130 (V in,dc ). Inductor 306 may charge during a first charging interval between T0 and T1, and an increasing positive charging current that charges inductor 306 may flow from inductor 306 to switch 308. Diode 326 is reverse biased and may block current from load 106 / capacitor 118 from flowing back to switch 308 and ground. In the case where inductor 306 has an inductance L, inductor current I may increase based on the following equation: L , the inductor current may be equal to the AC input current signal 110 (I in (t)):

[0042]

[0043] In equation 2, when the DC input voltage signal is 130 (V in,dc ) is positive, the slope of the inductor current is also positive, and the inductor current increases between time T0 and T1. The positive inductor current may reach a peak (or close to a peak) at time T1. The duration between time T0 and T1 is equal to t M In the case of , it represents the duration of the on-interval of the main switch 308 during which the main switch 308 is enabled, the positive peak inductor current I at time T1 p,峰值 Based on the following equation and V in,dc and t M Related:

[0044]

[0045] T1 to T2 may be a first idle time interval, during which the controller 312 may set V M and V SR The two signals are set to the second state to disable the respective switches 308 and 310. The duration between T1 and T2 (labeled as t dt1 ) may include the first resonant interval of the switching cycle (labeled as t res1 ), where inductor 306 resonates with capacitors 318 and 328. During the first resonant interval, the inductor current from inductor 306 can charge capacitor 318 and discharge capacitor 328, and the voltage of node 314 can increase until it is clamped to the positive supply rail (e.g., V out ). Therefore, t dt1 may be or may include the peak resonant transition interval. Since the peak inductor current is used to charge capacitor 318 and discharge capacitor 328, t res1 Can be relatively short.

[0046] T2 to T3 may be a discharge interval, in which the controller 312 may set V M The signal is set to the second state to continue to disable the main switch 308 and to set V SR The signal is set to a first state to enable the SR switch 310. The inductor 306 dissipates the stored magnetic energy to supply a discharge current to the load 106 and the capacitor 118. At node 314, V out Under the condition that the inductor voltage V L becomes V in,dc -V out , and the rate of change of the inductor current becomes:

[0047]

[0048] Since V in,dc In step-up conversion operation, the out , so V Lbecomes negative, and the inductor 306 discharges to supply current to the load 106 and / or the capacitor 118. is a negative value, so the inductor current and the input current I in (t) can be between T2 and T3 from the positive peak current (I p,峰值 ) decreases linearly. The inductor current may continue to decrease between T2 and T3 and become negative. The negative inductor current may flow to the AC power source 102, removing charge from the capacitor 318 of the main switch 308 and adding charge to the capacitor 328 of the SR switch 310. The duration between T2 and T3 is equal to t SR , which represents the on-interval of the SR switch 310 during which the SR switch is enabled. The negative discharge current of the inductor when the SR switch 310 is disabled may be the SR turn-off current.

[0049] The SR turn-off current may be based on the positive peak charging current, the inductance of the inductor 306 which sets the rate of decrease of the inductor current, and the duration t of the on-interval of the SR switch 310. SR In some examples, the controller 312 may determine t based on determining the SR off current required to remove the charge of the capacitor 318 of the main switch 308 and add the charge to the capacitor 328 of the SR switch 310 in a subsequent resonant interval. SR With such an arrangement, node 314 may drop to the negative supply rail (e.g., ground) before the primary switch 308 is enabled again. Since the voltage across the primary switch 308 is zero (or below zero) when the state of the primary switch 308 is switched, zero voltage switching (ZVS) may be achieved, which may reduce power losses during switching of the primary switch 308.

[0050] In some examples, the controller 312 may be configured to generate a voltage signal based on the DC input voltage signal 130 (V in,dc ) and the DC output voltage signal 112 (V out ) to determine t SR The DC input voltage can affect the positive peak inductor current (I p,峰值 ) and the amount of charge stored in capacitor 318 of main switch 308, which in turn may affect the amount of SR off current required to discharge capacitor 318 and bring the voltage of node 314 to ground in the second resonant interval. in,dc Equal to or less than V out half, then zero SR off current may be sufficient. But if V in,dc Beyond V out half of the time, the controller 312 may extend the on-time t of the SR switch 310. SR , so that the SR disconnection current is a negative current (eg, flowing toward the AC power source 102). The controller 312 may determine the minimum SR disconnection current and the minimum SR disconnection current based on Vin,dc 、V out , the inductance of inductor 306 , and the total capacitance of capacitors 318 and 328 when SR switch 310 is disabled.

[0051] T3 to T5 may be a second idle time interval, during which the controller 312 may set V M and V SR The signals are both set to the second state to disable switches 308 and 310. The duration of the second dead time interval (labeled t dt2 ) may include a second resonant interval (t res2 ), where inductor 306 and capacitors 318 and 328 form a resonant system. During the second resonant interval, the negative inductor current may remove charge from capacitor 318 of main switch 308 and add charge to capacitor 328 of SR switch 310. This causes the voltage of node 314 to drop to ground voltage due to resonance. Therefore, t dt2 The controller 312 may be based on the SR disconnection current, V in,dc 、V out and the resonant frequency determines t res2 , the SR turn-off current may be based on the total capacitance of capacitors 318 and 328 and the inductance of inductor 306. The voltage at node 314 may drop to the negative supply rail (eg, Figure 3 in the land).

[0052] T4 to T5 may be part of the second charging interval, when the voltage of node 314 drops to the ground voltage and becomes lower than V in,dc When the positive inductor voltage V L The inductor current may flow through the diode 316 of the main switch 308. The inductor 306 may be charged between T4 and T5, and the polarity of the inductor current may change during the second charging interval, or may depend on the initial conditions at T4.

[0053] At T5, the controller 312 can M The signal is set to the first state to enable the main switch 308 and start a new switching cycle sw2 that ends at time T6. At T5, since the voltage across the main switch 308 is zero when enabled, zero voltage switching (ZVS) can be achieved, which can reduce the power dissipation caused by the activation / deactivation of the main switch 308 and further improve the efficiency of the power converter circuit 122.

[0054] Because the average inductor voltage V in the steady state L is equal to zero, so the DC input voltage signal 130 (V in,dc) and DC output voltage signal 112 (V out ) can be related to the on-time (t M ) and the on-time (t SR )Related:

[0055] V in，dc ×t M +(V in,dc -V out )×t SR =0 (Equation 5)

[0056] According to Equation 5, the DC output voltage signal 112 (V out ) can be compared with the DC input voltage signal 130 (V in,dc )Related:

[0057]

[0058] See again Figure 3 , the controller 312 may receive a measurement result 350 of the DC input voltage signal 130, a measurement result 340 of the DC output voltage signal 112, and a reference DC output voltage 360 ​​at the beginning of a switching cycle, and set t of the switching cycle based on the measurement results and Equation 6. M and t SR For example, the controller 312 may include a proportional-integral (PI) controller that integrates the difference between the DC output voltage signal 112 and the reference DC output voltage 360 ​​and determines t of the switching cycle based on comparing the integrated difference to the DC input voltage signal 130 as in Equation 6. M and t SR .

[0059] Also, the controller 312 may set the t of each switching cycle for power factor correction operation. M and / or SR In some examples, the controller 312 may set t M and / or SR The power converter circuit 122 is operated in a critical conduction mode (CRM), wherein the controller 312 enables the main switch 308 when the inductor current is at (or close to) zero at the beginning of each switching cycle, such as Figure 4. The critical conduction mode may have various advantages. For example, when the main switch 308 is enabled and the SR switch 310 is disabled when the inductor current is zero, zero current switching (ZCS) may be achieved, which may reduce the power dissipation caused by the enabling / disabling of the switches and improve the efficiency of the power converter circuit 122. In addition, because no current flows through the SR switch 310 when it is disabled, the diode 326 of the SR switch 310 does not need to have a fast recovery time, which allows the SR switch 310 to be implemented with a relatively low bandwidth device and / or allows the power converter circuit 122 to operate at a higher switching frequency.

[0060] Figure 5 Graph 502 is included, which shows the CRM operation performed by controller 312 within a half cycle of AC input voltage signal 108. Graph 502 includes curves 504, 506, 508, 510, 512, and 514. Curve 504 represents the reference DC output voltage 160. Curve 506 represents the positive half cycle of DC input voltage signal 130 or AC input voltage signal 108. Graph 508 represents the inductor current through inductor 306, and graph 510 represents the AC input current signal 110 (I in ) of the average inductor current. Graph 512 represents the V M The curve 514 shows the change of the V SR Signal changes.

[0061] exist Figure 5 In each switching cycle, the controller 312 may be based on the target positive peak current I p,峰值 Determine the duration of the main switch on interval (t M ), which in turn can set the average input current within the switching cycle. In order to reduce the phase difference between the AC input current signal 110 and the AC input voltage signal 108, the controller 312 can determine t M , so that the average input current of each switching cycle has a constant relationship with the AC input voltage signal of the corresponding switching cycle. Referring again to Equation 3, when the DC input voltage signal 130 (which reflects the AC input voltage signal 108) is proportional to the positive peak current in the switching cycle, the controller 312 can set t to t based on the target current to be supplied to the load 106 and the capacitor 118. M The controller 312 can also adjust the duration of the SR switch on interval (t SR ) to provide the time for the inductor current to fall from the positive peak to zero, and adjust the DC output voltage signal 112 (V out ) and DC input voltage signal 130(V in,dc) because the DC input voltage and the positive peak inductor current vary as the AC input voltage varies. Therefore, the switching cycle may have a varying frequency. The switching cycle period may be at a maximum when the DC input voltage signal 130 becomes closer to the reference DC output voltage 160, and the controller 312 may increase t SR To reduce the step-up ratio. Also, the switching frequency may be at a maximum value when the DC input voltage signal 130 is close to zero, and the controller 312 may reduce t SR To increase the step ratio. For example, Figure 5 Including t M (3) and t SR The third cycle of (3) and the cycle including t M (4) and t SR The fourth cycle of (4) may have a maximum duration within a half cycle and include t M (0) and t SR (0) and including t M (7) and t SR The seventh cycle of (7) may have a minimum duration within a half cycle.

[0062] Figure 6 FIG. 1 is a schematic diagram of another example of a power supply system 104 in which a set of switches and their body diodes are used to perform the operations of the rectifier circuit 120 and the power converter circuit 122. Figure 6 , the power supply system 104 may include a power converter circuit 122, the power converter circuit including an inductor 306 and switches 602, 604, 606 and 608, and a controller 612 coupled to the power converter circuit 122. Switches 602, 604 and inductor 306 are coupled at a node 614, and switches 602 and 604 are coupled in series between the positive output 107a and the negative output 107b. Node 614 can be switched between the positive supply rail and the negative supply rail and can be a switching node. In addition, switches 606 and 608 are coupled at a node 620, and switches 606 and 608 are also coupled in series between the positive output 107a and the negative output 107b. Inductor 306 is coupled between the positive input 105a and node 614, and node 620 between switches 606 and 608 is coupled to the negative input 105b.

[0063] Switches 602, 604, 606, and 608 may be NFETs. Switch 602 and switch 604 may be configured to receive an AC input voltage signal 108 (V in), and switches 606 and 608 may switch once in each half cycle of the AC input voltage signal. Each of switches 602 and 604 may have a higher bandwidth than the corresponding switches 606 and 608. In some examples, each of switches 602 and 604 may include a transistor, such as an NFET or a GaN HEMT, and each of switches 606 and 608 may include a FET. Switch 602 may have a body diode 616 and a parasitic capacitor 618, and switch 604 may have a body diode 626 and a parasitic capacitor 628. Switch 606 may have a body diode 627, and switch 608 may have a body diode 629. For simplicity, the parasitic capacitances of switches 606 and 608 are omitted.

[0064] In some examples, switches 602, 604, 606, and 608 and inductor 306 can be configured as a totem pole boost rectifier. Controller 612 can generate control signals 630 (labeled as VG1), 632 (labeled as VG2), 634 (labeled as VG3), and 636 (labeled as VG4) to enable / disable switches 602, 604, 606, and 608, respectively, to perform rectification, power factor correction, and step-up conversion operations.

[0065] The negative input 105b receives a lower voltage V than the positive input 105a. in During the positive half cycle of , switch 606 is enabled to couple the negative supply rail (and negative output 107b) to the negative input 105b to receive the lower input voltage, while inductor 306 (when switch 604 is enabled) can connect the positive supply rail (and positive output 107a) to the positive input 105a. Therefore, the positive output 107a can have a positive polarity and the negative output 107b can have a negative polarity. And, switch 608 is disabled to allow the inductor current to flow through capacitor 118 and load 106 and return to the AC power source 102 via switch 606. Controller 612 can operate switch 602 as a main switch and switch 604 as an SR switch. Controller 612 can generate an equivalent to Figure 4 The control signal V M The control signal VG1 sequence is equivalent to the control signal V SR The control signal VG2 sequence. in During each switching cycle of the positive half cycle, during the charging interval (t M ), switch 602 is enabled and switch 604 is disabled. The charging interval also includes a first charging interval in which the inductor is charged. The charging interval is followed by a first idle time interval (t dt1 ), in the first idle time interval, both switches are disabled. The first idle time interval may include a first resonant interval t res1In the first resonant interval, the voltage of node 614 is transferred to the positive supply rail (eg, V out The first no-load time interval is followed by a discharge interval (t SR ), in which the switch 602 is disabled and the switch 604 is enabled, and the inductor is discharged. The discharge interval is followed by a second idle time interval (t dt2 ), the second idle time interval may include a second resonant interval t res2 The inductor 602 is connected to the inductor 614 by the voltage of the node 614. ...

[0066] The negative input 105b receives a higher voltage V than the positive input 105a. in During the negative half cycle of , switch 608 is enabled to couple the positive supply rail (and positive output 107a) to the negative input 105b to receive a higher input voltage, while the negative supply rail (and negative output 107b) is coupled to the positive input 105a to maintain the same polarity between the positive supply rail and the negative supply rail in the positive and negative half cycles. Also, switch 606 is disabled to allow the inductor current to flow through capacitor 118 and load 106 and return to the AC power source 102 via switch 602. Controller 612 can operate switch 604 as a main switch and switch 602 as an SR switch. Controller 612 can generate an output voltage equivalent to Figure 4 The control signal V M The control signal VG2 sequence is equivalent to the control signal V SR The control signal VG1 sequence. in During each switching cycle of the negative half cycle, during the charging interval (t M ), switch 602 is enabled and switch 604 is disabled, and the inductor is charged. The charging interval is followed by a first idle time interval (t dt1 ), in the first idle time interval, both switches are disabled and the voltage of node 614 is transferred to the negative supply rail (eg, ground) by resonance. The first idle time interval is followed by a discharge interval (t SR ), in which the switch 602 is disabled and the switch 604 is enabled, and the inductor is discharged. The discharge interval is followed by a second idle time interval (t dt2 ), during the second idle time interval, the voltage of node 614 is transferred to the positive supply rail (eg, V out), the inductor is then charged, and a new switching cycle can begin after the second idle time interval. If the voltage at node 614 reaches V at the end of the second interval out If the switch 602 changes from the disabled state to the enabled state, then ZVS can be achieved so that when the switch 602 changes from the disabled state to the enabled state, the voltage across the switch 602 is zero (or below zero) to start a new switching cycle.

[0067] The controller 612 may receive the DC output voltage signal 112 (V out ) and receiving the AC input voltage signal 108 (V in ) and receives the reference DC output voltage 360. The controller 612 can determine whether the AC input voltage signal 108 is in the positive half cycle or the negative half cycle based on the measurement result 660. The controller 612 can also determine the t of the switch 602 based on the measurement result 650 and the reference DC output voltage 360 ​​in both half cycles. M and t of switch 604 SR .

[0068] In some instances, to operate under CRM Figure 3 and Figure 6 In an example power converter of , a controller (e.g., controllers 312 and 612) may measure the inductor current through inductor 306 during the on-interval of the SR switch when the inductor current decreases, and disable the SR switch when the inductor current crosses zero or reaches a minimum SR off-current to achieve zero voltage switching (ZVS), wherein the minimum SR off-current is sufficient to allow the voltage across the main switch to complete the transition to one of the power rails in the second resonant cycle. If the magnitude of the AC input voltage exceeds half of the DC output voltage, the controller may extend the on-interval (t SR ), as described above. In addition, the controller may determine the duration of the second idle time interval (t dt2 Specifically, the controller detects the inductor current within the switching cycle and determines the on-time (t SR ), and adjust the timing of the control signals of the main switch and the SR switch within the same switching cycle.

[0069] Figure 7 The graphs 702, 704, 706, and 708 are included, which illustrate example operation of the power converter circuit 122 and the delay between two switching cycles to V SR Curve 702 shows the effect of adjusting the control signal V M The control signal changes with respect to time, and curve 704 shows V SRThe control signal changes with respect to time. Also, curve 706 shows the change of the inductor current with respect to time, and curve 708 shows the change of the voltage at the node 314 / 614 with respect to time. The time symbol is based on Figure 4 .

[0070] like Figure 7 As shown in FIG. 1 , at the end of the first switching cycle sw1, at time T3, the inductor current crosses zero. The controller may deactivate the SR switch at time T3 to provide an SR off current sufficient to complete the transition of node 314 / 614 to one of the supply rails. If the SR switch is deactivated at time T3, the negative inductor current may reach a peak value I n0 . However, due to the delay T D , deactivating the SR switch at time T3'. Therefore, the inductor current becomes more negative after time T3 and reaches a peak value I n1 .

[0071] There are various possibilities that may contribute to and increase the delay T D Sources of. For example, circuits involved in inductor current measurement, such as current sensors and ADCs, have limited bandwidth and may cause delays in providing current measurement data to the controller. The controller may also cause delays in calculating a target SR disconnect current amount for a switching cycle based on the AC input voltage and the DC output voltage, and determining whether to disable the SR switch by comparing the target SR disconnect current with the inductor current indicated by the current measurement data. In addition, the controller may include circuits, such as pulse width modulator (PWM) circuits and drive circuits, to generate and transmit control signals to the main switch and the SR switch. Those circuits may also cause additional delays in generating control signals.

[0072] The additional negative peak inductor current can increase the current ripple, which can cause additional power loss and increase distortion in the AC input current. Specifically, the average current of each switching cycle is based on the negative peak current and the positive peak current I p,峰值 If the negative peak current becomes more negative compared to the target negative peak current of the switching cycle, then the average AC input current over the entire switching cycle may no longer follow the AC input voltage, which may result in considerable distortion.

[0073] To reduce distortion, the controller may increase the positive peak current of the switching cycle (eg, by increasing the on-time t of the main switch). MTo match the negative peak current. Such an arrangement can maintain the shape of the average inductor current throughout the switching cycle, and the average inductor current can have a constant relationship with the AC input voltage. However, increasing the positive peak current in each switching cycle can result in additional power being drawn from the AC source, and much of the additional power being lost due to the negative inductor current that does not flow to the load. This can increase power losses in the power supply system 104 and reduce the efficiency of power transfer from the AC source 102 to the load 106.

[0074] Figure 8 Curves 802 and 804 show example variations of the inductor current of the power supply system 104 with respect to time. Curve 802 shows that there is no delay T in a half cycle of the AC input voltage. D , and curve 804 shows a delay T of about 100 nanoseconds (ns) in the same half cycle. D See the change of inductor current under the condition of Figure 8 , near zero AC input voltage in intervals 812 and 814, the inductor current has a larger current fluctuation in curve 804 than in curve 802. For example, at the beginning and end of the half cycle, the maximum current ripple is at 4 amperes (A) without delay, but at 13 A with delay. In the operation of curve 802, there is no delay T D , but the controller can extend the on-interval of the SR switch and provide additional negative inductor current to discharge the main switch in the second resonant interval, as described above. In curve 804, the delay T D It can also extend the on-time of the SR switch (t SR ) to provide additional negative inductor current. The increased current ripple in intervals 812 and 814 may generally increase power losses in the power supply system 104 and reduce the efficiency of power transfer from the AC power source 102 to the load 106.

[0075] And, see again Figure 7 After determining that the SR switch will be deactivated at T3, the controller may determine a second idle time interval (t dt2 ) duration to provide time for the voltage of node 314 / 614 to transition to one of the supply rails, and determine that the main switch will be enabled to start the next switching cycle (sw2) at time T4 to achieve ZVS of the main switch, while Figure 4 The controller can be based on the SR off current (the inductor current when the SR switch is disabled), the input voltage ( Figure 6 V in or Figure 3 V in,dc ), output voltage Vout The resonant frequency of the inductor 306 with the parasitic capacitances of the main switch and the SR switch at the switching node determines the second resonant interval t res2 , as described above, and dynamically changing the duration of the second dead time interval t dt2 To match or adapt the second resonant interval t between different switching cycles res2 .

[0076] Fig. 9 The duration t of the second resonant interval within a half cycle of the AC input voltage is shown in FIG. res2 900 is a graph of example changes with respect to time. Fig. 9 In the operation represented in FIG. 1 , a minimum SR off current amount is provided in each switching cycle to allow the switching node (e.g., node 314 / 614) to transition to one of the supply rails. Also, a minimum second resonant interval is provided in each switching cycle of the switching node to complete the transition, and the duration of the second resonant interval varies according to the SR off current. The second dead time interval duration (t dt2 ) to match the second resonant interval in each switching cycle. Fig. 9 In the example, t res2 The controller can set the on-time (t) of the SR switch between 0 and about 2 milliseconds (ms). SR ) to have zero SR off current, and t res2 It can increase with the increase of AC input voltage and reach the peak at about 0.28ms. Between 2ms and 4.1ms, the controller can extend the on-time of the SR switch to increase the negative SR off current, and t res2 The extension of the on-interval of the SR switch increases with the increase of the AC input voltage and reaches a maximum value at 4.1ms. Between 4.1ms and 6.5ms, the extension of the on-interval of the SR switch decreases with the increase of the AC input voltage, which reduces the negative SR off current and increases t res2 Between 6.5ms and 8.2ms (end of half cycle), the controller can set the on-time of the SR switch t SR , so that there is zero SR off current, and t res2 It can decrease as the AC input voltage increases.

[0077] The operation represented by curve 900 (where the controller adjusts the duration t of the second dead time interval in each switching cycle based on the minimum SR off current) dt2To match the changing second resonant interval) can use a lot of power in sensing, processing and calculation, but is still prone to errors, which can reduce the efficiency of the power converter. Specifically, in order to adjust the duration of the second resonant interval in each switching cycle, the controller can receive the measurement of the SR disconnection current from the current sensor in each switching cycle, and perform calculations to determine the resonant time based on the SR disconnection current and the dead time to adapt the resonant time. However, this may require the current sensor to have a high bandwidth and high accuracy, and such a current sensor may consume a lot of power. In addition, calculating the duration of the second dead time interval may be computationally intensive, and performing such calculations in each switching cycle may also cause the controller to incur considerable power consumption.

[0078] Furthermore, adjusting the duration of the second dead time interval based on the SR off current may be prone to error. Specifically, the controller may determine the duration t of the on time of the SR switch based on measuring the SR off current. SR and the duration of the second idle time interval t dt2 (and the second resonant interval), the SR off current can be represented by the inductor current when the SR switch is disabled. However, as described above, the circuits involved in the inductor current measurement, such as the current sensor and ADC, have limited bandwidth and may cause delays in providing current measurement data to the controller. Due to the delay, when the SR switch is disabled, the controller used to determine t dt2 The current measurement data may not reflect the actual inductor current, which may occur at t SR and t dt2 If t dt2 If t is too short, the controller may enable the main switch before the voltage at node 314 / 614 transitions to one of the supply rails, which results in non-ZVS and may cause additional power loss when the main switch switches. dt2 If the inductor current is too long, the controller may enable the main switch long after the voltage at node 314 / 614 transitions to one of the supply rails. This may cause the inductor current to Figure 4 The current flowing between T4 and T5 through the body diode of the main switch (for example, Figure 3 The diode 316 in the positive half cycle Figure 6 The body diode 616 in the negative half cycle Figure 6 Since the body diode has a larger resistance than the enabled main switch, a larger power loss may be induced, which may reduce the efficiency of the power supply system 104.

[0079] Fig.10 FIG. 1 is a schematic diagram of a power converter circuit 122 that can solve at least some of the problems described above. Fig.10, power converter circuit 122 may include inductor 306, switch 1008 and switch 1010, and controller 1012 coupled to power converter circuit 122. Controller 1012 may control switches 1008 and 1010. Controller 1012 may be part of a microcontroller (MCU), an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). Inductor 306 and switches 1008 and 1010 may be coupled at switching node 1014, and switches 1008 and 1010 may be coupled in series between positive output 107a and negative output 107b. In some examples, switches 1008 and 1010 may be Figure 3 of the boost converter, where switches 1008 and 1010 correspond to Figure 3 The main switch 308 and the SR switch 310 of , and the inductor 306 is coupled to the positive input 105a via the rectifier circuit 120 (eg, the diode bridge 304). In some examples, the switches 1008 and 1010 may also be part of a totem pole boost converter and correspond to Figure 6 100 and 1010. The inductor 306 may be directly coupled to the positive input 105a. In the positive half cycle of the AC input voltage signal 108, the switch 1008 may act as a main switch and the switch 1010 may act as an SR switch. In the negative half cycle of the AC input voltage signal 108, the switch 1008 may act as an SR switch and the switch 1010 may act as a main switch. Fig.10 In FIG. 1 , the body diode and the parasitic capacitance of switches 1008 and 1010 are omitted for simplicity.

[0080] The controller 1012 may generate a control signal 1030 (at Fig.10 Marked as V G1 ) to enable / disable switch 1008 and control signal 1032 (at Fig.10 Marked as V G2 ) to enable / disable switch 1010. Controller 1012 may provide a control signal 1030 at a first control output coupled to a first power converter control terminal (e.g., a control terminal of switch 1008). Controller 1012 may provide a control signal 1032 at a second control output coupled to a second power converter control terminal (e.g., a control terminal of switch 1010). Figure 4 In the case where the controller 1012 operates the switch 1008 as the main switch and the switch 1010 as the SR switch, the controller 1012 may include a first idle time interval (t t ) between the end of the on-interval of the switch 1008 and the beginning of the on-interval of the switch 1010 within one switching cycle. dt1), and a second dead time interval (t dt2 ). Also, in the case where the controller 1012 operates the switch 1010 as the main switch and the switch 1008 as the SR switch, the controller 1012 may include a first idle time interval (t t ) between the end of the on-interval of the switch 1010 and the beginning of the on-interval of the switch 1008 within one switching cycle. dt1 ), and a second dead time interval (t dt2 ).

[0081] In some examples, to simplify the determination of V G1 and V G2 The timing of the control signal involves calculations, and the controller 1012 can in ) in a cycle of , setting the duration of the second dead time interval to a constant value in a plurality of switching cycles, and determining the duration of the first dead time interval (t dt1 ), duration of the on-interval of the main switch (t M ) and the duration of the on-interval of the SR switch 1010 (t SR ). In some examples, the controller 1012 may set the duration of the second idle time interval based on a programmed value. Since the controller 1012 does not need to calculate the duration of the second idle time interval for each switching cycle, the controller 1012 may determine the duration of the second idle time interval based on a programmed value. G1 and V G2 The calculations involved in the timing of the control signal can be substantially reduced. The controller 1012 can adjust the on-time (t SR ) to adjust the SR disconnection current so that the switching node 1014 can complete the transition to the target voltage (e.g., one of the positive / negative power rails) within the second idle time interval, so that the activation of the main switch can be under ZVS conditions. Such an arrangement also allows the second resonant interval t res2 The controller 1012 may adjust the on-interval of the switch 1010 so that the switching node 1014 can complete the transition to the negative power rail at the end of the second dead time interval before the switch 1008 (acting as the main switch) is enabled. In the case where the switch 1008 is operated as an SR switch, the controller 1012 may adjust the on-interval of the switch 1010 so that the switching node 1014 can complete the transition to the positive power rail at the end of the second dead time interval before the switch 1010 (acting as the main switch) is enabled. In the case where the switch 1008 is operated as an SR switch, the controller 1012 may adjust the on-interval of the switch 1008 so that the switching node 1014 can complete the transition to the positive power rail at the end of the second dead time interval before the switch 1010 (acting as the main switch) is enabled.

[0082] The controller 1012 may receive a DC output voltage signal 112 (V out (t)) measurement result 1040, receiving AC input voltage signal 108 (V in (t)) and receives a reference DC output voltage 1060. In some examples, the controller 1012 may also receive programming data 1062 for determining the on-interval of the switch 1008, the on-interval of the switch 1010, the first dead time interval, and / or the second dead time interval. The programming data 1062 may include, for example, a resonant time constant representing the resonant circuit. The programming data 1062 may include a value representing the resonant impedance of the resonant circuit formed by the inductor 306 and the capacitor, wherein the capacitor represents the total parasitic capacitance of the switches 1008 and 1010 at the switching node 1014 coupled to the inductor 306, for example, where L may represent the inductance of the inductor 306 and C may represent the capacitance. In some examples, the programming data 1062 may include a value representing the resonant impedance of the resonant circuit formed by The controller 1012 can control the charging interval / on interval (t M ) and the discharge interval / on interval (t SR ) to achieve the target DC output voltage signal 112. In addition, the controller 1012 can determine the control signal V based on the measurement result of the AC input voltage signal 108. G1 and V G2 of duration to maintain a constant relationship between the AC input current signal 110 and the AC input voltage signal 108, as described above.

[0083] Furthermore, the power converter circuit 122 may include a transition measurement circuit 1070 to determine the transition state of the switching node 1014 when the main switch (one of the switches 1008 or 1010) changes state at the beginning of a switching cycle. The transition measurement circuit 1070 may be coupled to the switching node 1014 and may receive a control signal 1030 (V G1 ) or control signal 1032(V G2). Based on the voltage of the switching node 1014, the transition measurement circuit 1070 may determine whether the switching node 1014 transitions to the target voltage (e.g., one of the positive supply rail or the negative supply rail) at the beginning of the switching cycle to achieve zero voltage switching (ZVS) of the main switch of the power converter. And, based on one of the control signals 1030 or 1032, the transition measurement circuit 1070 may generate an indication signal 1072 indicating whether the switching node 1014 completes the transition before the controller 1012 enables the main switch. In some examples, the transition measurement circuit 1070 may include a comparator and a digital logic circuit, wherein the comparator is used to compare the voltage of the switching node 1014 with a threshold based on the target voltage, and the digital logic circuit is used to compare the voltage of the switching node 1014 with a threshold based on the output of the comparator and the output from the main switch (V G1 or V G2 The timing of the control signal of the controller 1012 of one of the controllers 1012 generates an indication signal 1072.

[0084] In the case where switches 1008 and 1010 are part of a boost converter, where switch 1008 is a main switch and switch 1010 is an SR switch, transition measurement circuit 1070 may be based on whether switch node 1014 is switched when main switch 1008 passes control signal V G1 The transition measurement circuit 1070 generates an indication signal 1072 before the switch 1008 and 1010 are part of a totem pole boost converter. In addition, in the case where the switches 1008 and 1010 are part of a totem pole boost converter, the transition measurement circuit 1070 may also receive a measurement result 1050 of the AC input voltage signal 108. If the power supply system 104 is in a positive half cycle of the AC input voltage, where the switch 1008 acts as a main switch and the switch 1010 acts as an SR switch, the transition measurement circuit 1070 may generate an indication signal 1072 based on whether the switching node 1014 is in the positive half cycle of the AC input voltage, where the switch 1008 acts as a main switch and the switch 1010 acts as an SR switch. G1 If the power supply system 104 is in the negative half cycle of the AC input voltage, where the switch 1008 acts as an SR switch and the switch 1010 acts as a main switch, the transition measurement circuit 1070 can generate an indication signal 1072 based on whether the switching node 1014 is in the negative half cycle of the AC input voltage. G2 The indicator signal 1072 is generated by transitioning to the positive supply rail before enabling.

[0085] The controller 1012 can adjust the switching cycle period based on the indication signal 1072. If the indication signal 1072 indicates that the switching node 1014 completes the transition before the main switch 1008 changes from the disabled state to the enabled state, such indication can reflect that the SR disconnection current is for the switching node during the second idle time interval t dt2 Therefore, the controller 1012 can reduce the duration of the switching cycle, which can also result in t SRThe duration of t is reduced to generate less SR disconnection current, and the negative value of the SR disconnection current may become smaller when the SR switch is disabled. However, if the indication signal 1072 indicates that the switching node 1014 has not completed the transition before the controller 1012 enables the main switch 1008, such indication may reflect that the SR disconnection current is for the switching node at t dt2 is insufficient to complete the transition within t, and the controller 1012 may increase the switching cycle period, which may also cause t SR The duration of t is increased to increase the SR off current, and the negative value of the SR off current can become larger when the SR switch is disabled. With such an arrangement, the controller 1012 can adjust t SR and SR disconnects the current, so that the switching node 1014 can be in the second idle time interval t dt2 The transition to the target voltage (eg, ground voltage) is completed within t dt2 and t res2 The condition remains fixed during the switching cycle.

[0086] In the example of the power supply system 104 described herein, the controller 1012 may be configured to provide a second idle time interval (t dt2 ) and the transcendental equations determine the first idle time interval (t dt1 ), charging interval (t M ) and discharge interval (t SR ), and the timing of control signal 1030 and control signal 1032, where t is expressed relative to the switching cycle period. dt1 ,t dt2 ,t M and t SR The angle of the duration of the phase angle is a variable. Based on. In some cases, iterative numerical methods can be used to solve these equations, but the iterative numerical methods can be computationally intensive and may not be suitable for real-time implementation. Moreover, the phase angle determined according to the iterative numerical method may or may not represent an exact analytical solution to the equation, which may reduce the accuracy of determining t to provide switching under ZVS conditions. dt1 ,t dt2 ,t M and t SR The duration of the dt2 One of them is preset to a specific value, and these equations can be solved using an exact analytical solution, which can reduce the calculation of t dt1 ,t dt2 ,t M and t SR The complexity and speed up the calculation. And, because t dt1 ,t dt2 ,t M and t SRAs part of the exact analytical solution, the calculated values ​​reflect the t dt1 ,t dt2 ,t M and t SR In some examples, the controller 1012 may set the angle of the second dead time interval, which may represent the valley resonant transition interval, to 90°, thereby allowing the use of mathematical identities to simplify equations and calculations for analytical solutions. The interval values ​​are calculated and used to generate control signals 1030 and 1032.

[0087] The controller 1012 does not rely on a high bandwidth current sensor, thereby reducing circuit complexity and cost. Accurate dead time control reduces hard switching and improves switching transistor performance. Also, because t dt1 ,t dt2 ,t M and t SR It can be updated quickly due to the reduced computational complexity, so when adjusting t dt1 ,t dt2 ,t M and t SR The delay when switching on and off can be reduced, which can reduce current ripple and distortion (e.g., total harmonic distortion (THD)).

[0088] Fig.11 1012 is a block diagram of example internal components of controller 1012. Fig.11 As shown in , the controller 1012 may include a reference generation circuit 1102, an interval calculation circuit 1116, and a pulse width modulation (PWM) generator circuit 1114. The controller 1012 further includes a control logic circuit 1118 to control the operation of these components, and a memory 1120 to support the operation. As described above, the controller 1012 may be part of a microcontroller (MCU), an application specific integrated circuit (ASIC), or a programmable logic circuit such as a field programmable gate array (FPGA). The memory 1220 may include volatile and / or non-volatile memory, such as a static random access memory (SRAM), a dynamic random access memory (DRAM), a flash memory, an erasable programmable read-only memory (EPROM). In the case where the controller 1012 is an MCU, each of the circuits 1102-1118 may be implemented by instructions that can be executed by the MCU, and the memory 1120 may store instructions that can be executed by the MCU. In the case where the controller 1012 is an ASIC or FPGA, each of the circuits 1102-1118 may be implemented by dedicated circuitry including logic circuits. The memory 1220 may also provide storage for input data and output data for each of the circuits.

[0089] The reference generation circuit 1102 can generate a reference current Iref The reference current may represent the AC input current signal 110 (I in (t)) and may be a target having a voltage similar to the AC input voltage signal 108 (V in ) to maintain a power factor equal to or substantially close to one. The reference current information may also be provided by an external control loop to control the power supply system 104 to provide a DC output voltage that matches the reference DC output voltage.

[0090] The reference generation circuit 1102 can generate I in various ways. ref In some examples, the reference generation circuit 1102 can receive a reference current I from the output control loop. ref,amp The reference generation circuit 1102 can also receive the measurement result 1050 and determine the normalized V according to the measurement result 1050. in (e.g., with an amplitude of 1V), and by ref,amp Multiply by the normalized V in To generate I ref In some examples, the reference generation circuit 1102 may also receive a DC output voltage signal 112 (V out ) and reference DC output voltage 1060(V out,ref ) measurement result 1040. The reference generation circuit 1102 may include a subtraction circuit for generating a difference between the DC output voltage signal 112 and the reference DC output voltage 1060, and a subtraction circuit for internally generating I based on the difference. ref,amp The reference generation circuit 1102 can then generate a proportional integral (PI) controller by ref,amp Multiply by the normalized V from the measurement 1050 in to produce the digital value 1122.

[0091] The interval calculation circuit 1116 may generate a digital value 1136 (t M ), indicating the digital value of the discharge interval 1138 (t SR ), representing the digital value 1140 of the first idle time interval (t dt1 ), and a digital value 1142 (t dt2 ),like Figure 4. The interval calculation circuit 1116 may receive the digital value 1122, the measurement result 1050, the measurement result 1040, the indication signal 1072, and the programming data 1062, and generate digital values ​​1136-1142 based on the digital value 1122, the measurement result 1050, the measurement result 1040, the indication signal 1072, and the programming data 1062. The interval calculation circuit 1116 provides the digital values ​​1136-1142 to the control logic circuit 1118. The control logic circuit 1118 may control the PWM generator circuit 1114 to generate a control signal V at the PWM output based on the digital values ​​1136-1142. G1 or V G2 .

[0092] The PWM generator circuit 1114 can generate a control signal V G1 or V G2 The PWM generator circuit 1114 may then transmit the digital value to the driver circuit ( Fig.11 The control logic circuit 1118 can control the PWM generator circuit 1114 to generate a PWM signal having a voltage value determined by t SR ,t M ,t dt1 and t dt2 Defines the timing of the control signal V G1 and V G2 sequence.

[0093] In some examples, the control logic circuit 1118 may include a state machine to control the PWM generator circuit 1114 to generate the control signal V G1 and V G2 , and controls the read and write operations to the memory 1120. The state machine may be based on a counter operation, and the count value and the respective t SR ,t M ,t dt1 and t dt2 The control logic circuit 1118 may also receive a measurement result 1050 representing the AC input voltage signal 108, determine whether the system is operating in the positive half cycle or the negative half cycle of the AC input voltage, and generate a control signal V accordingly. G1 and V G2 .

[0094] Fig. 12A Contains shown Fig.10The time domain curve 1202 shows the current flow in the inductor 306 during the charge / discharge cycle. The time domain curve 1204 shows the voltage across the switch 1008 during the charge / discharge cycle. The time domain curves 1202 and 1204 are similar to Figure 4 4. In interval t1, switch 1008 is closed and switch 1010 is open, and the current flowing through inductor 306 increases to charge inductor 306. In interval t2, switch 1008 and switch 1010 are open. In interval t3, switch 1010 is closed and switch 1008 is open while inductor 306 is discharging. In interval t4, switch 1008 and switch 1010 are open. Interval t1 may represent a charging interval t M , the interval t2 may represent the first idle time interval t dt1 , the interval t3 can represent the discharge interval t SR , and interval t4 may represent the second idle time interval t M .

[0095] Fig. 12B 1204 is an example state plane diagram showing the relationship between voltage and current in the time domain curves 1202 and 1204. The state plane diagram maps the time domain curves 1202 and 1204 to i L (v), which represents the dependence of the time domain waveform. Normalize the state dependence, i L (v)→j L (m). The normalized expression is:

[0096] V 基极 =V OUT (Equation 7)

[0097]

[0098]

[0099]

[0100]

[0101]

[0102] Θ = tω (Equation 13)

[0103]

[0104] in:

[0105] V OUT is the output voltage of the power supply system 104 .

[0106] V 基极is the base voltage selected for normalization.

[0107] L is the inductance of the inductor 306 .

[0108] C is the capacitance at the switching node 1014 .

[0109] R0 is the resonant impedance of the resonant circuit including L and C.

[0110] I 基极 is the base current chosen for normalization.

[0111] V IN is the input voltage of the power supply system 104 .

[0112] i L is the current flowing in the inductor 306 .

[0113] ω0 is the angular resonant frequency of the resonant circuit comprising L and C.

[0114] M is the normalized input voltage (relative to the output voltage V OUT Normalized).

[0115] jL is the normalized current.

[0116] θ is the angle corresponding to the time interval of the time domain curves 1202 and 1204 .

[0117] fsw is the switching frequency determined, for example, in the interval calculation circuit 1116.

[0118] F is the normalized frequency, in

[0119] Available from Fig. 12B The normalized state plane diagram of leads to the following system of equations.

[0120]

[0121]

[0122]

[0123]

[0124]

[0125]

[0126]

[0127]

[0128] Equation 15-22 contains 11 variables: J L1 , J L2 , J L3 , J L4 , θ1, θ2, θ3, θ4, M, F and J L θ1 represents Fig. 12A The interval t1 (charging interval) in the Fig. 12A The angle of the interval t2 (the first idle time interval) in Fig. 12A The angle of the interval t3 (discharge interval) in Fig. 12A The interval t4 (second idle time interval or valley resonant transition interval) in the switching cycle and the angle of the switching cycle period. The system of equations may have a unique solution, however, the equations are transcendental. In some examples, an iterative numerical method can be used to find the solution of the equation (including J L1 , J L2 , J L3 , J L4 , θ1, θ2, θ3, θ4, M, F and J L ), but such methods are computationally intensive and may not be suitable for real-time implementation. Also, iterative numerical methods may or may not provide an exact analytical solution, which reduces the accuracy of determining the interval at which ZVS is achieved.

[0129] In some examples, the controller 1012 may determine the solution to Equations 15-22 in real time based on a set of equations derived from Equations 15-22 in which θ4 is set to a specific value, so θ4 is not an unknown variable to be solved. In some examples, the controller 1012 may set θ4 to 90° (or ). Setting θ4 to 90° provides the resonant period One quarter of the valley resonance transition interval (the second idle time interval t4 or t dt2 ).

[0130]

[0131] With θ4 set to 90°, the following mathematical identities can be applied to simplify some of Equations 15-22:

[0132]

[0133] For example, Equation 18 may be simplified as shown below in Equation 25, and Equations 15-22 may be solved analytically.

[0134]

[0135] The following equations can be derived from Equations 15-22 based on Equations 23-25.

[0136] J L4 =1-M (Equation 26)

[0137] J L3 =M(Equation 27)

[0138]

[0139]

[0140]

[0141]

[0142]

[0143]

[0144]

[0145] The interval calculation circuit 1116 may be implemented in which θ4 is set to 90° or Equations 26-34 are used to determine an accurate analytical solution including the values ​​of θ1, θ2, and θ3, and the duration of the charging interval, the first idle time interval, the discharging interval, and the second idle time interval are determined based on the values ​​of θ1, θ2, θ3, and θ4. Negative current peak J L3 and J L4 (Equations 26 and 27) may depend on the ratio of the input voltage to the output voltage. In some examples, the interval calculation circuit 1116 may implement a method where θ4 is set to be different from 90° or The values ​​of Equations 15-22 are derived from different sets of equations.

[0146] Fig.13 26-34. The interval calculation circuit 1116 includes a feed forward (FF) circuit 1302, a feedback circuit 1303, a state plane solver circuit 1308, and an angle to interval conversion circuit 1310. The feedback circuit 1303 includes a compensation circuit 1304 and a state plane parameter generation circuit 1306.

[0147] The interval calculation circuit 1116 receives the digital value x REF [k], x[k], V IN 、V OUT , Tau (τ), and Ro as inputs, and from these values ​​the three input variables used to solve equations 26-34 are generated. The index "k" can represent x REFand a specific sampling time or a specific sample of x. These digital values ​​may represent the operating state of the power supply system 104 in the previous switching cycle, and the interval calculation circuit 1116 may determine the duration of the charging interval, the first idle time interval, the discharging interval, and the second idle time interval of the switching cycle after the previous switching cycle based on these digital values. Specifically, the ratio of the output voltage to the input voltage and the product of the ratio of the current reference to the output voltage and the resonant impedance (e.g. ) can be used as two of the three variables. The third variable (denoted as x[k]) is a measured value used for negative feedback to, for example, adjust the switching cycle period. The third variable can represent a measurement of the operation of the power supply system 104 during the first dead time period or the second dead time period, such as ZVD (zero voltage switching detection), as shown in the upcoming example. L 、i L1 or L2 .

[0148] Furthermore, the interval calculation circuit 1116 calculates the feed-forward value y[k]. The feed-forward value may represent the initial target state of operation of the power supply system 104, such as the target switching frequency (or switching cycle period), the target peak inductor current (I L1 ), the target peak inductor current during the discharge interval (I L2 ), target average inductor current, target charging interval duration, target discharging interval duration, etc. In some examples, the target state can be a target operating state for the power supply system 104 to achieve ZVS. The interval calculation circuit 1116 can use x[k] as negative feedback to tune the value of y[k], where y[k] is normalized by the interval calculation circuit 1116 and is related to M and J. L (Equations 11-12) are used together as input to equations 26-34. As shown in the upcoming example, the value y[k] can be tuned by a compensator.

[0149] Various measured values ​​can be used as x[k]. Table 1 below shows examples of x[k] and x used with x[k]. REF The corresponding instance of [k].

[0150] Table 1

[0151] x[k] <![CDATA[x REF [k]]]> ZVD[k] 1 <![CDATA[i L [k]]]> <![CDATA[i LREF [k]]]> <![CDATA[i L1 [k]]]> <![CDATA[i L1REF [k]]]> <![CDATA[i L2 [k]]]> <![CDATA[i L2REF [k]]]>

[0152] ZVD[k] may be a sample of the indication signal 1072 indicating whether zero voltage switching (ZVS) is detected. L [k] may be a sample of the average current flowing in the inductor 306 (average power converter current). L1[k] may be a sample of the peak current flowing in the inductor 306 during the charging interval ( Fig. 12A ). L2 [k] may be the peak current flowing in the inductor 306 during the discharge interval ( Fig. 12A ). The reference signal x associated with each x[k] REF [k] represents the desired / target value of x[k]. For example, i LREF [k] may be a target power converter current, such as a target average power converter current (target average inductor current), a desired peak charging current, or a desired peak discharging current.

[0153] An example of y[k] provided by the interval calculation circuit 1116 based on x[k] is shown below in Table 2. In various examples of the interval calculation circuit 1116, y[k] may be any one of the variables of Equations 26-34 other than x[k].

[0154] Table 2

[0155] y[k] F[k] <![CDATA[θ1[k]]]> <![CDATA[θ3[k]]]> <![CDATA[i L [k]]]> <![CDATA[i L1 [k]]]> <![CDATA[i L2 [k]]]>

[0156] FF circuit 1302 provides y based on the input value FF [k] Feedforward value. Additional information regarding the feedforward calculation is provided with respect to specific implementations.

[0157] y FF [k] = f(v IN [k],v OUT [k],x[k],x REF [k])(Equation 35)

[0158] FF circuit 1302 converts the feedforward value y to the feedforward output FF [k] is provided to the feedforward input of the compensation circuit 1304 for generating y[k]. The compensation circuit 1304 may be based on y received at the feedback input of the compensation circuit 1304. FF [k] and the feedback components x[k] and x REF [k] provides an operating parameter signal y[k]. Additional information regarding the calculation of y[k] is provided with respect to specific implementations.

[0159] y[k]=f(y FF [k],x[k],x REF [k])(Equation 36)

[0160] Compensation circuit 1304 provides y[k] to state-plane parameter generation circuit 1306. State-plane parameter generation circuit 1306 generates normalized state-plane parameter values ​​(Equations 37-39) used to solve Equations 26-34. State-plane parameter generation circuit provides parameter values ​​to state-plane solver circuit 1308 at parameter outputs.

[0161]

[0162]

[0163]

[0164] in:

[0165] v[k] is a measured voltage, such as a converter input voltage, a converter output voltage, or a converter switching node capacitor voltage; and Y 基极 [k] is the base associated with the selected y[k]. For example, referring to Table 2, if y[k] is F[k], then Y 基极 =f0; if y[k] is θ1 or θ3, then Or if y[k] is i L 、i L1 or L2 , then Y 基极 =I 基极 .

[0166] The state plane solver circuit 1308 applies the parameter values ​​(M[k], J[k]) received from the state plane parameter generation circuit 1306 at the solver input. L [k], y norm [k]) to solve equations 26-34. According to equation (33), θ4 is set to 90°. The state plane solver circuit 1308 provides the values ​​of angles θ1, θ2, θ3, and θ4 at the solver output to the angle input of the angle to interval conversion circuit 1310.

[0167] The angle-to-interval conversion circuit 1310 determines the interval values ​​t of the charging interval, the discharging interval, the first dead time, and the second dead time based on θ1, θ2, θ3, and θ4, respectively. M ,t SR ,t dt1 and t dt2 ( Fig. 12A The angle to interval conversion circuit 1310 may determine the interval time value as:

[0168] t j [k] = Θ j [k]τ[k]j=1…4(Equation 40)

[0169] where τ[k] is the resonant time constant of the power supply system 104, as described above. The angle-to-interval conversion circuit 1310 converts t M ,t SR ,t dt1 and t dt2 An interval input is provided to control logic circuit 1118 for generating control signal 1030 and control signal 1032 .

[0170] Fig.14 To use the average inductor current (i L [k]) to determine the interval value t M ,t SR ,t dt1 and t dt2 The interval calculation circuit 1116 includes a FF switching frequency circuit 1402 (which may be Fig.13 The FF switching frequency circuit 1402 may be a part of the feed forward circuit 1302), a switching frequency compensation circuit 1404, a state plane parameter generation circuit 1406, a state plane solver circuit 1408 and an angle to interval conversion circuit 1410. Fig.13 The feedforward circuit 1302 may be part of the switching frequency compensation circuit 1404 and the state plane parameter generation circuit 1406 may be part of the feedback circuit 1303, the state plane solver circuit 1408 may be part of the state plane solver circuit 1308, and the angle to interval conversion circuit 1410 may be part of the angle to interval conversion circuit 1310. The interval calculation circuit 1116 receives the digital value I L,REF ,I L [k], V IN 、V OUT , Tau(τ) and Ro as input.

[0171] FF switching frequency circuit 1402 provides a feed-forward (FF) switching frequency value (F SW,FF [k]). The feedforward switching frequency value may represent an initial estimate of the switching frequency value, which may then be adjusted by the feedback circuit 1303. In some examples, the FF switching frequency circuit 1402 may provide F as follows SW,FF [k]:

[0172] f sw,FF [k] = f(v IN [k],v OUT [k],i L,REF [k])(Equation 41)

[0173] In some examples, the FF switching frequency circuit 1402 may generate F based on an estimate that ignores (or does not otherwise consider) the resonant transition.SW,FF [k]:

[0174]

[0175] Among them I ZVS M may be a constant value representing a negative current for ZVS where resonant transitions of the switching nodes are not present or otherwise considered.

[0176] FF switching frequency circuit 1402 changes F SW,FF [k] is provided to the switching frequency compensation circuit 1404 for generating f sw [k] The switching frequency compensation circuit 1404 can be realized by combining F SW,FF [k] and the switching cycle adjustment value T sw.ajd [k] to provide f sw [k], as follows:

[0177]

[0178] Fig.15 To generate T sw,ajd [k] is a block diagram of a compensation circuit system 1500 for the FF switching frequency circuit 1402. The compensation circuit system 1500 includes a differential circuit 1502 and a compensator circuit 1504. The differential circuit 1502 generates a signal representing i L [k] and i L,REF [k], and provides the error signal to the compensator circuit 1504. The compensator circuit 1504 may include a modulator T sw,ajd [k] to reduce i L [k] and i L,REF [k] A proportional-integral-derivative (PID) controller (or other control process) is used to calculate the difference between the two.

[0179] Return to Fig.14 , the switching frequency compensation circuit 1404 changes T sw,ajd [k] is provided to the state plane parameter generation circuit 1406 for generating state plane parameters. The state plane parameter generation circuit 1406 may generate normalized state plane parameters as follows:

[0180]

[0181]

[0182]

[0183] The state plane parameter generation circuit 1406 converts M[k], J L[k] and F[k] are provided to the state-plane solver circuit 1408. The state-plane solver circuit 1408 applies the parameter values ​​received from the state-plane parameter generation circuit 1406 to equations 47-54 to determine θ1, θ2, and θ3.

[0184] J L4 [k] = 1 - M[k] (Equation 47)

[0185] J L3 =M[k] (Equation 48)

[0186]

[0187]

[0188]

[0189]

[0190]

[0191]

[0192] As in equation (33), θ4 is set to 90° (or ). The state plane solver circuit 1408 provides the values ​​of θ1, θ2, θ3, and θ4 to the angle to interval conversion circuit 1410.

[0193] The angle-to-interval conversion circuit 1410 determines the interval values ​​t of the charging interval, the discharging interval, the first dead time, and the second dead time based on θ1, θ2, θ3, and θ4, respectively. M ,t SR ,t dt1 and t dt2 The angle-to-interval conversion circuit 1410 may determine the interval time values ​​t1, t2, t3, and t4 as:

[0194] t j [k] = Θ j [k]τ[k]j=1…4(Equation 55)

[0195] Where τ[k] is the resonant time constant of the power supply system 104 See again Fig. 12A , t1 can correspond to t M , t2 can correspond to t dt1 , t3 can correspond to t SR , and t4 can correspond to t dt2 The angle to interval conversion circuit 1410 converts t M ,t SR ,tdt1 and t dt2 Provided to the control logic circuit 1118 for generating the control signal 1030 and the control signal 1032 .

[0196] Fig.16 FIG. 1 is a block diagram of an example interval calculation circuit 1116 for tuning the switching frequency using ZVD feedback (an indication of a ZVS state or a non-ZVS state). The interval calculation circuit 1116 includes a FF switching frequency circuit 1602, a switching frequency compensation circuit 1604, a state plane parameter generation circuit 1406, a state plane solver circuit 1408, and an angle to interval conversion circuit 1410. The interval calculation circuit 1116 receives a digital value I RLEF , ZVD M [k], V IN 、V OUT , Tau(τ) and Ro as input. ZVD M is the feedback of ZVD when the main switch (eg, switch 1008) is switched ( Fig.10 Indication signal 1072 in).

[0197] FF switching frequency circuit 1602 provides a FF switching frequency value (f SW,FF [k]). In some examples, the FF switching frequency circuit 1602 can generate f according to Equation 42. SW,FF [k].

[0198] FF switching frequency circuit 1602 changes F SW,FF [k] is provided to the switching frequency compensation circuit 1604 for generating f sw [k] The switching frequency compensation circuit 1604 can provide f according to equation 43 sw [k].

[0199] Fig.17 To generate T sw,ajd [k] is a block diagram of compensation circuit system 1700 for FF switching frequency circuit 1602. Compensation circuit system 1700 includes differential circuit 1702 and compensator circuit 1704. Differential circuit 1702 generates a signal representing ZVD M The difference between [k] and the logical "1" value (or ZVD M [k] is a logic 1 value, or has an asserted state), and provides the error signal to the compensator circuit 1704. The compensator circuit 1704 may include a ZVD based M [k] is a logical 1 value and T sw,ajd [k] modulates a proportional-integral-derivative (PID) controller (or other control process) to a higher or lower value. For example, if ZVD M[k] is a logic 1 value, then the compensator circuit 1704 can reduce T sw,ajd [k], and if ZVD M [k] is not a logic 1 value, then the compensator circuit can increase T sw,ajd [k].

[0200] Return to Fig.16 , the switching frequency compensation circuit 1404 changes T sw,ajd [k] is provided to the state plane parameter generation circuit 1406 for generating the state plane parameters. The state plane parameter generation circuit 1406 may generate the normalized state plane parameters according to equations 44-46.

[0201] The state plane parameter generation circuit 1406 converts M[k], J L [k] and F[k] are provided to the state-plane solver circuit 1408. The state-plane solver circuit 1408 applies the parameter values ​​received from the state-plane parameter generation circuit 1406 to equations 47-54 to determine θ1, θ2, θ3, and θ4.

[0202] As in equation (33), θ4 is set to 90° in equation 53. The state plane solver circuit 1408 provides the values ​​of θ1, θ2, θ3, and θ4 to the angle to interval conversion circuit 1410.

[0203] The angle-to-interval conversion circuit 1410 determines the time values ​​t of the charging interval, the discharging interval, the first dead time, and the second dead time based on θ1, θ2, θ3, and θ4, respectively. M ,t SR ,t dt1 and t dt2 The angle-to-interval conversion circuit 1410 may determine the time value according to equation 40. The angle-to-interval conversion circuit 1410 converts t M ,t SR ,t dt1 and t dt2 Provided to the control logic circuit 1118 for generating the control signal 1030 and the control signal 1032 .

[0204] Fig.18 To determine the switching cycle adjustment value T in the compensator circuit 1704 sw,ajd [k] Flowchart of the method. In block 1802, the compensator circuit 1704 determines ZVD M [k] Whether it is a logical 1 value (ZVD M [k] is asserted). In response to asserting ZVD in block 1802 M [k], then in block 1804, the compensator circuit 1704 may be configured relative to T sw,ajd The previous value of [k] is decreased by Tsw,ajd The value of [k].

[0205] T sw，ajd [k] = T sw，ajd [k-1]-k ZVD , ΔT sw (Equation 56)

[0206] in:

[0207] ΔT sw is a varying value (e.g., 0.5, 1, etc.); and

[0208] k ZVD is the gain factor.

[0209] In response to ZVD not being asserted in block 1802 M [k], then in block 1806), the compensator circuit 1704 may be configured relative to T sw,ajd The previous value of [k] is increased by T sw,ajd The value of [k].

[0210] T sw，ajd [k] = T sw，ajd [k-1]+k ZVD ΔT sw (Equation 57)

[0211] Fig.19 is the gain factor (k ZVD ) is a flow chart of a method for adjusting. In block 1902, the compensator circuit 1704 determines ZVD M The current value (ZVD M [k]) Is it related to ZVD M The previous value (ZVD M [k-1]) are the same (e.g., are the gain factors the same in consecutive switching cycles). If ZVD M If the current value of is the same as the previous value, then in block 1904, the compensator circuit 1704 may increase the current value applied to change T sw,ajd The gain factor (k) of the value of [k] ZVD ).

[0212] k ZVD =kx VD +Δk ZVD,1 (Equation 58)

[0213] Where Δk ZVD,1 is the change value applied to increase the gain.

[0214] If ZVD in block 1902 MIf the current value of is different from the previous value, then in block 1906, the compensator circuit 1704 may reduce the applied value to change T sw,ajd The gain factor (k) of the value of [k] ZVD ).

[0215] k ZVD =k ZVD -Δk ZVD,2 (Equation 59)

[0216] Where Δk ZVD,2 is the change value applied to reduce the gain.

[0217] Fig. 20 is a block diagram of a compensation circuit system 2000 that can be used to generate a frequency for calculating f in the FF switching frequency circuit 1602 or the FF switching frequency circuit 1402. SW,FF [k]I ZVS [k] By using the compensation circuit system 2000, I ZvS [k] to account for the resonant transition, rather than a constant as in Equation 42. Compensation circuit system 2000 includes differential circuit 2002 and compensator circuit 2004. Differential circuit 2002 generates a previous value (f SW [k-1]) and its feedforward component (f SW,FF [k-1]), which may represent the additional time provided to account for the resonant transition of the switching node. The compensator circuit 2004 may include a modulation I based on the error signal. ZVS [k] Proportional Integral Derivative (PID) controller (or other control process).

[0218] The FF switching frequency circuit 1402 or the FF switching frequency circuit 1602 may be based on the adjusted I ZVS_adj [k] produces f SW,FF [k] is:

[0219]

[0220] Fig.21 To determine t based on the average inductor current and the peak charging current M ,t SR ,t dt1 and t dt2 14. The interval calculation circuit 1116 includes a FF peak current circuit 2102, a peak current compensation module 2104, a state plane parameter generation circuit 2106, a state plane solver circuit 2108, and an angle to interval conversion circuit 1410. The interval calculation circuit 1116 receives a digital value I LREF ,IL [k], V IN 、V OUT , Tau(τ) and Ro as input.

[0221] FF peak current circuit 2102 provides a FF peak current value (i L1,FF [k]).

[0222] i L1，FF [k] = f(v IN [k],v OUT [k],i LREF [k]) (Equation 61)

[0223] In some examples, the FF peak current circuit 2102 can generate i according to Equation 62 L1,FF [k].

[0224] i L1，FF [k] = 2i L，REF [k] (Equation 62)

[0225] FF peak current circuit 2102 will i L1，FF [k] is provided to the peak current compensation module 2104 for generating i L1 [k] The switching frequency compensation circuit 1604 can provide i L1 [k] is:

[0226] i L1 [k] = i L1，COMP [k]+i L1，FF [k] (Equation 63)

[0227] Fig. 22 is used to generate i used in equation 63 L1,COMP [k] is a block diagram of a compensation circuit system 2200 for the FF peak current circuit 2102. The compensation circuit system 2200 includes a differential circuit 2202 and a compensator circuit 2204. The differential circuit 2202 generates a signal representing an average current (i L [k]) and the reference current (i L,REF [k]), and provides the error signal to the compensator circuit 2204. The compensator circuit 2204 may include a circuit that modulates i based on the error signal. L1，COMP [k] to reduce i L [k] and i L,REF [k] A proportional-integral-derivative (PID) controller (or other control process) is used to calculate the difference between the two.

[0228] Return to Fig.21 , the peak current compensation module 2104 will i L1[k] is provided to the state plane parameter generation circuit 2106 for generating state plane parameters. The state plane parameter generation circuit 2106 can generate normalized state plane parameters M[k] and J according to equations 44 and 45. L [k]. The state plane parameter generation circuit 2106 can generate a normalized state plane parameter J L1 [k] is:

[0229]

[0230] The state plane parameter generation circuit 1406 converts M[k], J L [k] and J L1 [k] is provided to the state-plane solver circuit 2108. The state-plane solver circuit 2108 applies the parameter values ​​received from the state-plane parameter generation circuit 2106 to solve equations 65-72 for θ1, θ2, θ3, and θ4.

[0231] J L4 =1-M (Equation 65)

[0232] J L3 =M (Equation 66)

[0233]

[0234]

[0235]

[0236]

[0237]

[0238]

[0239] The state plane solver circuit 2108 provides the values ​​of θ1, θ2, θ3, and θ4 to the angle-to-interval conversion circuit 1410. The angle-to-interval conversion circuit 1410 determines the time values ​​t of the charging interval, the discharging interval, the first dead time, and the second dead time based on θ1, θ2, θ3, and θ4, respectively. M ,t SR ,t dt1 and t dt2 The angle-to-interval conversion circuit 1410 may determine the time value according to equation 40. The angle-to-interval conversion circuit 1410 converts t M ,t SR ,t dt1 and t dt2 Provided to the control logic circuit 1118 for generating the control signal 1030 and the control signal 1032 .

[0240] In with Fig.21 In another example of the interval calculation circuit 1116 similar to the interval calculation circuit shown in FIG. 1 , the FF peak current circuit 2102 provides the FF peak current value (i ) based on the input value according to equation 73. L2,FF [k]).

[0241] i L2，FF [k] = f(v IN [k],v OUT [k],i L，REF [k]) (Equation 73)

[0242] In some examples, the FF peak current circuit 2102 can generate i according to Equation 74. L2,FF [k].

[0243] i L2 , FF [k] = 2i L，REF [k] (Equation 74)

[0244] FF peak current circuit 2102 will i L2,FF [k] is provided to the peak current compensation module 2104 for generating i L2 [k]. The peak current compensation module 2104 can provide i L2 [k] is:

[0245] i L2 [k] = i L2.COMP [k]+i L2，FF [k] (Equation 75)

[0246] where i L2,COMP [k] provided by the compensation circuit system 2200 (rather than Fig. 22 As shown in L1,COMP [k]).

[0247] Fig.23 is used to generate the i used in equation 75 L2,COMP [k] is a block diagram of a compensation circuit system 2300 for the FF peak current circuit 2102. The compensation circuit system 2300 includes a differential circuit 2302 and a compensator circuit 2304. The differential circuit 2302 generates a signal representing an average current (i L [k]) and the reference current (i L,REF [k]), and provides the error signal to the compensator circuit 2304. The compensator circuit 2304 may include a circuit that modulates i based on the error signal. L2,COMP [k] to reduce i L [k] and i L,REF[k] A proportional-integral-derivative (PID) controller (or other control process) is used to calculate the difference between the two.

[0248] The peak current compensation module 2104 converts i L2 [k] is provided to the state plane parameter generation circuit 2106 for generating state plane parameters. The state plane parameter generation circuit 2106 can generate normalized state plane parameters M[k] and J according to equations 44 and 45. L [k]. The state plane parameter generation circuit 2106 can generate a normalized state plane parameter J L2 [k] is:

[0249]

[0250] The state plane parameter generation circuit 2106 converts M[k], J L [k] and J L1 [k] is provided to the state-plane solver circuit 2108. The state-plane solver circuit 2108 applies the parameter values ​​received from the state-plane parameter generation circuit 2106 to solve equations 77-84 for θ1, θ2, θ3, and θ4.

[0251] J L4 =1-M (Equation 77)

[0252] J L3 =M (Equation 78)

[0253]

[0254]

[0255]

[0256]

[0257]

[0258]

[0259] The state plane solver circuit 2108 provides the values ​​of θ1, θ2, θ3, and θ4 to the angle-to-interval conversion circuit 1410. The angle-to-interval conversion circuit 1410 determines the time values ​​t of the charging interval, the discharging interval, the first dead time, and the second dead time based on θ1, θ2, θ3, and θ4, respectively. M ,t SR ,t dt1 and t dt2 The angle-to-interval conversion circuit 1410 may determine the time value according to equation 40. The angle-to-interval conversion circuit 1410 converts t M ,tSR ,t dt1 and t dt2 Provided to the control logic circuit 1118 for generating the control signal 1030 and the control signal 1032 .

[0260] Fig.24 2 is a block diagram of an example time constant estimator circuit 2402 for use with the interval calculation circuit 1116. If the resonant time constant τ[k] provided to the interval calculation circuit 116 does not reflect the actual resonant time constant of the power supply system 104 (e.g., the values ​​of L and C provided to the controller 1012 are inaccurate), then the interval t calculated based on τ[k] M ,t SR ,t dt1 and t dt2 The duration value of may not be equal to the interval for achieving ZVS. Therefore, the time constant estimator circuit 2402 may be based on the detection (or non-detection) of ZVD when the switch 1010 is switched (ZVD R [k])( Fig.10 The value of the resonant time constant τ[k] is adjusted by the indication signal 1072 in the input signal, and the interval calculation circuit 1116 can use the adjusted resonant time constant to determine t M ,t SR ,t dt1 and t dt2 The compensator 2404 may adjust the value of τ[k] to achieve ZVS of the power converter rectifier switch (e.g., switch 1010). The compensator 2404 may include a PID controller or other control circuit to adjust τ[k]. The time constant estimator circuit 2402 may provide the adjusted power converter resonant period τ[k] to the interval calculation circuit 1116 for calculating the time value t M ,t SR ,t dt1 and t dt2 .

[0261] Fig.25An example of the internal components of the transition measurement circuit 1070 and its operation is shown. The transition measurement circuit 1070 may include a voltage measurement circuit 2502, a threshold generator circuit 2504, a comparator 2506, and a processing circuit 2508. The voltage measurement circuit 2502 may be coupled to a main switch 2510 of the power converter to measure a voltage difference across the main switch 1010, wherein the main switch may be one of the switches 1008 or 1010. In the case where the main switch 2510 includes a FET, the voltage measurement circuit 2502 may provide a voltage signal 2512 based on a voltage difference between current terminals 2514 and 2516 (e.g., a drain terminal and a source terminal) of the FET, wherein the current terminal 2514 may be coupled to ground, and the current terminal 2516 may be coupled to a switching node (e.g., the switching node 1014) and to an inductor (e.g., the inductor 306). In some examples, the voltage measurement circuit 2502 may include a differential amplifier to generate the voltage signal 2512. Also, the threshold generator circuit 2504 may output a threshold voltage 2522 representing a zero voltage difference across the main switch 2510. The threshold voltage 2522 may be the voltage signal 2512 provided by the voltage measurement circuit 2502 when the voltage difference is zero. The comparator 2506 may compare the voltage signal 2512 with the threshold voltage 2522 to provide a decision signal 2530 indicating whether the voltage difference across the main switch 2510 is zero. Fig.25 In the example of , if the voltage difference between the current terminals 2514 and 2516 is equal to zero, then the comparator 2506 can provide a logic one for the decision signal 2530, and provide a logic zero for the decision signal 2530 if the voltage difference between the current terminals 2514 and 2516 exceeds zero.

[0262] Furthermore, the processing circuit 2508 may be coupled to a control terminal 2532 (eg, a gate terminal) of the main switch 2510 and the output of the comparator 2506. The processing circuit 2508 may be configured to generate a control signal based on the decision signal 2530 and a control signal 2534 (eg, V G1 or V G2 ) generates an indication signal 1072 to indicate whether the main switch 2510 switches state after the switching node 1014 is completely transferred to the ground, thereby achieving zero voltage difference and ZVS across the main switch 2510. In some examples, the processing circuit 2508 may include a pulse generator circuit.

[0263] Fig.26 and Fig. 27 2512, 2534, 2530 and the indication signal 1072 are plotted against time, wherein the indication signal 1072 is represented by Fig.25 An example transition measurement circuit 1070 is provided. Fig.262604, 2606 and 2608 of the signals 2512, 2534, 2530 and the corresponding graphs 2602, 2604, 2606 and 2608 of the indicator signal 1072 are shown when the indicator signal 1072 indicates ZVS, and Fig. 27 Corresponding curves 2702 , 2704 , 2706 , and 2708 of signals 2512 , 2534 , 2530 , and 1072 are shown in the case where the indicator signal 1072 indicates non-ZVS.

[0264] See also Fig.26 , at time T0, the voltage difference across the main switch 2510 drops below zero, and the signal 2512 also drops below the threshold voltage 2522. This causes the decision signal 2530 to be asserted at time T0. The asserted decision signal 2530 may enable the pulse generator of the transition measurement circuit 1070. At time T1 after T0, the control signal 2534 changes from the second state to the first state to enable the main switch 2510. The rising edge of the control signal 2534 at T1 may trigger the pulse generator to generate a pulse for the indication signal 1072, and the pulse may indicate a ZVS condition because the main switch 2510 changes state when the voltage across the main switch is zero.

[0265] See also Fig. 27 , at time T3, the control signal 2534 changes from the second state to the first state to enable the main switch 2510 when the voltage difference across the main switch 2510 is still above zero and the signal 2512 is above the threshold voltage 2522. This causes the decision signal 2530 to be de-asserted, which can disable the pulse generator of the transition measurement circuit 1070. Therefore, the indication signal 1072 can be de-asserted, which can indicate a non-ZVS condition because the main switch 2510 changes state when the voltage across the main switch is above zero.

[0266] Fig.28 28. An example state diagram 2850 is shown when the state machine in the control logic circuit 1118 operates in the switching mode. The control logic circuit 1118 can reset the counter and start in the state 2842 at the beginning of the switching mode. In some examples, when in the state 2842, the control logic circuit 1118 can receive the counters respectively representing t M ,t SR ,t dt1 and t dt2 After receiving the digital value, the control logic circuit 1118 can continue to the charging state 2852 via the edge 2844.

[0267] When in the charging state 2852, the control logic circuit 1118 may first reset the counter and control the PWM generator circuit 1114 to set the control signal of the main switch (e.g., switch 1008) in a first state to enable the main switch and set the control signal of the SR switch (e.g., switch 1010) in a second state to disable the SR switch. The counter may increment with respect to time, and when the counter value is below the value representing t M When the digital value 1136 of is reached, as indicated by the transition edge 2854 , the control logic circuit 1118 / PWM generator circuit 1114 may remain in the charging state.

[0268] When the counter value matches the digital value 1124 / 1136, the control logic circuit 1118 may reset the counter and transition to the first dead time state 2862 via transition edge 2864. In the first dead time state 2862, the PWM generator circuit 1114 sets V G1 and V G2 The counter may be incremented relative to time after the reset is released, and when the counter value is lower than the first idle time interval t dt1 When the digital value 1140 of the duration is reached, as indicated by the transition edge 2866, the control logic circuit 1118 / PWM generator circuit 1114 may remain in the first dead time state.

[0269] When the counter value matches the digital value 1140, the control logic circuit 1118 may reset the counter and transition to the discharge state 2872 via the transition edge 2874. In the discharge state 2872, the PWM generator circuit 1114 may set the control signal of the main switch (e.g., switch 1008) to the second state to disable the main switch, and set the control signal of the SR switch (e.g., switch 1010) to the first state to enable the SR switch. The counter may be incremented with respect to time after the reset is released, and when the counter value is below the discharge interval t SR When the digital value 1128 of the duration is reached, as indicated by the transition edge 2876, the control logic circuit 1118 / PWM generator circuit 1114 may remain in the discharge state.

[0270] When the counter value matches the digital value 1128, the control logic circuit 1118 may reset the counter and transition to the second dead time state 2882 via the transition edge 2884. In the second dead time state 2882, the PWM generator circuit 1114 controls the signal V G1 and V G2 Both are set to low. The counter may be incremented with respect to time after reset is released and when the counter value is below the second idle time interval t dt2When the counter value reaches the digital value 1142 of the duration of , the PWM generator circuit 1114 may remain in the first dead time state as indicated by the transition edge 2886. When the counter value reaches the digital value 1142, the control logic circuit 1118 may enter the state 2892, where the switching mode ends via the edge 2894.

[0271] Fig.29 An embodiment of a hardware system 2900 is shown that can be used as described above. For example, the hardware system 2900 can implement the functionality of the controller 1012. Fig.29 A generalized description of various components is provided, any or all of which may be utilized as appropriate.

[0272] Hardware system 2900 is shown as including hardware elements that may be electrically coupled via bus 2905 (or may otherwise communicate as appropriate). The hardware elements may include a processing unit 2910, which may include, but is not limited to, one or more general purpose processors, one or more special purpose processors (e.g., digital signal processing (DSP) chips, graphics acceleration processors, application specific integrated circuits (ASICs), etc.), and / or other processing structures or components. For example, processing unit 2910 may perform calculations according to equations 26-84 as described above. Fig.29 As shown in , some embodiments may have separate digital signal processors (DSPs) 2920 depending on the desired functionality. For example, DSP 2920 may process the measurement results 1040 of the output voltage and the measurement results 1050 of the input voltage of the power converter circuit 122. In some examples, hardware system 2900 may include one or more input devices 2970, which may include devices related to a user interface (e.g., a touch screen, a touch pad, a microphone, a button, a dial, a switch, etc.). Similarly, one or more output devices 2915 may involve interaction with a user (e.g., via a display, a light emitting diode (LED), a speaker). Hardware system 2900 may further include a sensor 2940. For example, sensor 2940 may include various components of transition measurement circuit 1070.

[0273] The hardware system 2900 may further include and / or communicate with memory 2960. The memory 2960 may include, but is not limited to, local and / or network accessible memory, disk drives, drive arrays, optical storage devices, solid-state storage devices (e.g., random access memory (RAM) and / or read-only memory (ROM), which may be programmable, flash-updatable), etc. These storage devices may be configured to implement any suitable data storage, including, but not limited to, various file systems, database structures, etc.

[0274] In some examples, memory 2960 may provide Fig.11 Memory 1120 to provide storage space to support calculations according to equations 26-84. Memory 2960 may also include software components ( Fig.29 2900 (not shown), including an operating system, device drivers, executable libraries, and / or other code, such as one or more applications, which may include computer programs provided by various embodiments, and / or may be designed to implement methods provided by other embodiments, and / or configure systems provided by other embodiments, as described herein. By way of example only, one or more programs described with respect to the operations described herein may be implemented as code and / or instructions in memory 2960 that can be executed by hardware system 2900 (and / or processing unit 2910 or DSP 2920 within hardware system 2900). In one aspect, then, these codes and / or instructions may be used to configure and / or adapt a general purpose computer (or other device) to perform one or more operations described herein.

[0275] Fig.30 Contains circuits for controlling power converters, such as Figure 3 , 6 10 and 10. The method 3000 may be performed by the controller 1012, for example. The power converter circuit may include an inductor (e.g., inductor 306), a first switch (e.g., one of switches 308, 602 / 604, or 1008), and a second switch (e.g., one of switches 310, 604 / 602, or 1010). The inductor and the first and second switches may be coupled at a switching node (e.g., one of nodes 314, 614, or 1014), and the first and second switches may be coupled in series between a positive output and a negative output of the power converter. The first switch may act as a main switch, and the second switch may act as an SR switch.

[0276] The power converter may be part of a power supply system (e.g., power supply system 104), which further includes a first measurement circuit (e.g., one of measurement circuits 352, 662, or 1052) coupled to the positive input and the negative input to measure the input voltage to the power converter, and a second measurement circuit (e.g., one of measurement circuits 342, 652, or 1042) to measure the output voltage of the power converter. The power supply system 104 may also include a third measurement circuit (e.g., transition measurement circuit 1070) to measure the state of the transition of the inductor current or the switching node voltage. An example of the transition measurement circuit 1070 is shown in FIG. Fig.25 In some examples, the third measurement circuit can be coupled to the first current terminal and the second current terminal of one of the first or second switches, such as Fig.25In some examples, the third measurement circuit can be coupled to the first current terminal and the second current terminal of both the first switch or the second switch. In some examples, the third measurement circuit can be coupled to the switching node.

[0277] In step 3002, the controller receives a first measurement result of an input voltage of a power converter from a first measurement circuit, the first measurement result may be part of a power converter state. The first measurement result may include a digital value generated by an ADC of the first measurement circuit, and the first measurement result may indicate the magnitude and polarity of the input voltage of the current switching cycle.

[0278] In step 3004, the controller receives a second measurement result of the output voltage of the power converter from the second measurement circuit, which second measurement result may be part of the power converter state. The second measurement result may include a digital value generated by an ADC of the second measurement circuit, and the second measurement result may indicate the magnitude of the output voltage.

[0279] In step 3006, the controller receives a third measurement signal from a third measurement circuit coupled to a current terminal of a first switch of the power converter, a current terminal of a second switch of the power converter, and / or an inductor of the power converter. The third measurement signal may indicate a voltage across the first switch when the first switch changes state. The indication signal may indicate that the voltage is properly transitioned to a target voltage (e.g., ground voltage, output voltage) such that when the main switch changes state, the voltage difference across the main switch (first switch or second switch) is zero or below zero, and whether ZVS is detected. In some examples, the third measurement signal may represent a current (e.g., an average current) flowing in the inductor. The detection of ZVS or non-ZVS and the average current flowing in the inductor may be part of the power converter state.

[0280] In step 3008, the controller receives a control signal indicating a predetermined power converter resonant period. In some examples, the resonant period may be calculated based on a specified inductance of the inductor and a specified capacitance at the switching node. In some examples, the resonant period may be adaptively determined based on a ZVD signal measured when a rectifier switch (e.g., switch 1010) is switched, such as Fig.24 as shown in .

[0281] In step 3010, the controller may determine a charging interval for charging the inductor in a switching cycle, a discharging interval for discharging the inductor in a switching cycle, and a first idle time interval after the charging interval and before the discharging interval based on the first measurement signal, the second measurement signal, and the third measurement signal. For example, the controller may determine the values ​​of θ1, θ2, θ3 by solving equations 26-33, equations 44-54, equations 64-72, or equations 76-84. The controller may use the values ​​of θ1, θ2, θ3 to solve equation 40 and determine t M ,t SR and t dt1 The value of .

[0282] In step 3012, the controller may determine a second idle time interval after the discharge interval and before the charge interval based on a predetermined power converter resonant period. For example, the controller may set θ4 as in Equations 33, 53, 71, or 83. The controller can use the value of θ4 to solve Equation 40 and determine t dt2 The value of .

[0283] In step 3014, the controller may provide the first drive signal and the second drive signal based on the charging interval, the discharging interval, the first idle time interval, and the second idle time interval. M ,t SR ,t dt1 and t dt2 Provided to the control logic circuit 1118. The control logic circuit 1118 can control the PWM generator circuit 1114 to generate V G1 and V G2 To control the switching of the first switch and the second switch.

[0284] During the charging interval, the controller may enable the first switch and disable the second switch to charge the inductor with the input current, and the inductor current increases to reach a peak current at the end of the charging interval. The controller may set the first control signal in a first state (e.g., the gate voltage is higher than the source voltage by a conduction threshold of the NFET of the first switch) to enable the first switch, and set the second control signal in a second state (e.g., the gate voltage is lower than the sum of the source voltage and the conduction threshold of the NFET of the second switch) to disable the second switch.

[0285] During a first idle time interval following the charging interval, the controller may deactivate both the first switch and the second switch.The controller may set both the first control signal and the second control signal in a second state to deactivate both the first switch and the second switch.

[0286] In a discharge interval after the first no-load time interval, the controller may disable the first switch and enable the second switch to discharge the inductor to provide the output current to the load, and when the discharge interval ends, the inductor current drops from the peak current to the SR disconnection current. The SR disconnection current may be zero or a negative current. The controller may set the first control signal in the second state to disable the first switch, and set the second control signal in the first state to enable the second switch.

[0287] During a second idle time interval following the discharge interval, the controller may set both the first control signal and the second control signal to a second state to disable both the first switch and the second switch.

[0288] The controller 1012 provides unified control that ensures accurate, optimal dead time for ZVS for both the main switch and the rectifier switch in a ZVS quasi-square wave (QSW) converter with precise average inductor current control. The current and voltage waveforms provided by the controller 1012 are beneficial from a hardware design and efficiency optimization perspective. Existing control techniques have limited performance due to reliance on high bandwidth current sensors, or open loop control based on approximate equations or lookup tables. Inaccuracies in control can result in poor current reference tracking, but more importantly can cause loss of ZVS in both the main device and the rectifier device, which can result in significant losses in the semiconductor device, especially in high frequency designs.

[0289] The ZVS-QSW converter is described by a system of transcendental equations. The solution can only be found using iterative numerical methods, which are not suitable for real-time implementation. The controller 1012 sets the angle of the valley resonant transition interval to 90° and uses mathematical identities to simplify and solve the system of equations analytically. This produces an exact solution to the waveform and timing of the ZVS-QSW converter, with the constraint that the valley resonant transition interval angle (θ4) is set to 90°. The calculated timing is used to generate the gate pulses.

[0290] The inputs to the controller 1012 may be the inductor current reference, the input voltage and output voltage of the converter, and the ZVD signal of the main switch. Before turning on the main switch, the dead time is kept fixed to a value corresponding to the 90° valley resonant transition interval angle (θ4). Based on an approximate estimate, the equations employ a switching frequency. The timing is calculated using the analytical solution described above, and the gate pulses are applied accordingly. The switching frequency may be adaptively adjusted based on, for example, the ZVD signal. Once the switching frequency is tuned to achieve ZVS, the average inductor current may be equal to the current reference, and the dead time calculated by the controller 1012 may correspond to the duration of the resonant transition interval.

[0291] like Figure 11-30 The controller 1012 is implemented to determine tM ,t SR ,t dt1 and t dt2 The algorithm / method of can have various benefits. Specifically, the controller 1012 can determine an exact analytical solution without using an iterative numerical method, which can reduce the calculation of t M ,t SR ,t dt1 and t dt2 , and allows these interval values ​​to be calculated and updated in real time. Also, because an accurate analytical solution is determined, the no-load time interval and switching frequency of ZVS can be determined more accurately, which can reduce hard switching and third quadrant conduction losses, thereby improving (or even maximizing) the performance of the semiconductor switching device. The controller 1012 provides ZVS at all operating points that result in low losses. Since during light load conditions t M ,t SR ,t dt1 and t dt2 The controller 1012 can also provide low total harmonic distortion (THD) by reducing the delay of calculation / adjustment of the controller 1012. For example, the THD can be about 9% under no-load conditions and less than 4% under full-load conditions. The controller 1012 can provide excellent transient response and no-load operation (e.g., low dissipation without burst or discontinuous mode operation).

[0292] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0293] Additionally, in this description, the statement “based on” means “based, at least in part, on.” Thus, if X is based on Y, then X may vary with Y and any number of other factors.

[0294] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0295] As used herein, the terms "terminal", "node", "interconnection", "pin" and "lead" are used interchangeably. Unless otherwise specified, these terms are generally used to refer to the interconnection or the termination of a device element, circuit element, integrated circuit, device or other electronic device or semiconductor component.

[0296] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, e.g., by an end user and / or a third party, during or after manufacture.

[0297] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the remaining circuitry. For example, field effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs—e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain extension mode devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0298] In the claims reference may be made to the control input of a transistor and to its current terminals. In the case of a FET, the control input is the gate and the current terminals are the drain and the source. In the case of a BJT, the control input is the base and the current terminals are the collector and the emitter.

[0299] References to a FET being "on" herein mean that there is a conduction channel of the FET and drain current can flow through the FET. References to a FET being "off" herein mean that there is no conduction channel, so drain current does not flow through the FET. However, turning a FET "off" allows current to flow through the body diode of the transistor.

[0300] The circuits described herein may be reconfigured to include additional or different components to provide functionality at least partially similar to functionality available before component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0301] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as external to the integrated circuit may be included in the integrated circuit, and / or some features shown as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0302] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "substantially" or "substantially" preceding a parameter means within + / -10% of the parameter, or if the parameter is zero, then within a reasonable value range of about zero.

[0303] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. A device comprising: A controller circuit having first and second control inputs and first and second control outputs, wherein the controller circuit is configured to: receiving at said first control input a measurement signal indicative of a state of the power converter; receiving at said second control input a control signal indicative of a resonant period of the power converter; determining, based on the power converter state and the power converter resonant period: a charging interval of a switching cycle; a first idle time interval of the switching cycle; a discharging interval of the switching cycle; and a second idle time interval of the switching cycle, wherein the first idle time interval is after the charging interval, the discharging interval is after the first idle time interval, and the second idle time interval is after the discharging interval; Within the switching cycle, a first drive signal is provided at the first control output and a second drive signal is provided at the second control output, wherein: During the charging interval, the first drive signal has a first state and the second drive signal has a second state; During the first idle time interval and the second idle time interval, the first drive signal and the second drive signal have the second state; and During the discharge interval, the first drive signal has the second state, and the second drive signal has the first state.

2. The apparatus according to claim 1, wherein: The first control output is coupled to a first power converter control terminal; the second control output is coupled to a second power converter control terminal; and The first state is opposite to the second state.

3. The apparatus of claim 1 , wherein the power converter state indicates at least one of: a zero voltage switching (ZVS) state of a previous switching cycle, a non-ZVS state of the previous switching cycle, an average power converter current of the previous switching cycle, a peak current within the charging interval of the previous switching cycle, a peak current within the discharging interval of the previous switching cycle, a power converter input voltage of the previous switching cycle, or a power converter output voltage of the previous switching cycle. 4 . The apparatus of claim 3 , wherein the controller circuit is configured to determine the second dead time interval based on one quarter of a resonant period of the power converter.

5. The apparatus of claim 4, wherein the measurement signal is a first measurement signal, the controller circuit has a third control input and a fourth control input, and the controller circuit is configured to: receiving at the third control input a second measurement signal representative of the power converter input voltage; receiving at the fourth control input a third measurement signal representative of the power converter output voltage; and The charging interval, the discharging interval, and the first idle time interval are determined based on the power converter input voltage and the power converter output voltage.

6. The apparatus of claim 5 , wherein the controller circuit has a fifth control input and a sixth control input, and the controller circuit is configured to: receiving at said fifth control input a reference signal representative of a target power converter current; receiving at said sixth control input a second control signal representative of a resonant impedance of the power converter; determining an operating parameter signal based on the first measurement signal, the second measurement signal, the third measurement signal and the reference signal; as well as The charging interval, the first dead time interval, and the discharging interval are determined based on the operating parameter signal, the second dead time interval, and the power converter resonant impedance.

7. The apparatus of claim 6, wherein the operating parameter signal indicates a period of the switching cycle, and the controller circuit is configured to: determining a feedforward component of the cycle based on the power converter input voltage and the power converter output voltage; determining a feedback component of the cycle based on the power converter state; and The charging interval, the first dead time interval, and the discharging interval are determined based on the period, the second dead time interval, the power converter resonant period, and the power converter resonant impedance.

8. The apparatus of claim 7, wherein the controller circuit is configured to: In response to the power converter state indicating the ZVS state, reducing the feedback component; and In response to the power converter state indicating the non-ZVS state, the feedback component is increased.

9. The apparatus of claim 8, wherein the controller circuit is configured to: determining a gain factor based on whether the power converter state indicates the ZVS state in consecutive switching cycles; and The feedback component is increased or decreased based on the gain factor.

10. The apparatus of claim 7, wherein the target power converter current represents a target average power converter current, and the controller circuit is configured to: In response to the power converter status indicating an average inductor current being higher than the target average power converter current, reducing the feedback component; and In response to the power converter status indicating that the average inductor current is below the target average power converter current, the feedback component is increased.

11. The apparatus of claim 6, wherein the operating parameter signal indicates a peak current within the charging interval, and the controller circuit is configured to: determining a feed-forward component of the peak current based on the power converter input voltage and the power converter output voltage; determining a feedback component of the peak current based on the power converter state; and The charging interval, the first dead time interval, and the discharging interval are determined based on the peak current, the second dead time interval, the power converter resonant period, and the power converter resonant impedance.

12. The apparatus of claim 6, wherein the controller circuit comprises: a feedforward circuit having a first feedforward input coupled to the first control input, a second feedforward input coupled to the second control input, and a third feedforward input coupled to the fifth control input and a feedforward output; a feedback circuit having a first feedback input coupled to the first control input, a second feedback input coupled to the second control input, a third feedback input coupled to the third control input, a fourth feedback input coupled to the fourth control input, a fifth feedback input coupled to the fifth control input, and a sixth feedback input coupled to the sixth control input and a parameter output; a state plane solver circuit having a solver input coupled to the parameter output and first, second, third and fourth solver outputs; an angle-to-interval conversion circuit having first, second, third and fourth angle inputs and first, second, third and fourth interval outputs, the first angle input being coupled to the first solver output, the second angle input being coupled to the second solver output, the third angle input being coupled to the third solver output, and the fourth angle input being coupled to the fourth solver output; as well as A pulse width modulation (PWM) generator circuit having a first interval input, a second interval input, a third interval input and a fourth interval input and a first PWM output and a second PWM output, wherein the first interval input is coupled to the first interval output, the second interval input is coupled to the second interval output, the third interval input is coupled to the third interval output, the fourth interval input is coupled to the fourth interval output, the first PWM output is coupled to the first control output, and the second PWM output is coupled to the second control output.

13. The apparatus of claim 12, wherein: the feedforward circuit being configured to provide a feedforward component of the operating parameter signal at the feedforward output based on the power converter input voltage and the power converter output voltage and the reference signal; The feedback circuit is configured to: determining a feedback component of the operating parameter signal based on the power converter state and the reference signal; providing the operating parameter signal based on combining the feedforward component and the feedback component; as well as providing a state plane parameter at the parameter output based on the power converter input voltage and the power converter output voltage, the reference signal, the operating parameter signal having the feedforward component and the feedback component, and at least one of the power converter resonant period or the power converter resonant impedance; The state plane solver circuit is configured to: determining a first angle, a second angle, and a third angle based on the state plane parameter and a fourth angle equal to 90 degrees; as well as providing the first angle, the second angle, the third angle, and the fourth angle at respective first solver outputs, second solver outputs, third solver outputs, and fourth solver outputs; and The angle-to-interval conversion circuit is configured to: providing the charging interval at the first interval output based on the first angle and the power converter resonant period; providing the first dead time interval at the second interval output based on the second angle and the power converter resonant period; as well as providing the discharge interval at the third interval output based on the third angle and the power converter resonant period; as well as The second dead time interval is provided at the fourth interval output based on the fourth angle and the power converter resonant period.

14. The apparatus of claim 3, wherein the ZVS state and the non-ZVS state are power converter main switches.

15. The apparatus of claim 3, wherein the power converter state indicates one of: the ZVS state of a power converter rectifier switch, or the non-ZVS state of the power converter rectifier switch; and Wherein the controller circuit is configured to: determining an adjusted power converter resonant period based on the power converter resonant period and the power converter state; and The second dead time interval of the switching cycle is determined based on the adjusted power converter resonant period.

16. A method comprising: receiving a measurement signal indicative of a state of the power converter; receiving a control signal indicative of a resonant period of the power converter; determining, based on the power converter state and the power converter resonant period: a charging interval of a switching cycle; a first idle time interval of the switching cycle; a discharging interval of the switching cycle; and a second idle time interval of the switching cycle, wherein the first idle time interval is after the charging interval, the discharging interval is after the first idle time interval, and the second idle time interval is after the discharging interval; as well as A first drive signal and a second drive signal are provided within the switching cycle, wherein: During the charging interval, the first drive signal has a first state and the second drive signal has a second state; During the first idle time interval and the second idle time interval, the first drive signal and the second drive signal have the second state; and During the discharge interval, the first drive signal has the second state, and the second drive signal has the first state.

17. The method of claim 16, wherein the power converter state indicates at least one of: a zero voltage switching (ZVS) state of a previous switching cycle, a non-ZVS state of the previous switching cycle, an average power converter current of the previous switching cycle, a peak current within the charging interval of the previous switching cycle, a peak current within the discharging interval of the previous switching cycle, a power converter input voltage of the previous switching cycle, or a power converter output voltage of the previous switching cycle.

18. The method of claim 16, further comprising determining the second dead time interval based on one quarter of a resonant period of the power converter.

19. The method of claim 16, wherein: The control signal is a first control signal; and The method further comprises: receiving a reference signal representative of a target power converter current; receiving a second control signal indicative of a resonant impedance of the power converter; determining an operating parameter signal based on the power converter state, the power converter input voltage, the power converter output voltage, and the reference signal; and The charging interval, the first dead time interval, and the discharging interval are determined based on the operating parameter signal, the second dead time interval, and the power converter resonant impedance.

20. An apparatus comprising: a power converter having a positive input, a negative input, a positive output, and a negative output, the power converter comprising a first switch, a second switch, and an inductor, the first switch and the second switch being coupled in series between the positive output and the negative output, and a first current terminal of the first switch being coupled to the second switch and a second current terminal of the inductor; as well as A controller circuit configured to: receiving a measurement signal indicative of a state of the power converter; receiving a control signal indicative of a resonant period of the power converter; determining, based on the state of the power converter and a resonant period of the power converter: a charging interval of a switching cycle of the power converter; a first idle time interval of the switching cycle; a discharging interval of the switching cycle; and a second idle time interval of the switching cycle, wherein the first idle time interval is after the charging interval, the discharging interval is after the first idle time interval, and the second idle time interval is after the discharging interval; In the switching cycle, a first drive signal is provided to the first switch, and a second drive signal is provided to the second switch, wherein: During the charging interval, the first drive signal has a first state and the second drive signal has a second state; During the first idle time interval and the second idle time interval, the first drive signal and the second drive signal have the second state; and During the discharge interval, the first drive signal has the second state, and the second drive signal has the first state.

21. The apparatus of claim 20, wherein the controller circuit is configured to determine the second dead time interval based on one quarter of the resonant period of the power converter.

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