Phase tracking and correction architecture

Abstract

Aspects described herein include apparatuses and methods for phase tracking and correction using sampling. One aspect includes a wireless communication apparatus having: an analog 1-bit sampler configured to sample a phase-locked loop (PLL) output signal using a PLL reference clock to generate 1-bit samples; and a digital phase calculation and control circuit configured to receive the 1-bit sample from the analog 1-bit sampler and to apply a phase correction to the PLL based on a phase error derived from the 1-bit sample.

Description

Technical Field

[0001] The present disclosure relates generally to electronics and wireless communications. For example, aspects of the present disclosure relate to tracking and correction of low frequency phase drift. Background Art

[0002] Wireless communication devices and technologies are becoming increasingly common. Wireless communication devices typically send and receive communication signals. Communication signals are typically processed by a variety of different components and circuits. In some modern communication systems, phased array antennas are used to improve system operations with improved link budgets, system capacity, beamforming, multiple-input multiple-output (MIMO) communications, and other such system operations. Supporting one or more such systems can involve complex system design choices, as well as managing complex interactions between device elements and signals. Summary of the invention

[0003] Various implementations of systems, methods, and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the desirable attributes described herein.Without limiting the scope of the appended claims, certain prominent features are described herein.

[0004] Systems, devices, methods, computer-readable media, and circuits for phase tracking and correction are disclosed. According to at least one example, a communication device for phase detection and correction includes: an analog 1-bit sampler configured to sample a phase-locked loop (PLL) output signal using a PLL reference clock to generate a 1-bit sample; and a digital phase calculation and control circuit configured to receive the 1-bit sample from the analog 1-bit sampler and apply a phase correction to the PLL based on a phase error. The device may include a phase detection, correction, and tracking system, including: an analog 1-bit sampler and a digital phase calculation and control circuit:

[0005] Some such aspects operate in the following situations: sampling a PLL output signal before a local oscillator (LO) signal generator circuit within a transmit signal path of a wireless communication device. Some such aspects operate in the following situations: sampling the PLL output signal in a path between a voltage controlled oscillator and the LO signal generator circuit. Some such aspects operate in the following situations: sampling the PLL output signal from a portion of a receive path between a receive PLL circuit and a local oscillator (LO) signal generator circuit.

[0006] Some such aspects operate in the following circumstances: an analog 1-bit sampler includes: a signal buffer; a T-switch circuit; a voltage comparator having an input coupled to the signal buffer via the T-switch circuit; and a PLL reference clock buffer for a PLL reference clock, the PLL reference clock buffer being coupled to the T-switch circuit, wherein the PLL reference clock buffer is configured to: control the T-switch circuit to hold a sample from a PLL output signal at the input via the signal buffer at each cycle of the PLL reference clock.

[0007] Some such aspects operate where the reference clock buffer is further used to control timing of a 1-bit output of the voltage comparator while the sample is held at the input of the voltage comparator.

[0008] Some such aspects also include: a delay element coupled in a path for controlling the timing of the 1-bit output of the voltage comparator. Some such aspects also include: a signal buffer; a voltage comparator having an input coupled to the signal buffer; and a PLL reference clock buffer for the PLL reference clock, wherein the voltage comparator is coupled to the PLL reference clock buffer to use the PLL reference clock from the PLL reference clock buffer to clock the 1-bit sampling of the signal from the signal buffer.

[0009] Some such aspects also include: a digital phase calculation and control circuit having: a first digital phase accumulator; a second digital phase accumulator; and a sampling input connected to the output of the analog 1-bit sampler.

[0010] Some such aspects operate in the following situations: when the value from the second digital phase accumulator is in a first dead band associated with a 50% duty cycle state of the first digital phase accumulator, the single phase value is calculated using the value from the first digital phase accumulator; and when the value from the first digital phase accumulator is in a second dead band associated with a 50% duty cycle state of the second digital phase accumulator, the single phase value is calculated using the value from the second digital phase accumulator.

[0011] Some such aspects also operate where the digital phase calculation and control circuit includes circuitry configured to: compare the phase error to an error target; and generate a control signal associated with the phase error when the phase error is greater than the error target. Some such aspects also include a delta sigma modulation circuit, wherein an output of the digital phase calculation and control circuit is coupled to the delta sigma modulator circuit to provide the control signal to the delta sigma modulation circuit.

[0012] Some such aspects also include: a digital divider circuit having: a first input coupled to the PLL output; a second input coupled to the digital phase calculation and control circuit; and an output configured to provide a feedback clock to the input of the PLL, wherein, in response to a phase drift error being greater than a threshold value, the feedback clock is selected at least in part by dividing a PLL output signal received from the PLL based on a control signal from the digital phase calculation and control circuit.

[0013] According to at least one other example, a communication device includes: a signal path; an analog sampler coupled to the signal path at a detection position and configured to generate a 1-bit phase sample of the signal on the signal path; a phase sampling circuit having an input coupled to the signal path at a detection position and an output indicating an average phase value over a calculation cycle; and determining a phase error value based on the average phase value of the calculation cycle of each of a plurality of phase accumulators, comparing the phase error value with a threshold value, and generating a control signal when the phase error value is greater than the threshold value.

[0014] According to at least one other example, a method includes determining a phase error threshold; calculating a phase error value using multiple 1-bit samples from an analog sampler and a digital circuit, wherein the analog sampler and the digital circuit are coupled to an output of a phase-locked loop (PLL) circuit and a reference clock network of a wireless communication device; and applying a phase correction to the PLL circuit based on the output of the digital circuit.

[0015] In another example, a communication device for phase tracking and correction is provided, which includes: a storage device (e.g., a memory configured to store data such as virtual content data, one or more images, etc.) and one or more processors (e.g., implemented in a circuit) coupled to the memory and configured to execute instructions, and in combination with various components (e.g., a network interface, a display, an output device, etc.) so that the communication device performs the following operations: determining a phase error threshold; calculating a phase error value using multiple 1-bit samples from an analog sampler and a digital circuit, wherein the analog sampler and the digital circuit are coupled to an output of a phase-locked loop (PLL) circuit and a reference clock network of a wireless communication device; and applying phase correction to the PLL circuit based on the output of the digital circuit.

[0016] In another example, a communication apparatus for phase tracking and correction includes means for sampling a phase locked loop output signal and means for applying a phase correction based on a phase error generated from the sampling.

[0017] The foregoing and other features and embodiments will become more fully apparent after reference to the following description, claims and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In the drawings, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations such as "102a" or "102b", these letter character designations may distinguish between two similar parts or elements appearing in the same drawing. When it is intended that a reference numeral encompass all parts having the same reference numeral in all figures, the letter character designation of the reference numeral may be omitted.

[0019] Figure 1 is a diagram illustrating a wireless communication system for communicating with wireless devices that can be implemented in accordance with aspects described herein.

[0020] Figure 2A is a block diagram illustrating portions of a wireless device in which aspects of the present disclosure may be implemented.

[0021] Figure 2B is a block diagram illustrating portions of a wireless device in which aspects of the present disclosure may be implemented.

[0022] Figure 3 is a block diagram illustrating portions of a wireless device in which aspects of the present disclosure may be implemented.

[0023] Figure 4 is a block diagram illustrating portions of a wireless device in which aspects of the present disclosure may be implemented including a sampler and a 1-bit comparator.

[0024] Figure 5A is a diagram showing an analog sampler including switches and a 1-bit comparator that may be used in accordance with aspects of the present disclosure.

[0025] Figure 5B is a diagram illustrating an analog sampler and a 1-bit comparator that do not include switches and that may be used in accordance with aspects of the present disclosure.

[0026] Figure 6 is a block diagram illustrating aspects of a digital phase calculation and control circuit in accordance with aspects of the present disclosure.

[0027] Figure 7 is a block diagram illustrating portions of a wireless device in which aspects of the present disclosure may be implemented.

[0028] Figure 8 is a flow chart illustrating aspects of phase error measurement and correction according to some implementations of the present disclosure.

[0029] Fig. 9is a state diagram illustrating aspects of phase error measurement and correction according to some implementations of the present disclosure.

[0030] Fig.10 is a flow chart illustrating a method according to aspects of the present disclosure.

[0031] Fig.11 is a functional block diagram of an apparatus including 1-bit sampling with digital phase calculation and control according to some aspects of the present disclosure.

[0032] Fig.12 is a diagram illustrating an environment including electronic devices and base stations that may be used with aspects of the present disclosure.

[0033] Fig.13 is a diagram of an electronic device that can be used with aspects of the present disclosure. DETAILED DESCRIPTION

[0034] The specific embodiments described below in conjunction with the drawings are intended as descriptions of exemplary implementations, and are not intended to represent the only implementations in which the present invention can be practiced. The term "exemplary" as used herein means "used as an example, instance, or illustration," and should not be interpreted as being preferred or advantageous over other exemplary implementations. The specific embodiments include specific details for providing a thorough understanding of the exemplary implementations. In some instances, some devices are shown in block diagram form. The same reference numerals may be used to identify common elements of the drawings in the following drawings.

[0035] The development of wireless communication infrastructure (e.g., 3rd Generation Partnership Project (3GPP) fifth generation (5G) millimeter wave (mmW) systems) involves the use of antenna arrays having tens, hundreds, or thousands of elements. For example, a 5G New Radio (NR) massive multiple-input multiple-output (MIMO) antenna array having such elements may include a design that uses phase alignment between different elements. Temperature variations, device aging, and other such considerations may cause low-frequency phase drifts (e.g., drifts that occur over time frames consistent with natural temperature variations, device aging, and other such variations, as compared to high-frequency phase spikes caused by power supply problems or other such transient or "spiky" phase noise issues). Such phase alignment between elements may include, for example, phase alignment between separate transmit or receive chains coupled to respective antennas and / or between different transceivers or chips, such as in a system where multiple transceivers or chips are coupled to various antenna arrays or spliced ​​together to control transmit and / or receive operations in a system having a large number of antennas.

[0036] Aspects described herein include an analog sampler combined with a phase calculation and control system to correct such phase drift. In an illustrative aspect, a signal between a phase-locked loop (PLL) and a local oscillator (LO) signal generator is sampled using an analog circuit that quantizes the sampled signal by 1 bit. A digital circuit is used to track the phase, and the phase is monitored at predefined intervals. A phase range is used in monitoring, and when the phase is out of range, a phase correction is applied by adjusting the phase via a digital circuit. The various aspects described herein provide improved device performance with less than 1 degree phase accuracy in some implementations, while providing a reconfigurable system that tracks low-frequency phase drift and can avoid conflicts in low-frequency phase correction that may be caused by transient or spike phase noise sources.

[0037] Further details regarding various aspects described herein are provided with respect to the following figures.

[0038] Figure 1 1 is a diagram showing a wireless device 110 communicating with a wireless communication system 120. According to aspects described herein, the wireless device may include a transceiver including an architecture for tracking and correcting phase according to various aspects described herein. In addition, as described herein, a base station, a GNodeB, or other such devices described herein may include a MIMO communication element having a transmit and receive chain for multiple channels or channel beamforming. The examples herein may use phase tracking and correction of the center PLL frequency for LO generation to distribute a constant signal to different MIMO channels and / or chips to maintain performance. The wireless communication system 120 may be a long term evolution (LTE) system, a code division multiple access (CDMA) system, a global mobile communication (GSM) system, a wireless local area network (WLAN) system, a 5G NR (new radio) system, or some other wireless system. The CDMA system may implement wideband CDMA (WCDMA), CDMA 1X, Evolution Data Optimization (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. The communication elements of the wireless device 110 for implementing mmW and non-mmW communications according to any such communication standards may be supported by various designs of transceivers using chained signal routing. For simplicity, Figure 1 A wireless communication system 120 is shown that includes two base stations 130 and 132 and one system controller 140. In general, a wireless communication system may include any number of base stations and any set of network entities.

[0039] The wireless device 110 may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. The wireless device 110 may be a cellular phone, a smart phone, a tablet computer, or other such mobile device (e.g., a device integrated with a display screen). Other examples of the wireless device 110 include a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smart book, a netbook, a tablet computer, a cordless phone, a medical device, a device configured to connect to one or more other devices (e.g., via the Internet of Things), a wireless local loop (WLL) station, a Bluetooth device, a car or automotive device, etc. The wireless device 110 may communicate with the wireless communication system 120. The wireless device 110 may also receive signals from a broadcast station (e.g., a broadcast station 134) and / or signals from a satellite (e.g., a satellite 150 in one or more global navigation satellite systems (GNSS); in other examples, the wireless device 110 may be configured to transmit to a satellite). The wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA IX, EVDO, TD-SCDMA, GSM, 802.11, 5G, etc.

[0040] The wireless communication system 120 may also include a wireless device 160. In an exemplary embodiment, the wireless device 160 may be a wireless access point, or another wireless communication device that includes or includes a portion of a wireless local area network (WLAN). In an exemplary embodiment, the wireless device 110 may be configured as a customer premises equipment (CPE) that may communicate with a base station 130 and another wireless device 110 or other device in the wireless communication system 120. In some embodiments, the CPE may be configured to communicate with the wireless device 160 using WAN signaling and to interface with the base station 130 based on such communication, rather than the wireless device 160 communicating directly with the base station 130. In an exemplary embodiment where the wireless device 160 is configured to communicate using WLAN signaling, the WLAN signal may include a WiFi or other communication signal.

[0041] Figure 2A is a block diagram illustrating a wireless device 200 in which aspects of the present disclosure may be implemented. For example, the wireless device 200 may be Figure 1 1 or 160, etc. The described circuits may be circuits that support mmW communications or other such communications using a large array of antenna elements configured to receive signals via chain routing (e.g., rather than splitter-based routing, but in other examples, splitter-based routing may be used). In some examples, the wireless device 200 (or any device described and / or shown below) may be Figure 1 Examples of any device shown in .

[0042] Figure 2A An example of a transceiver 220 having a transmitter 230 and a receiver 250 is shown. In general, the conditioning of the signals in the transmitter 230 and the receiver 250 may be performed by one or more stages of amplifiers, filters, upconverters, downconverters, etc. These circuit blocks may be associated with Figure 2A The configuration shown in is arranged differently. In addition, Figure 2A Other circuit blocks not shown in the figure may also be used to condition the signals in transmitter 230 and receiver 250. Unless otherwise specified, Figure 2A Any signal in or any other diagram in the accompanying drawings may be a single-ended signal or a differential signal. Figure 2A Some circuit blocks in the circuit can also be omitted.

[0043] exist Figure 2A In the example shown, the wireless device 200 generally includes a transceiver 220 and a data processor 210. The data processor 210 may include a processor 296 operably coupled to a memory 298. The memory 298 may be configured to store data and program codes, and may generally include analog and / or digital processing components. The data processor 210 or a portion thereof may be implemented as a modem. The transceiver 220 includes a transmitter 230 and a receiver 250 that support bidirectional communication. Generally, the wireless device 200 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or a portion of the transceiver 220 may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed signal ICs, etc.

[0044] A transmitter or receiver can be implemented using a super-heterodyne architecture or a direct conversion architecture. In a super-heterodyne architecture, the signal is frequency converted between radio frequency (RF) and baseband in multiple stages, e.g., for a receiver, from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal is frequency converted between RF and baseband in one stage. Super-heterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Figure 2A In the example shown, transmitter 230 and receiver 250 are implemented using a direct conversion architecture.

[0045] In the transmit path, the data processor 210 processes the data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to the transmitter 230. In an exemplary embodiment, the data processor 210 includes digital-to-analog converters (DACs) 214a and 214b for converting the digital signals generated by the data processor 210 into I and Q analog output signals, such as I and Q output currents, for further processing. In other embodiments, the DACs 214a and 214b are included in the transceiver 220, and the data processor 210 digitally provides data to the transceiver 220 (e.g., for I and Q).

[0046] In the transmitter 230, baseband (e.g., low-pass) filters 232a and 232b filter the I and Q analog transmit signals, respectively, to remove the undesired images caused by the previous digital-to-analog conversion. Amplifiers (Amp) 234a and 234b amplify the signals from the baseband filters 232a and 232b, respectively, and provide I and Q baseband signals. An up-converter 240 having up-converting mixers 241a and 241b up-converts the I and Q baseband signals with the I and Q transmit (TX) local oscillator (LO) signals from the TX LO signal generator 290, and provides an up-converted signal. Filter 242 filters the up-converted signal to remove the undesired images caused by the up-conversion and the noise in the receiving band. Power amplifier 244 amplifies the signal from filter 242 to obtain the desired output power level, and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 246 and transmitted via antenna 248. Although the examples discussed herein utilize I and Q signals, those skilled in the art will appreciate that the components of a transceiver may be configured to utilize polar modulation.

[0047] In the receive path, antenna 248 receives the communication signal and provides a received RF signal, which is routed through a duplexer or switch 246 and provided to a low noise amplifier (LNA) 252. Switch 246 is designed to operate with a specific RX to TX duplexer frequency separation so that the RX signal is isolated from the TX signal, but other devices and / or methods that accommodate both TX and RX signals may be used. The received RF signal is amplified by LNA 252 and filtered by filter 254 to obtain the desired RF input signal. Down-conversion mixers 261a and 261b in down-converter 260 mix the output of filter 254 with the I and Q receive (RX) LO signals (i.e., LO_I and LO_Q) from RXLO signal generator 280 to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers 262a and 262b and further filtered by baseband (e.g., low pass) filters 264a and 264b to obtain I and Q analog input signals that are provided to the data processor 210. In the exemplary embodiment shown, the data processor 210 includes analog-to-digital converters (ADCs) 216a and 216b for converting the analog input signals into digital signals that are further processed by the data processor 210. In some embodiments, the ADCs 216a and 216b are included in the transceiver 220 and provide data digitally to the data processor 210.

[0048] exist Figure 2A 2 , TX LO signal generator 290 generates I and Q TX LO signals for up-conversion, while RX LO signal generator 280 generates I or Q RX LO signals for down-conversion. Each LO signal is a periodic signal having a specific base frequency. Phase-locked loop (PLL) 292 receives timing information from data processor 210 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from LO signal generator 290. Similarly, PLL 282 receives timing information from data processor 210 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from LO signal generator 280.

[0049] In an exemplary embodiment, RX PLL 282, TX PLL 292, RX LO signal generator 280, and TX LO signal generator 290 may alternatively be combined into a single LO generator circuit 295, which may include a common or shared LO signal generator circuit to provide the TX LO signal and the RX LO signal. Alternatively, separate LO generator circuits may be used to generate the TX LO signal and the RX LO signal.

[0050] Certain components of the transceiver 220 are Figure 2A200 are functionally illustrated in FIG. 200 , and the configurations illustrated therein may or may not represent physical device configurations in certain implementations. For example, as described above, transceiver 220 may be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed signal ICs, etc. In some embodiments, transceiver 220 is implemented on a substrate or board such as a printed circuit board (PCB) having various modules, chips, and / or components. For example, power amplifier 244, filter 242, and switch 246 may be implemented in separate modules or as discrete components (and, in some examples, multiple power amplifiers, LNAs, and / or other associated circuits may be distributed across multiple chips), while the remaining components shown in transceiver 220 may be implemented in a single transceiver chip.

[0051] The power amplifier 244 may include one or more stages including, for example, a driver stage, a power amplifier stage, or other components, which may be configured to amplify communication signals at one or more frequencies, in one or more frequency bands, and at one or more power levels. Depending on various factors, the power amplifier 244 may be configured to operate using one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and may be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.

[0052] In an exemplary embodiment in a superheterodyne architecture, the power amplifier 244 and LNA 252 (and in some examples the filters 242 and / or 254) may be implemented separately from other components in the transmitter 230 and the receiver 250, and may be implemented on a millimeter wave integrated circuit. Although the wireless device 200 describes one example of a device, it will be apparent that the aspects described herein may be implemented in other architectures (e.g., a superheterodyne architecture), and that the phase detection, correction, and tracking of the described subsampling architecture is not limited to Figure 2A .

[0053] Figure 2B is a block diagram illustrating portions of a wireless device in which aspects of the present disclosure may be implemented. Figure 2B Shown with Figure 2AThe same wireless device 200, showing a signal path 299 for a signal susceptible to low frequency phase drift. Signal path 299 begins at the phase locked loop output of the TX PLL 292, which is passed to the TX LO signal generator 290 to generate an LO signal. Although there is a feedback loop between the TX PLL 292 and the TX LO signal generator 290, such a loop does not compensate for low frequency phase drift, which can affect system performance, particularly in large MIMO systems where phase synchronization is required between channels (e.g., as implemented in base stations such as base stations 130, 132, 1204, etc.), and where performance can be affected by phase drift as described above. The phase of the signal along signal path 299 can be affected by temperature-based phase drift or other low frequency phase drift, and when such phase drift from low frequency sources is not compensated when the signal is propagated to the elements of the massive MIMO array, performance degradation can result. Although for simplicity, Figure 2A and Figure 2B A simple device structure is shown, but a similar structure can be used to support a MIMO antenna array with a large number of antenna elements. In such a system, a central PLL and LO signal generator can be used with the implementation described herein to provide a stable signal with limited phase drift to the different elements of the MIMO array. Such a centralized PLL and LO operation can be applied to both the transmit chain and the receive chain in the MIMO system. Figure 3 Additional details of such low frequency phase drift within the device are described.

[0054] Furthermore, although various descriptions and examples herein are given in the Figure 2B 299 in the transmitter 230 shown, but the receiver 250 is similarly affected by low frequency phase drift, and it will be apparent that similar corresponding architectures for receive signal paths can be used to compensate for phase drift as described for transmit signal paths such as signal path 299. In one example aspect, the architecture described herein can be used to sample a signal between a TX PLL 292 and a TX LO signal generator 290 (e.g., the output of the TX PLL 292 before being modified by the TX LO signal generator 290). Similarly, in some aspects, corresponding architecture implementations can be used to sample and process a signal output from the RX PLL 282 before input to the RX LO signal generator 280.

[0055] Figure 3is a block diagram illustrating a portion of a TX PLL 300 (eg, similar to TX PLL 292) including phase sampling and control circuitry. Portions of TX PLL 300 may introduce low frequency (eg, temperature-based) phase drift into the transmit chain. Figure 3 The TX PLL 300 may be used in a wireless device in which aspects of the present disclosure may be implemented as shown. Figure 3 The block diagram of the TX PLL includes a digital to time converter (DTC) 302, a phase frequency detector (PFD) 304, a charge pump (CP) 306, a filter 308, a voltage controlled oscillator (VCO) 310, a VCO buffer 312, buffers 314 and 316, a phase sampling circuit 318, a digital phase calculation and control circuit 320 (or circuits), and a digital divider (digitaldivider) (NDIV) 322. The VCO 310 may include low frequency, intermediate frequency, and high frequency VCOs, each with a separate buffer, and the buffer 314 may output a signal to both the LO generator (e.g., the TX LO signal generator 290) and the digital phase calculation and control circuit 320 discussed below. The buffer 316 provides the PLL signal to the phase sampling circuit 318. In the following Figure 5A An example of a phase sampling circuit is provided in . Phase sampling circuit 318 provides a sampling signal to digital phase calculation and control circuit 320. Digital phase calculation and control circuit 320 then controls NDIV 322, which provides a phase feedback clock Fv to DTC 302, which also receives a reference clock Fr.

[0056] Within TX PLL 300, DTC 302, PFD 304, VCO buffer 312, and NDIV 322 may all specifically introduce significant (e.g., temperature-based) phase drift as operating conditions of a wireless device including TX PLL 300 change. Similarly, CP 306 leakage may also introduce (e.g., temperature-based) phase drift depending on device operating conditions. Figure 3 TX PLL 300 is shown including phase drift compensation circuitry in the form of phase sampling circuitry 318 and digital phase calculation and control circuitry 320. In various implementations, phase sampling circuitry 318, or other implementations of phase samplers in accordance with aspects described herein, may sample anywhere in the signal path between a PLL and a corresponding LO signal generator (e.g., TX PLL 292 and TX LO signal generator 290 or RX PLL 282 and RX LO signal generator 280) and provide the sampled signal to a digital feedback circuit.

[0057] Figure 4is a block diagram illustrating portions of a wireless device 400 in which aspects of the present disclosure, including a sampler and a 1-bit comparator, may be implemented. Figure 4 An architecture for phase drift tracking and compensation in accordance with various aspects described herein is shown in the form of a VCO phase circuit 420 that includes an analog sampler and 1-bit comparator 422 and a digital control circuit 424. As described above, in various implementations, the VCO phase circuit 420 can be implemented in a signal path (e.g., signal path 299) anywhere between a PLL and a corresponding LO signal generator. The LO signal generator can be configured to generate I and Q signals, as described above, or can be configured to generate additional phases or reduce (e.g., divide) the frequency of a signal output from the PLL, etc. In addition to the VCO phase circuit 420, Figure 4 The wireless device 400 also includes a phase frequency detector 402, a charge pump 404, a loop and / or low pass filter 406, a VCO 408, a buffer 410, a PLL output 490, a programmable divider 440 and a delta sigma modulation circuit 430.

[0058] The VCO phase circuit 420 operates as a phase detection, correction, and tracking system having an analog portion (e.g., a sampler and 1-bit comparator 422) and a digital portion (e.g., a digital control circuit 424). The implementations described herein can perform simple 1-bit quantization of a sampled PLL signal acquired from any point in the path between the PLL and the LO generator using a sampler and 1-bit comparator 422 as described above. The digital control circuit 424 can then be used to calculate the LO phase, monitor the phase (e.g., at predefined intervals), and apply a one-time phase correction when the digital control circuit 424 determines that the phase is out of range at a phase calculation cycle.

[0059] In some embodiments, the digital control circuit 424 can be configured to correct the entire phase error in a one-time phase correction, or can be configured for limited phase correction. By periodically performing measurements with associated individual phase corrections, the VCO phase circuit 420 can compensate for low-frequency phase drifts, such as drifts due to temperature changes, while avoiding high-frequency phase shifts, such as phase shifts due to power supply spikes or other such transient phase interruptions. The digital control circuit 424 can provide highly accurate adjustments as well as reconfiguration options and possibilities for integration with other digital control systems. In some implementations, the accuracy of phase tracking for such low-frequency phase drifts can be within one degree or less. In other implementations, other accuracies can be implemented in the design based on the performance preferences of a given design.

[0060] like Figure 3 and Figure 4 As shown, the input of the sampler is displayed at the output of the VCO buffer (e.g., buffer 410 or 312 for corresponding VCO 408 and 310). In some implementations, the input signal for the sampler comes from the output of such a buffer. In some implementations, the input signal for the sampler comes from any position in the signal path between the PLL and the LO generator circuit. In other implementations, phase drift can be detected from any position in the path affected by the frequency signal (e.g., any position in path 299) via a detector tap. In any implementation, the phase detected at any position in the path is then used to perform phase calculations, and correction is applied at the corresponding PLL when the phase is out of range. The phase can be corrected by adjusting the divider (e.g., divider 440), by adjusting the phase using deltasigma modulation via the DSM circuit 430, or in any other way.

[0061] Figure 5A is a diagram showing an analog sampler and 1-bit comparator 500A including switches that can be used according to aspects of the present disclosure. In some implementations, the analog sampler and 1-bit comparator 500A can be used as Figure 4 The analog sampler and 1-bit comparator 422 or used as a phase sampling circuit 318. The analog sampler and 1-bit comparator 500A includes a reference clock input 504 (e.g., a PLL clock signal such as a reference clock Fr), a signal input 502 (e.g., from a tap point in a path, such as a path between a PLL and an LO signal generator, or from a tap of path 299 as described above), corresponding buffers 510 and 520 for buffering signals, a switch 530 (which may be referred to as a T switch in some embodiments as described below), a delay path 522 (e.g., in a path for coupling the output of the buffer 520 to a comparator 540 for timing control of a signal at a sampler output 550), a comparator 540, and a sampler output 550. In other examples, one or both of the buffers 510, 520 are omitted.

[0062] Buffer 510 can isolate the analog sampler and 1-bit comparator 500A from the signal path being sampled to avoid degraded signals on the signal path. Reference buffer 520 can similarly provide isolation from the clock, as well as improve the slew-rate of the clock transition to improve the measurement. The clock signal from the reference clock input 504 is used with the T switch 530 and the comparator 540. When the T switch 530 is closed (e.g., during the "on" state), the T switch 530 provides tracking of the input signal from the signal input 502, and when the T switch 530 is open (e.g., during the "off" state), the voltage is maintained at the comparator 540 input. The delayed clock signal from the delay path 522 is used to trigger the comparator 540 voltage comparison after each edge of the reference clock to generate an output 1-bit quantization as a 1 or 0 signal at the sampler output 550. The delay path 522 can allow the signal to stabilize after the T switch 530 is switched between the on and off states.

[0063] In some implementations, reference clock input 504 receives a PLL clock input, which may be a clock at, for example, approximately 153 megahertz (MHz), 300 (MHz), or another such reference frequency. Figure 5A The aspect shown in FIG. 5 shows a T switch 530 including a path between a buffer 510 and a comparator 540 as the top of the T, and a connection to a reference clock input 504 (e.g., between a buffer 520 and a delay 522) as the base of the T, which provides a signal for controlling the switching of the T switch 530. In other implementations, other switch structures or structures may be used to control the input signal to the comparator 540. In some implementations, for example, gate control may be used to control the signal at the input of the comparator 540.

[0064] Figure 5B is a diagram showing an analog sampler and a 1-bit comparator 500B without switches that can be used according to aspects of the present disclosure. Figure 5A In the implementation of the switch described in the embodiment of the present invention, the comparator is used to compare the input signals so that a decision can be made based on the amplitude of the two input signals at the time when the sampling clock activates the comparison. The 1-bit output from the comparator is then used for device operation. The analog sampler and 1-bit comparator 500B accepts the following Figure 5AThe sampled signal shown in FIG. 5 is a sampled signal, but the comparison and sampling are simply performed without using a switch to track and hold the sampled signal (e.g., when the switch is open, the signal is held at the comparator input by the operation of the T switch). Instead, the comparator 540 simply compares the signal directly at the time the clock signal from the buffer 520 arrives, and outputs a 1-bit quantized value without tracking and holding from the T switch. The digital control process of the sampler output 550 without the T switch remains unchanged.

[0065] Figure 6 is a block diagram illustrating aspects of a digital phase calculation and control circuit 600 (or circuit system) according to aspects of the present disclosure. The digital phase calculation and control circuit 600 may be similar to Figure 3 The digital phase calculation and control circuit 320 and Figure 4 The digital control circuit 424. The digital phase calculation and control circuit 600 receives a 1-bit quantized input from the sampling circuit at input 601 (e.g., the output 550 from the analog sampler and the 1-bit comparator 500A or 500B). The circuit of the two digital phase accumulators 602 and 604 receives a reference clock (e.g., a reference clock input, such as a reference clock Fr) provided to the sampling circuit. The accumulators 602 and 604 may also receive other inputs. Each digital phase accumulator 602 and 604 is used with samples from the sampling circuit to calculate the phase, as described below. However, as described below, when the input signal duty cycle is not 50%, each individual detection calculation may have a detection "dead zone". The calculation associated with such a dead zone cannot correctly reflect the information used for the detection calculation, and in the dead zone, the phase and phase error are determined without relying on the calculation. By using two digital phase accumulators with different initial phases, the detection dead zone is eliminated when performing calculations to determine the phase over a large number of clock cycles. Both digital phase accumulators will not have a dead band at the same time, and therefore, when a dead band occurs in one of the two accumulators, the calculations associated with the dead band may be discarded or otherwise ignored.

[0066] The use of two digital phase accumulators 602 and 604 may also be considered as follows. The phase calculation of the digital phase calculation and control circuit 600 may correct errors caused by non-50% duty cycle. In the example shown, the digital calculation and control circuit 600 runs two calculations in parallel. Each calculation may have a detection dead zone when the duty cycle is not 50%. By switching between the two calculations, the dead zone may be avoided and the calculated phase may be accurately determined. While parallel paths / calculations are beneficial in certain implementations, it will be appreciated that a single path / calculation may be used in some configurations.

[0067] The two separate calculations may be represented as follows, where a first digital phase accumulator calculation θ1 is associated with accumulator 602 and a non-50% duty cycle at 90 degrees and 270 degrees, and where a second digital phase accumulator calculation θ2 is associated with accumulator 604 and a non-50% duty cycle at 0 degrees and 180 degrees. Calculation circuit 616 performs the digital phase calculations. Figure 6 In the illustration of , "VCO" is used to represent the sampled value at input 601, DPA_I is used to represent a 1-bit quantized sinusoidal waveform having the same phase as the digital phase accumulator 602, and DPA_Q is used to represent a 1-bit quantized sinusoidal waveform having the same phase as the digitized phase accumulator 604. VCO, DPA_I, and DPA_Q are multiplied and averaged to determine the phase value. As described above, in some implementations, two phases θ1 and θ2 may be calculated. A non-50% duty cycle of the input signal may result in calculation errors associated with the duty cycle and different non-overlapping dead zones of the two different phase calculations. By switching between the two calculations based on the calculated phase value, these calculation errors caused by the non-50% duty cycle may be removed.

[0068] Alternative systems may calculate phase using digital quantization of the phase signal, which may involve both significant resources for analyzing the phase signal, and more complex computational algorithms in processing the digitized signal to determine phase drift. Such systems calculate phase and phase drift at various points in time, and are subject to significant errors and overcorrected responses when the phase measurement captures transient phase errors due to power supply noise, switching, or other such high-frequency phase effects. In contrast, the 1-bit quantization calculations described above involve a large number of simple calculations over time that can be configured for various operating conditions and device performance preferences (e.g., by selecting the number of samples used in the calculations, error thresholds, etc.).

[0069] Calculation circuit 608 sums the values ​​output from calculation circuit 606, and calculation circuits 610, 612, and 614 determine an average. Circuit 610 provides an average value from the calculation using accumulator 602, circuit 614 provides a mean value from the calculation using accumulator 604, and circuit 612 can provide a calculation cycle. Circuit 616 then uses the accumulated values ​​to calculate a phase value and a phase error. If the phase error (e.g., a phase drift value) is greater than a threshold amount, a control signal can be output (or a control signal can always be output, but the value of the control signal can be changed based on the phase error), and the control signal can be used with a delta-sigma modulation circuit to adjust the PLL phase. Such a phase adjustment is tracked by the circuit and will affect the next measurement cycle. Although the phase value and phase error are shown as from Figure 6The circuit 616 in the output, but such values ​​may not be output. For example, they may only be used by the circuit 616 internally to determine whether to output control or what value to output on the control.

[0070] The values ​​referenced above may be averaged (e.g., at circuits 610, 612, and / or 614) to provide an accurate end result. Due to variations in individual calculations, intermediate values ​​may not provide significant results. In some examples, the process may be considered to accumulate data to determine the phase as an accurate calculation of the data conversion value associated with the phase. The frequency resolution at which the averaging is performed may be programmable or selectable. For example, with a reference clock in the range of 100-200 MHz, the averaging time may be adjusted from a few microseconds to tens of milliseconds. Longer averaging times may be associated with higher accuracy, but may require longer time to complete a single calculation.

[0071] about Figure 6 The described configurations are merely examples of how phase error (e.g., phase drift) and / or control signals may be determined. Other configurations for determining phase error and / or control signals based on comparison of phase error to a threshold may be implemented. For example, a configuration for determining phase error and / or control signals based on a comparison of phase error to a threshold may be used. Figure 6 1-bit sampling of an analog sampler other than that shown in to determine digital processing of a divider (or DSM) adjustment (eg, to change a division ratio or other division value within a PLL).

[0072] Figure 7 is a block diagram illustrating portions 700 of a wireless device in which aspects of the present disclosure may be implemented. Figure 7 Shown by Figure 6 The paths of signals used by the digital phase calculation and control circuit 600. In other examples, other structures can be used. Figure 7An input 702 is shown from a detection location in the signal path as described above. The location in the signal path that is tapped (e.g., to provide an input) to generate a sub-sample of the signal phase can appear along the signal path at any location in the signal that represents the PLL phase. In some implementations, the input signal is taken at the location of the VCO output of the PLL and before the LO generator circuit. Circuit 710 is a phase sampling circuit (e.g., 318, 422, 500) that provides a one-bit sample to a digital control circuit 750 (e.g., 320, 424, 600). A reference clock (e.g., Fr) from input 704 is provided to the phase sampling circuit 710 and the digital control circuit 750. As part of the phase calculation and control, the digital control circuit 750 can take into account the delays through various buffers 720 and circuits 730. When the phase error calculated in the control circuit 750 is determined to be greater than a threshold, the digital control circuit 750 may provide a feedback (e.g., control) signal to the PLL circuit 740 (e.g., via a delta sigma modulation circuit such as DSM 430, where the PLL circuit may include components in the device 400) to correct the error.

[0073] The signal at locations A, B, C, and D is a reference clock from input 704 with various delays based on the propagation time of the reference clock as it propagates through the circuit. Line and buffer delays can be matched by system design with comparator (e.g., in 710) settling times so that the digital control circuit is timed to allow the digital phase accumulator (e.g., accumulators 602 and 604, e.g., in 750) to match the 1-bit sampled signal from the analog sampler (e.g., circuit 710, e.g., 318, 422, 500A, 500B, etc.). The clock signal and samples are then used by the digital control circuit 750, which is similar to the above description for Figure 6 The description is consistent.

[0074] Figure 8 8 is a flow chart illustrating various aspects of phase error measurement and correction according to various aspects of the present disclosure. In block 802, targets and thresholds are set. For example, a target may be to allow a phase error of 5 degrees. The target may also include a calculation period (e.g., a period for performing one calculation, as described above) based on the desired frequency of error correction and the accuracy of tracking. A smaller threshold will result in more frequent adjustments; a smaller calculation period will result in more frequent phase measurements and error calculations, but due to the above description of Figure 6The described averaging operation occurs over a shorter length of time resulting in a less accurate measurement. The phase calculation and error determination portion of the digital control circuit (e.g., circuit 616 or a similar portion of digital control circuit 750, 424, etc.) then idles as part of block 804 until a trigger occurs in block 806. The trigger in block 806 can be, for example, the expiration or completion of a sampling acquisition over a certain time period or number of cycles selected as part of the operation of block 802. The phase calculation and associated phase error value calculation are performed in block 808. During block 810, if the phase error is determined to be greater than the threshold value selected in block 802, a phase correction is applied in block 812. After completing block 812, the loop continues at block 804, where it idles until a subsequent calculation is completed (e.g., over a time period to complete one calculation, which calculation can vary based on a particular design or device setting), at which point the phase and phase error calculations are repeated.

[0075] As described above, performing such calculations using samples collected over a selectable calculation period (e.g., a configurable amount of time for performing a calculation, where a larger time increases accuracy, as described above) allows both targeted calculation accuracy and avoidance and averaging of out of phase error spikes with high frequency. For example, a power supply phase spike may cause phase error in a small number of samples during a given calculation, but due to the above-mentioned averaging, the impact on the calculated phase and phase error for the given calculation will be small. Such operation acts as a control mechanism to avoid false corrections that may be triggered by other systems due to high frequency phase error spikes captured in a system attempting to compensate for low frequency (e.g., temperature) based phase drift.

[0076] Fig. 9 is a state diagram illustrating aspects of phase error measurement and correction according to some implementations of the present disclosure. Fig. 9 The diagram of FIG. 1 depicts a digital phase calculation and control circuit (eg, circuits 320, 424, for controlling a phase shift signal) that may be used by a wireless communication device (eg, a base station or other device implementing a drift-sensitive communication system) as described herein. Figure 6 The operating state and the transition between states are implemented by the computing circuit, circuit, etc.) or other control circuits.

[0077] Block 950 represents an idle state. For example, the digital phase calculation and control circuitry may be in an idle state where registers are used to trigger phase measurements.

[0078] Block 952 shows a setup state. When a control register or control circuit of the wireless device identifies that a measurement is needed, the operating state changes from the idle state of block 950 to the setup state of block 952 to set up any measurement configurations. Operations performed in such a state may be similar to those of block 902 above, where error thresholds, targets, and other such setup details are selected. In some implementations, the setup state may include programmable selection of the number of samples per measurement, whether setting up a single measurement, tracking measurements (e.g., tracking until the phase error is below a selected threshold), or a continuous measurement state.

[0079] Block 954 represents the calibration initial state. When the setup is complete in block 952, the state may proceed to the calibration initial state, wherein any calibration settings associated with the selected programmable state in the setup operation of block 952 are executed and set in preparation for operational calculations in later states. If multiple elements are set, the calibration may cycle between the initialization and calibration run states of block 956. Block 958 represents the calibration complete state when all calibrations associated with the setup selection are complete.

[0080] Block 960 represents a check or operating state in which measurements are made. As described above, the check may include different measurements for the measurement states selected in the setup state, including continuous, tracking, or single measurement states. The operating state of block 960 may be used to perform sampling and calculations for the phase and phase error values ​​described above (e.g., with respect to Figure 6 or any other such operations described herein).

[0081] Block 962 represents the calibration initial state. The calibration initial state may check the measurement for each measurement of phase and phase error (e.g., phase and phase error measurements) against an error threshold. If the phase and phase error values ​​from the measurements made in the block 960 operation are less than the error threshold, the state returns to the idle state. Depending on the overall operation selection from the setup state, the idle state may then wait for a new setup operation (e.g., after a measurement when setting up or completing a set of tracking measurements), or if the tracking measurement state is in progress or the setup is in a continuous measurement setup state, the idle state may return to the operational state of block 960 to make additional measurements.

[0082] Block 964 represents a correction state. If the correction initialization state of block 962 identifies that the phase error is greater than the phase threshold, then a phase correction operation is implemented in the phase correction state of blocks 964, 966, and 968. Such an operation may involve generating a control code that is used by the delta sigma modulation circuit to adjust the operation of the PLL (e.g., TX PLL 292, RX PLL 282, etc.). Such feedback adjustments take time to propagate through the channel, and therefore, rather than shifting directly from the correction state of block 964 to the idle state of block 950 after the correction operation is identified as completed in the correction completion state of block 968, a delay may be imposed to allow phase adjustment feedback to be implemented before the states of the correction loop (e.g., the states of blocks 962, 964, 966, and 968) are completed and the system returns to the idle state of block 950 (e.g., via a delta sigma modulation circuit such as circuit 430). As described above, the idle state of block 950 may then implement additional delays before proceeding to additional subsequent states. Such a subsequent state may jump directly to the subsequent phase measurement check of block 960 if continuous or tracking operation is being performed from a previous setup, or may be a new setup if a control instruction for a new setup is received from the system control circuitry.

[0083] For example, a base station with 64x64 MIMO may include a large number of channels for implementing various operations and may include phase scanning, beamforming, and other such operations where the relative phase between channels is important to performance. If the channels drift over temperature, performance will degrade and MIMO performance will also be lost. Examples herein may use phase tracking and correction of the central PLL frequency for LO generation to distribute the signal to different MIMO channels to maintain performance. Different tracking systems for both the transmit and receive chains may be implemented simultaneously. Figure 8 and Fig. 9 operation, wherein separate phase tracking systems follow independent implementations for setup, control, phase tracking, and phase correction as described above.

[0084] Fig.10 1 is a flow chart describing an example of the operation of a method 1000 for operation of a device including a sampling architecture for phase detection, correction, and tracking as described herein. The blocks in the method 1000 may be performed in the order shown or out of the order shown, and in some embodiments, may be performed at least partially in parallel.

[0085] At block 1002 of method 1000, the device (or a component thereof) may perform operations for determining a computing cycle. For example, data processor 210 may make this determination based on values ​​in memory 298, for example.

[0086] At block 1004 of method 1000, the device (or a component thereof) may perform operations for determining a phase error threshold. For example, data processor 210 may make this determination based on values ​​in memory 298, for example.

[0087] At block 1006 of method 1000, the device (or a component thereof) may perform operations for calculating a phase value and an error value using a plurality of 1-bit samples from an analog sampler and a digital circuit. The calculation may be based on phase accumulation values ​​from a first phase accumulator and a second phase accumulator. The analog sampler, the first phase accumulator, and the second phase accumulator are coupled to an output of a phase-locked loop (PLL) circuit and a reference clock network (e.g., configured to provide a reference clock Fr) of a wireless communication device. Block 1006 may be performed by a device element or component such as 318, 320, 420, 422, 424, 500A, 500B, 600, and / or 700.

[0088] At block 1008 of method 1000, the device (or a component thereof) may perform operations for applying phase correction to the PLL circuit. For example, control circuit 320, 424, or 600 may apply phase correction or cause phase correction to be applied, such as by adjusting DSM 430 to change a division ratio or other division value (e.g., the value of divider 322, 440).

[0089] Fig.11 1 is a functional block diagram of an apparatus including a sampling architecture for phase detection, correction, and tracking as described herein. Apparatus 1100 includes a unit 1102 for sampling a PLL output signal using a PLL reference clock to produce a 1-bit sample. For example, unit 1102 may include 318, 320, 420, 422, 424, 500A, 500B, 600, and / or 700. Apparatus 1100 also includes a unit 1104 for applying phase correction based on a phase error generated from a 1-bit sample (e.g., a calculated 1-bit sample, which may vary as described in some aspects above). For example, unit 1104 may include 320, 322, 424, 430, 440, 600, and / or 750.

[0090] Fig.121 is a diagram illustrating an exemplary environment 1200 that includes an electronic device 1202 and a base station 1204 that each includes a transceiver (e.g., a wireless transceiver 1222 of the electronic device 1202). In the environment 1200, the electronic device 1202 communicates with the base station 1204 via a wireless communication link 1206 (wireless link 1206). In such an example, the electronic device 1202 is depicted as a smart phone. However, the electronic device 1202 can be implemented as any suitable computing or other electronic device, such as a cellular base station, a broadband router, an access point, a cellular or mobile phone, a gaming device, a navigation device, a media device, a laptop computer, a desktop computer, a tablet computer, a server, a network attached storage (NAS) device, a smart appliance, a vehicle-based communication system, an Internet of Things (IoT) device, and the like.

[0091] Base station 1204 communicates with electronic device 1202 via wireless link 1206, which may be implemented as any suitable type of wireless link. Although base station 1204 is depicted as a base station tower of a cellular radio network, base station 1204 may generally represent or be implemented as another device, such as a satellite, a cable TV headend, a terrestrial television broadcast tower, an access point, a peer device, a mesh network node, a router, a fiber optic line, another electronic device, etc. Thus, electronic device 1202 may communicate with base station 1204 or another device via a wired connection, a wireless connection, or a combination thereof.

[0092] The wireless link 1206 may include a downlink of data or control information transmitted from the base station 1204 to the electronic device 1202, and an uplink of other data or control messages transmitted from the electronic device 1202 to the base station 1204. The wireless link 1206 may be implemented using any suitable communication protocol or standard, such as, for example, 3rd Generation Partnership Project Long Term Evolution (3GPP LTE), 5G New Radio (3GPP 5GNR), IEEE 802.11, IEEE 802.16, Bluetooth TM etc.

[0093] According to the description herein, base station 1204 may include a massive MIMO communication system for transmitting, receiving, and beamforming signals associated with multiple channels of wireless link 1206, or for multiple wireless links with multiple electronic devices 1202. Examples herein may use phase tracking and correction of a central PLL frequency for LO generation (e.g., in TX PLL 292 or between TX PLL 292 and TX LO signal generator 290) to distribute a constant signal to different MIMO channels to maintain performance.

[0094] The electronic device 1202 includes a processor 1208 and a computer-readable storage medium 1210 (CRM 1210). The processor 1208 may include any type of processor, such as an application processor or a multi-core processor, which is configured to execute processor-executable instructions (e.g., code) stored by the CRM 1210. The CRM 1210 may include any suitable type of data storage medium, such as volatile memory (e.g., random access memory (RAM)), non-volatile memory (e.g., flash memory), optical media, magnetic media (e.g., disk or tape), etc. In the context of the present disclosure, the CRM 1210 is implemented to store instructions 1212, data 1214, and other information of the electronic device 1202, and therefore does not include a transient propagating signal or carrier wave.

[0095] The electronic device 1202 may also include an input / output port 1216 (I / O port 1216) or a display 1218. The I / O port 1216 enables data exchange or interaction with other devices, networks, or users. The I / O port 1216 may include a serial port (e.g., a universal serial bus (USB) port), a parallel port, an audio port, an infrared (IR) port, and the like. The display 1218 may be implemented as a screen or projection that presents graphics of the electronic device 1202, such as one or more graphic images, such as for a user interface associated with an operating system, program, or application. Alternatively or additionally, the display 1218 may be implemented as a display port or a virtual interface through which the graphic content of the electronic device 1202 is transmitted or presented.

[0096] For communication purposes, the electronic device 1202 also includes a modem 1220, a wireless transceiver 1222, and at least one antenna 1230. The wireless transceiver 1222 uses RF wireless signals to provide a connection to a corresponding network and other electronic devices connected thereto. Additionally or alternatively, the electronic device 1202 may include a wired transceiver, such as an Ethernet or fiber optic interface, for communicating through a personal or local network, an intranet, or the Internet. The wireless transceiver 1222 can facilitate communication through any suitable type of wireless network, such as a wireless local area network (LAN) (WLAN) (e.g., Wi-Fi or Bluetooth), a peer-to-peer (P2P) network, a mesh network, a cellular network (e.g., 3GPP2, 4G LTE, 5G NR or other cellular networks), a wireless wide area network (WWAN) (e.g., based on 3GPP2, 4G LTE, 5G NR, etc.), a navigation network (e.g., a global positioning system (GPS) or another satellite positioning system (SPS) in North America), and / or a wireless personal area network (WPAN). In the context of example environment 1200, wireless transceiver 1222 enables electronic device 1202 to communicate with base station 1204 and a network to which it is connected. Other figures referenced herein may relate to other wireless networks.

[0097] The modem 1220, such as a baseband modem, can be implemented as a system on chip (SoC) that provides a digital communication interface for data, voice, messaging, and other applications of the electronic device 1202. The modem 1220 may also include a baseband circuit to perform a high-speed sampling process, which may include analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), gain correction, skew correction, frequency conversion, and the like. The modem 1220 may also include logic for performing in-phase / quadrature (I / Q) operations, such as synthesis, encoding, modulation, demodulation, and decoding. More generally, the modem 1220 may be implemented as a digital signal processor (DSP) or a processor configured to perform signal processing to support communication via one or more networks. Alternatively, the ADC or DAC operation may be performed by a separate component or another illustrated component (e.g., a wireless transceiver 1222).

[0098] The wireless transceiver 1222 may include circuits, logic, and other hardware for sending or receiving wireless signals for at least one communication frequency band. In operation, the wireless transceiver 1222 may implement at least one radio frequency transceiver unit to process data and / or signals associated with the communication data of the electronic device 1202 via the antenna 1230. Typically, the wireless transceiver 1222 may include filters, switches, amplifiers, etc. for routing and processing signals sent or received via the antenna 1230. Typically, the wireless transceiver 1222 includes multiple transceiver units (e.g., for different wireless protocols, such as WLAN and WWAN, or for supporting different frequency bands or frequency band combinations).

[0099] In one example, the filters, switches, amplifiers, mixers, etc. of the wireless transceiver 1222 may include at least one single-ended amplifier, a switching circuit, at least one transformer, at least one differential amplifier, and at least one mixer. In some implementations, a single-ended amplifier that amplifies signal strength is coupled to the antenna 1230. Thus, in addition to increasing signal strength, the single-ended amplifier can couple wireless signals to or from the antenna 1230. In some implementations, the switching circuit may switchably couple a single transformer or a group of transformers to the single-ended amplifier. The group of transformers provides physical or electrical separation between the single-ended amplifier and other circuits of the wireless transceiver 1222. The group of transformers also regulates signals propagating through the group of transformers. The output of the transformer may be coupled to one or more mixers.

[0100] Some examples may use a differential amplifier at the output of the transformer before the signal is input to the mixer. In such an example, the differential amplifier is similar to a single-ended amplifier, which enhances the strength of the propagating signal. The wireless transceiver may also perform frequency conversion using a composite signal and a mixer. The mixer may include an up-converter and / or a down-converter, which performs frequency conversion in a single conversion step or through multiple conversion steps. The wireless transceiver 1222 may also include logic (not shown) for performing in-phase / quadrature (I / Q) operations using the composite signal, such as synthesis, encoding, modulation, demodulation, and decoding.

[0101] In some cases, the components of the wireless transceiver 1222 are implemented as separate receiver and transmitter entities. Additionally or alternatively, the wireless transceiver 1222 can be implemented using multiple or different parts to implement corresponding receive and transmit operations (e.g., using separate transmit and receive chains). In addition, different wireless protocols such as WWAN and WLAN can be implemented on separate chips or as separate chip systems (SoCs). Therefore, blocks such as modem 1220 and transceiver 1222 can represent more than one modem 1220 or transceiver implemented together on separate chips or separate SoCs.

[0102] Although elements 1208-1230 are described above with respect to device 1202, these components may also be used to implement base station 1204. In some such examples, the above description of Figure 3-Figure 7 The circuits described and / or hereinbefore Figure 8-Figure 10 The described operations may be implemented in one or more of the processor 1208 , the modem 1220 , and the transceiver 1222 , and / or based on instructions 1212 and / or data 1214 .

[0103] The apparatus implementing the circuits described herein may be a stand-alone device or may be part of a larger device. The device may be (i) a stand-alone IC, (ii) a collection of one or more ICs that may include a memory IC for storing data and / or instructions, (iii) an RFIC such as an RF receiver (RFR) or RF transmitter / receiver (RTR) or corresponding mmW elements, (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded in other devices, (vi) a receiver, a cellular phone, a wireless device, a handset or a mobile unit, a base station or an access point (vii), etc.

[0104] Fig.13 1302, which includes a transceiver 1306 that may include and / or implement phase tracking and correction according to the examples described herein. As shown, in addition to the integrated circuit 1310, the electronic device 1302 also includes an antenna 1304, a transceiver 1306, and an optional user input / output (I / O) interface 1308. The illustrated example of the integrated circuit 1310 or its core includes a microprocessor 1312, an optional graphics processing unit (GPU) 1314, a memory array 1316, and a modem 1318. Each component can be operably coupled to another component, for example, the GPU 1314 is operably coupled to the user I / O interface 1308.

[0105] The electronic device 1302 may be a mobile or battery powered device, or a stationary device designed to be powered by the power grid. Examples of electronic devices 1302 include server computers, network switches or routers, blades in a data center, base stations, access points, CPE, personal computers, desktop computers, notebook or laptop computers, tablet computers, smart phones, entertainment devices, or wearable electronic devices such as smart watches, smart glasses, or clothing. The electronic device 1302 may also be a device or a portion thereof with embedded electronic devices. Examples of electronic devices 1302 with embedded electronic devices include passenger cars, industrial equipment, refrigerators or other household appliances, drones or other unmanned aerial vehicles (UAVs), or power tools.

[0106] For electronic devices with wireless capabilities, the electronic device 1302 includes an antenna 1304, which is coupled to a transceiver 1306 to enable reception or transmission of one or more wireless signals. An integrated circuit 1310 can be coupled to the transceiver 1306 to enable the integrated circuit 1310 to access received wireless signals or provide wireless signals for transmission via the antenna 1304. The electronic device 1302 as shown also includes at least one optional user I / O interface 1308. Examples of user I / O interface 1308 include a keyboard, a mouse, a microphone, a touch-sensitive screen, a camera, an accelerometer, a tactile mechanism, a speaker, a display screen, or a projector. The transceiver 1306 may correspond to, for example (e.g., Fig.12 ) wireless transceiver 1222.

[0107] Integrated circuit 1310 may include, for example, one or more instances of a microprocessor 1312, an optional GPU 1314, a memory array 1316, a modem 1318, and the like. Microprocessor 1312 may be used as a central processing unit (CPU) or other general-purpose processor. Some microprocessors include different parts, such as multiple processing cores, which can be powered on or off independently. GPU 1314 may be particularly suitable for processing visual-related data for display, such as video data images. If visual-related data is not rendered or otherwise processed, GPU 1314 may be fully or partially powered off. Memory array 1316 stores data for microprocessor 1312 or GPU 1314. Example types of memory for memory array 1316 include random access memory (RAM), such as dynamic RAM (DRAM) or static RAM (SRAM); flash memory; and the like. If a program does not access data stored in memory, memory array 1316 may be powered off as a whole or block by block. Modem 1318 demodulates the signal to extract the encoded information, or modulates the signal to encode information into the signal. If there is no information to decode from the incoming communication or encode to the outgoing communication, modem 1318 can be idle to reduce power consumption. Integrated circuit 1310 can include additional or alternative parts other than those shown, such as an I / O interface, a sensor such as an accelerometer, another part of a transceiver or receiver chain, a custom or hard-coded processor such as an application specific integrated circuit (ASIC), and the like.

[0108] Integrated circuit 1310 may also include a system on chip (SoC). An SoC may integrate a sufficient number of different types of components to enable the SoC to provide computing functions as a laptop, mobile phone, base station, or another electronic device, at least primarily using one chip. The components of an SoC or integrated circuit 1310 may generally be referred to as cores or circuit blocks. Fig.13Examples of cores or circuit blocks include, in addition to those shown in , voltage regulators, main memory or cache memory blocks, memory controllers, general purpose processors, cryptographic processors, video or image processors, vector processors, radio units, interface or communication subsystems, wireless controllers, or display controllers. Any of these cores or circuit blocks, such as a central processing unit or a multimedia processor, may further include multiple internal cores or circuit blocks.

[0109] While selected aspects have been shown and described in detail, it will be apparent that various substitutions and modifications may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

[0110] Illustrative aspects of the present disclosure include, but are not limited to:

[0111] Aspect 1. A wireless communication device comprising: an analog 1-bit sampler, which is configured to sample a phase-locked loop (PLL) output signal using a PLL reference clock to generate a 1-bit sample; and a digital phase calculation and control circuit, which is configured to receive the 1-bit sample from the analog 1-bit sampler, and apply phase correction to the PLL based on a phase error derived from the 1-bit sample.

[0112] Aspect 2. The wireless communication device according to aspect 1, wherein the PLL output signal is sampled before a local oscillator (LO) signal generator circuit within a transmit signal path of the wireless communication device.

[0113] Aspect 3. The wireless communication device according to aspect 2, wherein the PLL output signal is sampled in a path between the voltage controlled oscillator and the LO signal generator circuit.

[0114] Aspect 4. The wireless communication device according to aspect 1, wherein the PLL output signal is sampled from a portion of a receive path between a receive PLL circuit and a local oscillator (LO) signal generator circuit.

[0115] Aspect 5. A wireless communication device according to any one of Aspects 1 to 4, wherein the analog 1-bit sampler includes: a signal buffer; a switching circuit; a voltage comparator having an input coupled to the signal buffer via the switching circuit; and a PLL reference clock buffer for a PLL reference clock, the PLL reference clock buffer being coupled to the switching circuit, wherein the PLL reference clock buffer is configured to: control the switching circuit to hold a sample from the PLL output signal at the input via the signal buffer at each cycle of the PLL reference clock.

[0116] Aspect 6. The wireless communication device according to aspect 5, wherein the PLL reference clock buffer is further used to control the timing of the 1-bit output of the voltage comparator when the sample is held at the input of the voltage comparator.

[0117] Aspect 7: The wireless communication device according to any one of aspects 1 to 6, further comprising: a delay element coupled in a path for controlling the timing of the 1-bit output of the voltage comparator.

[0118] Aspect 8. A wireless communication device according to Aspect 7, wherein the delay element is configured to trigger the voltage comparator after each edge of the PLL reference clock to generate a 1-bit output as a 1 or 0 signal at the output of the voltage comparison circuit.

[0119] Aspect 9A. A wireless communication device according to any one of Aspects 1 to 8, wherein the analog 1-bit sampler includes: a signal buffer; a voltage comparator having an input coupled to the signal buffer; and a PLL reference clock buffer for the PLL reference clock, wherein the voltage comparator is coupled to the PLL reference clock buffer to use the PLL reference clock from the PLL reference clock buffer to time the 1-bit sampling of the signal from the signal buffer.

[0120] Aspect 9B. A wireless communication device according to any one of Aspects 1 to 8, wherein the analog 1-bit sampler includes: a signal buffer; a voltage comparator having an input coupled to the signal buffer; and a PLL reference clock buffer for the PLL reference clock, wherein the voltage comparator is coupled to the PLL reference clock buffer and is configured to be activated to use the PLL reference clock from the PLL reference clock buffer to time a 1-bit sample of a signal from the signal buffer to generate a 1-bit sample.

[0121] Aspect 10. The wireless communication device according to any one of aspects 1 to 9, wherein the digital phase calculation and control circuit is configured to: use the 1-bit sampling to calculate a single phase value and the phase error.

[0122] Aspect 11. A wireless communication device according to any one of aspects 1 to 10, wherein the single phase value is calculated using the 1-bit sample multiplied by the corresponding 1-bit quantized phase accumulation value.

[0123] Aspect 12. A wireless communication device according to any one of Aspects 1 to 10, wherein the digital phase calculation and control circuit comprises: a first digital phase accumulator; a second digital phase accumulator; and a sampling input connected to the output of an analog 1-bit sampler.

[0124] Aspect 13. A wireless communication device according to Aspect 12, wherein: when the value from the second digital phase accumulator is in a first dead zone associated with a 50% duty cycle state of the first digital phase accumulator, the value from the first digital phase accumulator is used to calculate the single phase value; and when the value from the first digital phase accumulator is in a second dead zone associated with a 50% duty cycle state of the second digital phase accumulator, the value from the second digital phase accumulator is used to calculate the single phase value.

[0125] Aspect 14. A wireless communication device according to any one of Aspects 1 to 10, wherein the digital phase calculation and control circuit includes: a circuit configured to perform the following operations: compare the phase error with an error target; and when the phase error is greater than the error target, generate a control signal associated with the phase error.

[0126] Aspect 15. The wireless communication device according to aspect 14 further includes: a delta sigma modulation circuit, wherein the output of the digital phase calculation and control circuit is coupled to the delta sigma modulator circuit to provide the control signal to the delta sigma modulation circuit.

[0127] Aspect 16. The wireless communication apparatus of aspect 14, wherein the control signal is selected to generate a single phase error correction to compensate for the phase error.

[0128] Aspect 17. The wireless communication apparatus of aspect 14, wherein the control signal is selected to generate a partial phase error correction to compensate for the phase error over a plurality of subsequent cycles of the phase error calculation and subsequent phase error correction values.

[0129] Aspect 18. A wireless communication device according to any one of Aspects 1 to 17, wherein: the PLL includes a PLL output coupled to the analog 1-bit sampler to provide the PLL output signal to a signal buffer of the analog 1-bit sampler.

[0130] Aspect 19. A wireless communication device according to any one of Aspects 1 to 18, further comprising a local oscillator (LO) signal generating circuit coupled to the PLL output and a feedback loop between the PLL output and the LO signal generator to compensate for high-frequency phase spikes, wherein the phase correction applied by the digital phase calculation and control circuit compensates for low-frequency phase drift.

[0131] Aspect 20. The wireless communication device according to any one of Aspects 1 to 19 further includes: a digital divider circuit, the digital divider circuit including: a first input coupled to the PLL output; a second input coupled to the digital phase calculation and control circuit; and an output, which is configured to provide a feedback clock to the input of the PLL, wherein, in response to a phase error being greater than a threshold value, the feedback clock is selected at least in part by dividing the PLL output signal received from the PLL based on a control signal from the digital phase calculation and control circuit.

[0132] Aspect 21. The wireless communication device according to aspect 20, further comprising: a delta sigma modulator, wherein the delta sigma modulator is configured to: set a frequency division value of the digital frequency divider circuit based on the control signal.

[0133] Aspect 22. A wireless communication device according to any one of Aspects 1 to 21, wherein the digital phase calculation and control circuit is further configured to: monitor the phase error according to an operation setup state indicated by a processing circuit of the wireless communication device.

[0134] Aspect 23. A wireless communication device according to Aspect 22, wherein the operation setup state indicates monitoring a single calculation cycle in a single measurement state, monitoring until a phase error is less than a threshold error value in a tracking measurement state, and monitoring repeated calculation cycles until an interruption is received in a continuous measurement state.

[0135] Aspect 24. A wireless communication device comprising: a signal path; an analog sampler coupled to the signal path at a detection position and configured to generate a 1-bit phase sample of the signal on the signal path; a phase sampling circuit having an input coupled to the analog sampler and an output indicating an average phase value over a calculation period; and a control circuit configured to determine a phase error value based on the average phase value of the calculation period of each of a plurality of phase accumulators, compare the phase error value with a threshold value, and generate a control signal when the phase error value is greater than the threshold value.

[0136] Aspect 25. The wireless communication device according to Aspect 24 further includes: a phase-locked loop (PLL) having a control input and a signal output, the signal output being configured to provide the signal to the signal path, wherein the control circuit is configured to provide the control signal to the control input of the PLL when the phase error value is greater than a threshold value.

[0137] Aspect 26. A wireless communication device according to any one of Aspects 24 to 25, wherein the phase sampling circuit includes: the plurality of phase accumulators configured to calculate an accumulated value corresponding to each bit of the 1-bit phase sample from the analog sampler; and a calculation circuit configured to multiply each 1-bit phase sample by a corresponding accumulated value from each of the plurality of phase accumulators; and determine an average phase value of each of the plurality of phase accumulators over the calculation period.

[0138] Aspect 27. A method comprising: determining a phase error threshold; calculating a phase error value using multiple 1-bit samples from an analog sampler and a digital circuit, wherein the analog sampler and the digital circuit are coupled to an output of a phase-locked loop (PLL) circuit and a reference clock network of a wireless communication device; and if the error value is greater than the phase error threshold, applying a phase correction to the PLL circuit based on the output of the digital circuit.

[0139] Aspect 28. The method according to Aspect 27 further includes: selecting an operation setup state between a single measurement state, a tracking measurement state, and a continuous measurement state; and calculating a corresponding phase error value within a calculation cycle based on the operation setup state.

[0140] Aspect 29. The method according to aspect 28 further comprises: selecting a number of 1-bit samples in the calculation cycle, and selecting a phase error threshold for the operation establishment state.

[0141] Aspect 30. A method according to any one of Aspects 27 to 29, wherein the digital circuit comprises: a first phase accumulator and a second phase accumulator, and wherein calculating the phase error value comprises: calculating the phase error value based on the number of 1-bit samples and the phase accumulation values ​​from the first phase accumulator and the second phase accumulator.

[0142] Aspect 31: An apparatus comprising means for performing the operations according to any one of aspects 1 to 30 above.

[0143] Aspect 32: A non-transitory computer-readable storage medium, comprising instructions stored thereon, which, when executed by one or more processors, cause the one or more processors to implement the operations according to any one of Aspects 1 to 30 above.

Claims

1. A wireless communication device, comprising: an analog 1-bit sampler configured to sample a phase-locked loop (PLL) output signal using a PLL reference clock to generate a 1-bit sample; as well as A digital phase calculation and control circuit is configured to receive the 1-bit sample from the analog 1-bit sampler and apply a phase correction to the PLL based on a phase error derived from the 1-bit sample.

2. The wireless communication device according to claim 1, wherein: The PLL output signal is sampled prior to a local oscillator (LO) signal generator circuit within a transmit signal path of the wireless communication device.

3. The wireless communication device according to claim 2, wherein: The PLL output signal is sampled in a path between a voltage controlled oscillator and the LO signal generator circuit.

4. The wireless communication device according to claim 1, wherein: The PLL output signal is sampled from a portion of a receive path between a receive PLL circuit and a local oscillator (LO) signal generator circuit.

5. The wireless communication device according to claim 1, wherein: The analog 1-bit sampler comprises: signal buffer; Switching circuit; a voltage comparator having an input coupled to the signal buffer via the switch circuit; and a PLL reference clock buffer for the PLL reference clock, the PLL reference clock buffer being coupled to the switch circuit, wherein the PLL reference clock buffer is configured to control the switch circuit to hold a sample from the PLL output signal at the input via the signal buffer at each cycle of the PLL reference clock.

6. The wireless communication device according to claim 5, wherein: The PLL reference clock buffer is also used to control the timing of the 1-bit output of the voltage comparator while the sample is held at the input of the voltage comparator.

7. The wireless communication device according to claim 6, further comprising: A delay element is coupled in a path for controlling the timing of the 1-bit output of the voltage comparator.

8. The wireless communication device according to claim 7, wherein: The delay element is configured to trigger the voltage comparator after each edge of the PLL reference clock to generate the 1-bit output as a 1 or 0 signal at the output of the voltage comparison circuit.

9. The wireless communication device according to claim 1, wherein: The analog 1-bit sampler comprises: signal buffer; a voltage comparator having an input coupled to the signal buffer; and a PLL reference clock buffer for the PLL reference clock, wherein the voltage comparator is coupled to the PLL reference clock buffer and configured to be activated by the PLL reference clock from the PLL reference clock buffer to generate the 1-bit sample.

10. The wireless communication device according to claim 9, wherein: The digital phase calculation and control circuit is configured to calculate a single phase value and the phase error using the 1-bit samples.

11. The wireless communication device according to claim 10, wherein: The single phase value is calculated using the 1-bit sample multiplied by a corresponding 1-bit quantized phase accumulation value.

12. The wireless communication device according to claim 10, wherein: The digital phase calculation and control circuit comprises: a first digital phase accumulator; a second digital phase accumulator; and Connect to the sampling input of the analog 1-bit sampler output.

13. The wireless communication device according to claim 12, wherein: calculating the single phase value using the value from the first digital phase accumulator when the value from the second digital phase accumulator is in a first dead band associated with a 50% duty cycle state of the first digital phase accumulator; as well as The single phase value is calculated using the value from the second digital phase accumulator when the value from the first digital phase accumulator is in a second dead band associated with a 50% duty cycle state of the second digital phase accumulator.

14. The wireless communication device according to claim 10, wherein: The digital phase calculation and control circuit includes circuitry configured to: comparing the phase error to an error target; and A control signal associated with the phase error is generated when the phase error is greater than the error target.

15. The wireless communication device according to claim 14, further comprising: A delta sigma modulation circuit, wherein the output of the digital phase calculation and control circuit is coupled to the delta sigma modulator circuit to provide the control signal to the delta sigma modulation circuit.

16. The wireless communication device according to claim 14, wherein: The control signal is selected to generate a single phase error correction to compensate for the phase error.

17. The wireless communication device according to claim 14, wherein: The control signal is selected to generate a partial phase error correction to compensate for the phase error and subsequent phase error correction values ​​over a plurality of subsequent cycles of phase error calculation.

18. The wireless communication device of claim 1, wherein: The PLL includes a PLL output coupled to the analog 1-bit sampler to provide a signal buffer of the analog 1-bit sampler with the PLL output signal.

19. The wireless communication device according to claim 18, further comprising: A local oscillator (LO) signal generating circuit is coupled to the PLL output.

20. The wireless communication device of claim 19, further comprising: A digital frequency divider circuit, the digital frequency divider circuit comprising: A first input coupled to the PLL output; coupled to a second input of said digital phase calculation and control circuit; and an output configured to provide a feedback clock to an input of the PLL, wherein, in response to the phase error being greater than a threshold value, the feedback clock is selected at least in part by dividing the PLL output signal received from the PLL based on a control signal from the digital phase calculation and control circuit.

21. The wireless communication device according to claim 20, further comprising: A delta sigma modulator, wherein the delta sigma modulator is configured to: set a frequency division value of the digital frequency divider circuit based on the control signal; and A feedback loop is provided between the PLL output and the LO signal generator to compensate for high frequency phase spikes, wherein the phase correction applied by the digital phase calculation and control circuit compensates for low frequency phase drift.

22. The wireless communication device according to claim 1, wherein: The digital phase calculation and control circuit is further configured to monitor the phase error based on an operational setup status indicated by processing circuitry of the wireless communication device.

23. The wireless communication device according to claim 22, wherein: The operational setup state indicates monitoring a single calculation cycle in a single measurement state, monitoring until a phase error is less than a threshold error value in a tracking measurement state, and monitoring repeated calculation cycles until an interrupt is received in a continuous measurement state.

24. A wireless communication device, comprising: Signal path; an analog sampler coupled to the signal path at a detection location and configured to generate a 1-bit phase sample of the signal on the signal path; a phase sampling circuit having an input coupled to the analog sampler and an output indicative of an average phase value over a computation period; as well as A control circuit is configured to determine a phase error value based on the average phase value of the calculation cycle of each of a plurality of phase accumulators, compare the phase error value with a threshold value, and generate a control signal when the phase error value is greater than the threshold value.

25. The wireless communication device of claim 24, further comprising: A phase locked loop (PLL) having a control input and a signal output, the signal output being configured to provide the signal to the signal path, wherein the control circuit is configured to provide the control signal to the control input of the PLL when the phase error is greater than the threshold value.

26. The wireless communication device according to claim 24, wherein: The phase sampling circuit comprises: the plurality of phase accumulators configured to calculate an accumulated value corresponding to each bit of the 1-bit phase sample from the analog sampler; and A calculation circuit is configured to multiply each 1-bit phase sample by a corresponding accumulated value from each of the plurality of phase accumulators; and determine the average phase value of each of the plurality of phase accumulators over the calculation period.

27. A method comprising: determining a phase error threshold; calculating a phase error value using a plurality of 1-bit samples from an analog sampler and a digital circuit coupled to an output of a phase locked loop (PLL) circuit and a reference clock network of a wireless communication device; as well as If the error value is greater than the phase error threshold, a phase correction is applied to the PLL circuit based on the output of the digital circuit.

28. The method according to claim 27, further comprising: Selecting the operation setup state between a single measurement state, a tracking measurement state, and a continuous measurement state; as well as A corresponding phase error value is calculated within a calculation cycle based on the operation setup state.

29. The method according to claim 28, further comprising: A number of 1-bit samples are selected in the calculation cycle, and a phase error threshold is selected for the operation setup state.

30. The method of claim 27, wherein: The digital circuit includes: a first phase accumulator and a second phase accumulator, and wherein calculating the phase error value includes calculating the phase error value based on the plurality of 1-bit samples and phase accumulation values ​​from the first phase accumulator and the second phase accumulator.

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