Centralized phased array beam control method and system based on FPGA

Abstract

The invention discloses a centralized phased array beam control method and system based on an FPGA, and relates to the technical field of phased array beam control, and the method comprises the steps: carrying out the real-time iterative operation through an incremental adaptive correction kernel in a centralized control FPGA, and obtaining an amplitude-phase correction increment and a corresponding target effective frame number; performing increment differential coding on the amplitude-phase correction increment and the corresponding target effective frame number in a centralized control FPGA (Field Programmable Gate Array) to generate an increment differential beam control message; sending the increment difference beam control message to an array element FPGA (Field Programmable Gate Array) at the front end of an array, executing frame-level atom switching according to a target effective frame number, and fusing the amplitude-phase correction increment and a locally stored old beam control weight in the switching process to obtain a final array element beam control weight; generating a real-time beam control directional diagram based on the final array element beam control weight; the stability and convergence precision of beam control are improved, and the bandwidth requirement of a control link is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of phased array beam control technology, in particular to a centralized phased array beam control method and system based on FPGA. BACKGROUND

[0002] With the wide application of phased array technology in radar, communication and electronic countermeasures, the real-time controllability, pointing accuracy and dynamic performance of array beam have gradually become the key determinants of system performance. Traditional phased array beam control systems are mostly based on distributed architecture, with amplitude and phase adjustment and local closed-loop correction performed by each array element or subarray front end. In recent years, some centralized control architectures have also appeared, which calculate beam control weights uniformly through a central processor and then send them to the array front end to achieve higher consistency and faster response. At the same time, FPGA has become an important hardware platform for implementing real-time beam control algorithms, array error compensation and high-speed interface scheduling due to its programmable logic structure, strong parallel computing capability and low latency advantage.

[0003] In existing centralized beam control methods, array errors usually need to be repeatedly sent in the form of whole-frame amplitude and phase control weights, and complete data containing all amplitude and phase parameters must be sent to all array elements in each control period. With the continuous expansion of array size and the continuous improvement of beam refresh frequency, this full-quantity transmission mode makes the link data volume increase linearly or even explosively, resulting in the beam control channel being occupied by a large number of unchanged reference weights repeatedly transmitted, and low communication efficiency. At the same time, the communication pressure increases significantly, making it difficult to maintain low-latency real-time scheduling, which limits the response capability of the system in high-dynamic scenarios such as fast beam switching and real-time adaptive anti-jamming. SUMMARY

[0004] In view of the above existing problems, the present application is proposed.

[0005] Therefore, the present application provides a centralized phased array beam control method based on FPGA to solve the problem of excessive update data volume and high link load in centralized beam control.

[0006] To solve the above technical problems, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides a centralized phased array beam control method based on FPGA, which comprises:

[0008] Through centralized control FPGA, obtain phased array operation monitoring information to perform array error estimation, obtain array amplitude and phase error, and generate reference beam pointing weight according to beam control task;

[0009] Based on the reference beam pointing weight value and the array amplitude and phase error, the real-time iterative operation is carried out through the incremental adaptive correction kernel in the centralized control FPGA to obtain the amplitude and phase correction increment and the corresponding target effective frame number;

[0010] The amplitude and phase correction increment and the corresponding target effective frame number are subjected to incremental differential encoding in the centralized control FPGA to generate an incremental differential beam control message.

[0011] The incremental differential beam control message is sent to the array front-end element FPGA, frame-level atomic switching is performed according to the target effective frame number, and the amplitude and phase correction increment and the locally stored old beam control weight value are fused in the switching process to obtain the final element beam control weight value.

[0012] Based on the final element beam control weight value, a real-time beam control direction map is generated, and the array amplitude and phase error of the next control cycle is updated according to the real-time beam control direction map.

[0013] As a preferred scheme of the FPGA-based centralized phased array beam control method, the application comprises the following steps:

[0014] The acquisition module is used for acquiring phased array operation monitoring information through the centralized control FPGA to perform array error estimation and obtain the array amplitude and phase error, and generating a reference beam pointing weight value according to the beam control task.

[0015] The incremental calculation module is used for obtaining the amplitude and phase correction increment and the corresponding target effective frame number through the real-time iterative operation of the incremental adaptive correction kernel in the centralized control FPGA based on the reference beam pointing weight value and the array amplitude and phase error.

[0016] The message generation module is used for generating an incremental differential beam control message by subjecting the amplitude and phase correction increment and the corresponding target effective frame number to incremental differential encoding in the centralized control FPGA.

[0017] The synchronous fusion module is used for sending the incremental differential beam control message to the array front-end element FPGA, performing frame-level atomic switching according to the target effective frame number, and fusing the amplitude and phase correction increment and the locally stored old beam control weight value in the switching process to obtain the final element beam control weight value.

[0018] The update module is used for generating a real-time beam control direction map based on the final element beam control weight value, and updating the array amplitude and phase error of the next control cycle according to the real-time beam control direction map.

[0019] Further, the array amplitude and phase error and the reference beam pointing weight value acquisition method comprises the following steps:

[0020] Based on the phased array operation monitoring information, the centralized control FPGA performs amplitude-phase error solving to obtain array element amplitude deviation and phase change, and array amplitude-phase error.

[0021] According to the pointing requirements of the beam control task, the centralized control FPGA determines the amplitude-phase pointing reference that each array element should have in the current period in combination with the geometric layout of the array and the target pointing angle, and generates a reference beam pointing weight.

[0022] Further, the method for obtaining the amplitude-phase correction increment and the corresponding target effective frame number comprises:

[0023] The centralized control FPGA performs amplitude-phase difference operation on the reference beam pointing weight and the array amplitude-phase error element by element, and extracts error information.

[0024] Based on the error information, the centralized control FPGA calls its internal incremental adaptive correction kernel to gradually adjust the amplitude compensation and phase compensation of each array element according to the current working state of the array and the error change trend, and obtains the amplitude-phase correction increment conforming to the current control period through multiple rounds of small-step iteration.

[0025] The centralized control FPGA combines the link transmission delay, the array element FPGA switching rhythm, and the refresh frequency of the beam control task to perform time alignment evaluation on the amplitude-phase correction increment, and determines the target effective frame number corresponding to the amplitude-phase correction increment.

[0026] Further, the method for generating the incremental differential beam control packet comprises:

[0027] The centralized control FPGA performs amplitude-phase difference value operation on the amplitude compensation and phase compensation of each array element based on the amplitude-phase correction increment, taking the old beam control weight of the array element in the last period as the differential reference; the difference between the new and old amplitude-phase control quantities is quantized, compressed, and field reorganized to express in the form of incremental amplitude-phase change with the minimum necessary amplitude-phase change, forming an amplitude-phase correction increment suitable for low-bandwidth link transmission;

[0028] The amplitude-phase correction increment suitable for low-bandwidth link transmission is structured and organized in frame sequence with the target effective frame number; the combination of the amplitude increment domain, the phase increment domain, and the effective frame number domain forms compact incremental differential encoding, reducing the data volume of the beam control parameters;

[0029] The structured field of the incremental differential encoding is packaged into a downlink-resolvable incremental differential beam control packet.

[0030] Further, the execution of the frame-level atomic switching comprises:

[0031] The incremental differential beam control message is sent to the array front-end element FPGA via the downlink; after receiving the incremental differential beam control message, the amplitude compensation amount and phase compensation amount in it are cached in the pre-update register, and compared with the local frame counter according to the target effective frame number carried in the message.

[0032] When the local frame counter reaches the target effective frame number, a register group switch is triggered at the boundary of a single time slot, so that the buffered amplitude and phase correction increments and the old beam control weights stored locally are synchronized into the fusion path.

[0033] Furthermore, the method for obtaining the final array element beam control weights includes:

[0034] Within the same time slot boundary where the register group completes the switching, the amplitude and phase correction increments that will be synchronously entered into the fusion path will be synthesized item by item in the amplitude and phase domains with the old beam control weights of the previous cycle stored locally, according to the array element correspondence.

[0035] Amplitude and phase domain fusion is achieved by adding amplitude compensation to the old amplitude control and phase compensation to the old phase control, resulting in the final array element beam control weights that conform to the current target effective frame number.

[0036] Furthermore, the method for generating a real-time beam control pattern includes:

[0037] The final array element beam control weights are loaded in parallel to the amplitude control unit and phase control unit of all transceiver components in the array through the control interface of the front-end array element FPGA.

[0038] The transceiver component is driven by the digital control circuit built into it, which converts the final array element beam control weights into digital adjustment parameters required by the radio frequency link, and adjusts the signal amplitude and phase of each array element to obtain the radio frequency signal.

[0039] Radio frequency signals are spatially synthesized to form an electromagnetic beam with target pointing and desired pattern characteristics in free space, and the real-time beam control pattern for the current control cycle is output.

[0040] Furthermore, updating the array amplitude and phase error for the next control cycle based on the real-time beam control pattern includes:

[0041] The centralized control FPGA evaluates the deviation of the real-time beam control pattern, compares the pattern characteristic index with the corresponding index of the preset pattern expression specification, and obtains the pattern deviation.

[0042] The radiation pattern deviation is correlated with the final element beam control weights of the current cycle, and the amplitude contribution error and phase contribution error are calculated according to the element dimension to form the initial error signal.

[0043] The initial error signal is synchronously compared with the instantaneous array operating state of the current period, and the initial error signal is corrected and compensated in the time domain according to the historical error change pattern of the array in the stable operating range.

[0044] The corrected error signal is used as the array amplitude and phase error for the next control cycle and written into the error update register, so that it serves as the error reference for the amplitude and phase correction increment solution process in the next control cycle.

[0045] Furthermore, the method for triggering a register group switch at a single time slot boundary when the local frame counter reaches the target effective frame number includes:

[0046] The array front-end element FPGA continuously receives the global synchronization clock from the centralized control FPGA and runs the local frame counter through the clock synchronization logic to ensure that the counters of all elements are strictly aligned with the frame timing of the centralized control FPGA.

[0047] The array front-end element FPGA performs real-time cycle-by-cycle comparison between the value of the local frame counter and the target effective frame number carried in the incremental differential beam control message; when the value of the local frame counter is equal to the target effective frame number, the array element FPGA immediately triggers the control signal when it receives the rising edge of the next clock cycle.

[0048] The trigger control signal acts simultaneously on the pre-update register and the locally stored old beam control weights in the front-end array element; causing the amplitude and phase correction increments and the old beam control weights to unlock at the same time and enter the fusion path synchronously.

[0049] The beneficial effects of this invention are as follows: By using an incremental adaptive correction kernel to perform small-step iterations through centralized control of the FPGA, amplitude and phase correction increments containing only necessary changes and pre-planned target effective frame numbers are generated. This achieves smooth and gradual compensation and precise time alignment of control commands, effectively improving the stability and convergence accuracy of beam control and reducing the bandwidth requirements of the control link. At the same time, by triggering frame-level atomic switching on the array front-end FPGA based on the target effective frame number, the received increments are instantaneously fused with the local old weights at strictly synchronized time slot boundaries. This ensures strict synchronization, phase consistency, and update reliability of beam state switching for all elements of a large-scale phased array. Thus, while ensuring high-precision beamforming quality, it solves the key problems of large control data volume and difficulty in real-time synchronization. Attached Figure Description

[0050] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a flowchart of the FPGA-based centralized phased array beam control method in this invention;

[0052] Figure 2 This is a schematic diagram of the FPGA-based centralized phased array beam control system in this invention.

[0053] Figure 3 This is a flowchart illustrating the generation of incremental differential beam control messages in this invention;

[0054] Figure 4 This is a flowchart illustrating the process of obtaining the final array element beam control weights in this invention. Detailed Implementation

[0055] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0056] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0057] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0058] Reference Figure 1 , Figure 2 , Figure 3 and Figure 4 This is one embodiment of the present invention, which provides a centralized phased array beam control method based on FPGA, including the following steps:

[0059] Methods for obtaining array amplitude and phase errors and reference beam pointing weights include:

[0060] Based on the phased array operation monitoring information, the FPGA is centrally controlled to perform amplitude and phase error calculation, obtain the amplitude deviation and phase change of the array elements, and obtain the array amplitude and phase error.

[0061] It should be noted that the phased array operation monitoring information refers to the data collected and transmitted back to the centralized control FPGA in real time during the array operation by the front-end array element FPGA through the array control link, such as a high-speed serial bus, fiber optic interface or dedicated data acquisition network. This includes the amplitude and phase status quantities of the array element transceiver components (as RF performance indicators), as well as drive current, power supply status, temperature parameters and local feedback monitoring quantities (as instantaneous array operating status). This information is a key electrical and environmental parameter used for error correction.

[0062] Using the amplitude and phase pointing reference of the array element in the control cycle as a reference, the amplitude and phase monitoring quantities of each array element are compared and differentially calculated item by item. The amplitude and phase deviations that reflect the actual state of the array element deviating from the ideal pointing requirements are extracted to form the array amplitude and phase error, which is a set of amplitude and phase deviation values ​​indexed by the array element number.

[0063] Based on the pointing requirements of the beam control task, the centralized control FPGA, combined with the array's geometric layout and target pointing angle, determines the amplitude and phase pointing reference that each array element should have in this cycle, and generates the reference beam pointing weights.

[0064] Specifically, the centralized control FPGA calculates the unit vector pointing towards the target based on the target pointing angle required by the beam control task; it then performs a dot product operation between the position vector of each array element relative to the array reference center and the unit vector pointing towards the target to calculate the required phase compensation for each element as a phase pointing reference. The expression for calculating the phase compensation is as follows:

[0065] ;

[0066] in, It is the first Phase compensation amount (phase pointing reference) of each array element. It is the operating wavelength. It is the first The position vectors of each array element relative to the reference center It is a unit vector pointing in the direction of the target. It is the array element number. It is twice the value of pi;

[0067] The centralized control FPGA uses an amplitude weighting algorithm to calculate the amplitude weighting value of each array element based on the sidelobe suppression requirements of the beam task. This value serves as the amplitude pointing reference. The phase pointing reference and the amplitude pointing reference are combined into a complex number to form the reference beam pointing weight.

[0068] Methods for obtaining the amplitude and phase correction increment and the corresponding target effective frame number include:

[0069] The centralized control FPGA performs element-by-element amplitude and phase differential operations on the reference beam pointing weights and the array amplitude and phase errors to extract error information.

[0070] Specifically, the centralized control FPGA fuses the ideal amplitude and phase pointing references with the actual amplitude and phase errors of the acquisition array to calculate the actual operating state weights of the array elements in the current control cycle. These actual operating state weights are then compared element-by-element with the old beam control weights issued and applied in the previous control cycle. By calculating the amplitude and phase differences between the two, the differences between the actual state of the array elements and the state in the previous cycle are extracted. This forms the amplitude and phase increments that need to be adjusted in the current cycle, serving as precise error information.

[0071] Based on error information, the centralized control FPGA calls its internal incremental adaptive correction core. According to the current working state of the array and the error change trend, it gradually adjusts the amplitude compensation and phase compensation of each array element. Through multiple rounds of small-step iteration, it obtains the amplitude and phase correction increment that conforms to the current control cycle.

[0072] Specifically, the centralized control FPGA inputs the error information into its internal incremental adaptive correction core; the correction core initiates adaptive iterative calculations based on the current working state of the array and the error change trend of the error information over time.

[0073] The calibration kernel employs a multi-round, small-step iterative approach using the least mean square error (LMS) or a similar mechanism. In each iteration, based on the current error signal, the required amplitude and phase compensation amounts for each array element are gradually adjusted with an adaptive step size. This small-step iterative strategy effectively avoids beam pattern jitter and instability caused by large-step jumps in weights. The calibration kernel continues iterative calculations until the obtained amplitude and phase compensation amounts enable the array to meet predetermined performance indicators within the current control cycle, such as pointing accuracy less than 0.05° RMS, sidelobe suppression less than -30dB, or main lobe beamwidth less than 1.5 degrees. The final amplitude and phase compensation amounts are then combined to form the amplitude and phase correction increment.

[0074] The centralized control FPGA, combined with the link transmission delay, the FPGA switching rhythm of the array elements, and the refresh frequency of the beam control task, performs time alignment evaluation on the amplitude and phase correction increment to determine the target effective frame number corresponding to the amplitude and phase correction increment.

[0075] It should be noted that after generating the amplitude and phase correction increment, the centralized control FPGA evaluates the link transmission delay from itself to the array front-end element FPGA; it rounds the transmission time up to align it to the nearest future effective time when the element FPGA can switch data (i.e., the element FPGA switching rhythm); by comprehensively considering these factors and ensuring that it does not exceed the next refresh cycle required by the beam control task, the centralized control FPGA performs time alignment evaluation and finally locks a unique future frame counter value as an identifier for all elements to synchronously update the amplitude and phase correction increment, i.e., the target effective frame number.

[0076] Methods for generating incremental differential beam control messages include:

[0077] The centralized control FPGA uses the old beam control weights of the previous cycle of the array element as the differential reference to calculate the amplitude and phase difference of each array element based on the amplitude and phase compensation amount. The difference between the new and old amplitude and phase control amounts is quantized, compressed, and reorganized into fields, and expressed in the form of the minimum necessary amplitude and phase change increment, forming an amplitude and phase correction increment suitable for low bandwidth link transmission.

[0078] It should be noted that the centralized control FPGA uses the old beam control weights issued and actually applied in the previous control cycle of the array element as the differential reference; it synthesizes the old beam control weights with the amplitude and phase correction increments obtained in the current cycle to obtain the target beam control weights; it performs element-by-element difference calculations on the target beam control weights and the old beam control weights in the amplitude and phase domains to calculate the net amplitude change and net phase change, which are equivalent to the amplitude and phase correction increments.

[0079] Because the weight changes of a phased array between adjacent control cycles are often very small, centralized control FPGAs utilize this characteristic to perform precision dimensionality reduction processing on the net amplitude and phase changes. For example, the high-precision bit width (e.g., twelve bits) originally used to represent the full weights is mapped to a shorter bit width (e.g., six or eight bits), retaining only the bits that can express the minimum effective amplitude step and the minimum effective phase step. This quantization compression process achieves effective dimensionality reduction of the difference between the old and new amplitude and phase control quantities, significantly reducing the number of bits required to express the control of a single array element;

[0080] The net amplitude and phase changes after quantization and compression are combined and expressed as an increment of the minimum necessary amplitude and phase changes, forming an amplitude and phase correction increment suitable for low-bandwidth link transmission. This encoding method no longer transmits the complete amplitude and phase values, but only the relative changes. This incremental expression significantly reduces the data volume compared to transmitting high-precision full weights, resulting in compact data packets suitable for low-bandwidth link transmission, thus ensuring real-time high-speed beam scheduling capabilities in large-scale arrays.

[0081] The amplitude and phase correction increments suitable for low-bandwidth link transmission are structured and organized with the target effective frame number in frame order; by combining the amplitude increment domain, phase increment domain and effective frame number domain, a compact incremental differential code is formed, reducing the amount of data sent for beam control parameters.

[0082] It should be noted that the centralized control FPGA serializes the net amplitude change and net phase change obtained after quantization and compression of all array elements according to the array element sequence number, forming a complete amplitude increment domain data stream and phase increment domain data stream; the target effective frame number is used as the synchronization and execution identifier of the message and placed at the beginning of the entire data structure; by logically associating and sequentially combining the three core fields of effective frame number field, amplitude increment domain, and phase increment domain according to the predetermined frame order and array element sequence number, a compact incremental differential code is formed, realizing a high degree of integration between control data and time synchronization information, and effectively reducing the amount of data sent for beam control parameters;

[0083] It should be noted that the predetermined frame order and array element number refer to the data arrangement order that the centralized control FPGA agrees on in advance and strictly follows when constructing the message. For example, the amplitude increments of all array elements are arranged in the order from array element 1 to array element N, and then the phase increments of all array elements are also arranged in this order.

[0084] The structured fields of incremental differential encoding are encapsulated into downlink-parseable incremental differential beam control messages.

[0085] Specifically, the centralized control FPGA encapsulates the incremental differential encoded structured fields according to the requirements of the downlink transmission protocol. The encapsulation process includes, but is not limited to, adding start and end identifiers, data checksums (such as CRC checksums), and necessary header information. The resulting incremental differential beam control message is a complete data packet with high compression ratio, carrying accurate synchronization information and robust to the link, representing the final form for efficient beam control command issuance.

[0086] Performing frame-level atomic switching includes:

[0087] The incremental differential beam control message is sent to the array front-end element FPGA via the downlink. After receiving the incremental differential beam control message, the amplitude compensation amount and phase compensation amount are cached in the pre-update register, and compared with the local frame counter according to the target effective frame number carried in the message.

[0088] It should be noted that the centralized control FPGA transmits the encapsulated incremental differential beam control messages at high speed to the array front-end element FPGA via the downlink interface. The messages undergo integrity verification and structured parsing, and the minimum necessary amplitude and phase compensation values ​​are extracted. These values ​​are then temporarily stored in a pre-update register, awaiting activation. Based on the target active frame number carried in the message, a synchronization comparison is performed between the local and global synchronized clock-driven local frame counter, preparing the time for subsequent frame-level atomic switching.

[0089] When the local frame counter reaches the target effective frame number, a register group switch is triggered at the boundary of a single time slot, so that the buffered amplitude and phase correction increments and the old beam control weights stored locally are synchronized into the fusion path.

[0090] It should be noted that when the FPGA element of the array front-end detects that the value of its local frame counter is equal to the target effective frame number, it immediately generates a control signal. This control signal triggers a register group switching operation at the single time slot boundary of the next clock cycle. This atomic switching mechanism ensures that within the same tiny time window, the amplitude and phase correction increments temporarily stored in the pre-update register and the old beam control weights of the previous cycle stored locally are simultaneously unlocked and synchronously entered into the fusion path; through synchronous operation, it ensures that all array elements apply the new weights at the same time, avoiding instantaneous jitter and distortion in the beam pattern.

[0091] Methods for obtaining the final element beam control weights include:

[0092] Within the same time slot boundary where the register group completes the switching, the amplitude and phase correction increments that will be synchronously entered into the fusion path will be synthesized item by item in the amplitude and phase domains with the old beam control weights of the previous cycle stored locally, according to the array element correspondence.

[0093] Specifically, because the register group switching is triggered and completed within a single time slot boundary, it ensures that the amplitude and phase correction increments and the old beam control weights of the previous cycle can appear simultaneously in the fusion path. The array front-end element FPGA ensures, based on the element number in the incremental differential encoding, that the amplitude compensation and phase compensation of each element are added to its own old amplitude control and old phase control values ​​only.

[0094] Amplitude and phase domain fusion is achieved by adding amplitude compensation to the old amplitude control and phase compensation to the old phase control, resulting in the final array element beam control weights that conform to the current target effective frame number.

[0095] It should be noted that the old control baseline is linearly superimposed with the net change calculated for the current period, specifically as follows:

[0096] Final amplitude control amount = old amplitude control amount + amplitude compensation amount;

[0097] The final phase control value = old phase control value + phase compensation value. The array front-end element FPGA instantly updates the amplitude and phase weights of all array elements within a single time slot boundary, thus obtaining the final array element beam control weights.

[0098] Methods for generating real-time beam control patterns include:

[0099] The final beam control weights of the array elements are loaded in parallel to the amplitude control units and phase control units of all transceiver components in the array through the control interface of the front-end array element FPGA.

[0100] Specifically, the final element beam control weights are simultaneously transmitted to every transceiver component in the array via a high-speed parallel control bus or a dedicated control interface. This parallel loading mechanism ensures that the amplitude control units and phase control units of all elements can receive and update to the latest and corrected final element beam control weights for the current cycle within a short time.

[0101] The transceiver unit is driven by a built-in digital control circuit, which converts the final array element beam control weights into digital adjustment parameters required by the radio frequency link, and adjusts the signal amplitude and phase of each array element to obtain the radio frequency signal.

[0102] Specifically, after receiving the final element beam control weights, the transceiver component's internal digital control circuitry (such as a digital attenuator, digital phase shifter, or waveform generation module) analyzes these weights and converts them into digital adjustment parameters that actually affect the RF link. These digital adjustment parameters precisely drive the transceiver component to perform amplitude weighting and phase adjustment on the RF signal being processed by the element, ensuring that the amplitude and phase of the RF signal strictly conform to the requirements of the final element beam control weights, ultimately outputting an RF signal from each element port.

[0103] Radio frequency signals are spatially synthesized to form an electromagnetic beam with target pointing and desired pattern characteristics in free space, and the real-time beam control pattern for the current control cycle is output.

[0104] Specifically, radio frequency (RF) signals are fed into the antenna elements of the array and radiated outwards. Since the phase relationships and amplitude weights of all array element signals are precisely calculated, corrected, and atomically synchronized by a centralized control FPGA, these RF signals coherently superimpose (i.e., spatial synthesis) in free space according to Huygens' principle. This coherent superposition causes the electromagnetic beam energy to form a main lobe in the predetermined target pointing direction, exhibiting the expected radiation pattern characteristics (such as sidelobe suppression and main lobe width). This superposition result is the real-time beam control pattern actually radiated by the array within this control cycle.

[0105] The array amplitude and phase error is updated for the next control cycle based on the real-time beam control pattern, including:

[0106] The centralized control FPGA evaluates the deviation of the real-time beam control pattern, compares the pattern characteristic index with the corresponding index of the preset pattern expression specification, and obtains the pattern deviation.

[0107] It should be noted that the centralized control FPGA receives pattern measurement feedback data from the array (e.g., acquired through a specific monitoring receiver) and compares this pattern measurement feedback data with a theoretically ideal preset pattern representation specification.

[0108] Beam pattern characteristics include, but are not limited to, key parameters such as main lobe pointing accuracy, beamwidth, and sidelobe level. By quantitatively analyzing these beam pattern characteristics, the centralized control FPGA calculates the difference between the current real-time beam control pattern and the ideal pattern, i.e., the pattern deviation, which characterizes the actual error of this beamforming operation.

[0109] Furthermore, the preset beam pattern representation specification is the theoretical gold standard guiding the centralized control FPGA in deviation evaluation; it is determined during the mission planning phase. This beam pattern representation specification details all the ideal electromagnetic characteristics that the beam pattern should satisfy at a specific target pointing angle, including but not limited to:

[0110] Ideal pointing vector: Defines the spatial angle at which the main lobe center should be precisely aligned; Amplitude weighting function: Specifies the ideal amplitude weights of each array element (e.g., Taylor weighting or Chebyshev weighting) to achieve the desired sidelobe level; Phase distribution function: Specifies the theoretical phase distribution that each array element should possess after eliminating spatial errors to ensure the accuracy of the main lobe pointing; Performance threshold: The allowable range of pattern characteristics, such as the required main lobe pointing accuracy (e.g., less than 0.05°RMS), peak sidelobe level (e.g., less than -30dB), and null depth, etc.

[0111] The centralized control FPGA precisely compares the pattern characteristic indicators extracted from the pattern measurement feedback data with the various performance thresholds in the preset pattern representation specification, thereby quantitatively calculating the pattern deviation.

[0112] The radiation pattern deviation is correlated with the final element beam control weights for the current cycle, and the amplitude contribution error and phase contribution error are calculated according to the element dimension to form the initial error signal.

[0113] It should be noted that the centralized control FPGA uses a sensitivity analysis model to perform correlation analysis on the radiation pattern deviation; it links the radiation pattern deviation with the final array element beam control weights used in this operation to determine which array elements, and the amplitude or phase changes of the array elements, contribute the most to the final deviation; through this correlation analysis, the centralized control FPGA reverse-calculates the actual deviation of each array element in amplitude and phase according to the array element dimension, forming the initial error signal;

[0114] Furthermore, a linear array theoretical model is adopted as the theoretical basis for the sensitivity analysis model. To ensure that this linear array theoretical model accurately reflects the complex hardware and environmental characteristics of the actual array, system identification technology is used for real-time training and calibration. Within the stable operating range of the array, small, known amplitude and phase correction increments are periodically sent to some array elements as input perturbations. Simultaneously, the actual real-time beam control pattern is acquired through a specific monitoring receiver, and the actual pattern deviation is calculated as the output response. Using these measured input perturbation and output response data pairs, combined with algorithms such as minimum mean square error or recursive least squares, the sensitivity analysis model is iteratively corrected until it converges to a more accurate actual sensitivity matrix. After training, the sensitivity analysis model can accurately and efficiently correlate and analyze the observed pattern deviations, and reverse-calculate the amplitude contribution error and phase contribution error in each array element dimension.

[0115] The sensitivity analysis model, trained and calibrated using system identification technology, is stored as the actual sensitivity matrix within the centralized control FPGA. During the correlation analysis phase, the centralized control FPGA transforms the real-time beam control pattern deviation assessment result—the pattern deviation—into a structured error vector. Subsequently, using its built-in correlation analysis logic, it performs an inverse linear operation on this error vector and the actual sensitivity matrix. Through this inverse linear operation, the centralized control FPGA can accurately calculate the actual amplitude and phase deviations of each array element along the element dimension, thus forming a precise set of amplitude contribution errors and phase contribution errors—the initial error signal.

[0116] The initial error signal is synchronously compared with the instantaneous array operating state of the current cycle, and the initial error signal is corrected and compensated in the time domain according to the historical error change pattern of the array in the stable operating range.

[0117] Specifically, the centralized control FPGA performs real-time synchronous comparison between the initial error signal and the current instantaneous array operating status (such as temperature, voltage, and drive current) reflected in the array operation monitoring information. Simultaneously, it reviews stored historical error change patterns (e.g., typical drift trends of the array at specific temperatures or aging levels) to distinguish which parts of the initial error signal are long-term errors caused by system drift, thermal noise, or nonlinear effects, and which are instantaneous errors. Time-domain correction and compensation using Kalman filtering and exponentially weighted moving average algorithms smooth and filter unstable components in the initial error signal based on historical patterns and instantaneous states, ensuring that the final error feedback is stable and representative.

[0118] The corrected error signal is used as the array amplitude and phase error for the next control cycle and written into the error update register, so that it serves as the error reference for the amplitude and phase correction increment solution process in the next control cycle.

[0119] Specifically, after time-domain correction and compensation, the corrected error signal is determined as the array amplitude and phase error for the next control cycle. The centralized control FPGA writes this array amplitude and phase error into a specific internal error update register. This written error data will serve as the input error reference for the incremental adaptive correction core to calculate the new amplitude and phase correction increment at the beginning of the next control cycle, thus realizing closed-loop correction and adaptive adjustment of the entire beam control system.

[0120] When the local frame counter reaches the target effective frame number, the methods for triggering a register group switch at a single time slot boundary include:

[0121] The array front-end element FPGA continuously receives the global synchronization clock from the centralized control FPGA and runs the local frame counter through clock synchronization logic to ensure that the counters of all elements are strictly aligned with the frame timing of the centralized control FPGA.

[0122] It should be noted that the clock synchronization logic is based on a reference clock, which is generated uniformly by the centralized control FPGA and distributed to all array front-end element FPGAs through a dedicated clock distribution network or synchronization signal link. At the receiving end, the clock synchronization logic within each element FPGA uses hardware modules such as phase-locked loops (PLLs) or delay-locked loops (DLLs) to perform jitter removal, deskewing, and frequency reconstruction on the received global synchronization clock to generate a high-purity local working clock; this local working clock drives the counting of the local frame counter. Through this high-precision synchronization mechanism, the local frame counter of the array front-end element FPGA is strictly aligned with the frame timing of the centralized control FPGA on the time boundary, ensuring time consistency in the identification of the target active frame number by all elements.

[0123] The array front-end element FPGA performs real-time cycle-by-cycle comparison between the value of the local frame counter and the target effective frame number carried in the incremental differential beam control message; when the value of the local frame counter is equal to the target effective frame number, the array element FPGA immediately triggers the control signal when it receives the rising edge of the next clock cycle.

[0124] It should be noted that the digital comparator inside the FPGA compares the current value of the local frame counter with the target active frame number temporarily stored in the register cycle by cycle. Once the comparison result is equal, the comparator generates a pre-trigger indication within the current clock cycle. This indication signal is strictly aligned with the rising edge of the next global synchronization clock. The FPGA uses this rising edge as an indivisible single time slot boundary to immediately trigger a high-level or pulse-type control signal.

[0125] The trigger control signal acts simultaneously on the pre-update register and the locally stored old beam control weights in the front-end array element; causing the amplitude and phase correction increments and the old beam control weights to unlock at the same time and enter the fusion path synchronously.

[0126] It should be noted that the control signal (at a single time slot boundary) is allocated to the output enable ports of two key storage areas: one is the pre-update register for buffering amplitude and phase correction increments, and the other is the register group storing the old beam control weights from the previous cycle. Since this control signal acts synchronously and atomically on both, it simultaneously unlocks the two data sources. This operation ensures that the buffered amplitude and phase correction increments (i.e., amplitude compensation and phase compensation) and the locally stored old beam control weights (i.e., old amplitude control and old phase control) are pushed and synchronously entered into the fusion path at the same time, laying a strict atomic switching foundation for the subsequent weight synthesis step.

[0127] This embodiment also provides a centralized phased array beam control system based on FPGA, including:

[0128] The acquisition module is used to acquire phased array operation monitoring information through centralized control FPGA, perform array error estimation, obtain array amplitude and phase error, and generate reference beam pointing weights according to beam control tasks.

[0129] The incremental calculation module is used to perform real-time iterative calculations based on the reference beam pointing weight and the array amplitude and phase error through the incremental adaptive correction kernel in the centralized control FPGA to obtain the amplitude and phase correction increment and the corresponding target effective frame number.

[0130] The message generation module is used to perform incremental differential encoding on the amplitude and phase correction increment and the corresponding target effective frame number in the centralized control FPGA to generate incremental differential beam control messages.

[0131] The synchronous fusion module is used to send incremental differential beam control messages to the array front-end element FPGA, perform frame-level atomic switching according to the target effective frame number, and fuse the amplitude and phase correction increment with the old beam control weights stored locally during the switching process to obtain the final element beam control weights.

[0132] The update module is used to generate a real-time beam control pattern based on the final array element beam control weights; and to update the array amplitude and phase error for the next control cycle based on the real-time beam control pattern.

[0133] This embodiment also provides a computer device applicable to the centralized phased array beam control method based on FPGA, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the centralized phased array beam control method based on FPGA as proposed in the above embodiment.

[0134] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0135] This embodiment also provides a storage medium storing a computer program that, when executed by a processor, implements the FPGA-based centralized phased array beam control method as proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0136] In summary, this invention achieves smooth, gradual compensation and precise time alignment of control commands by using a centralized control FPGA with an incremental adaptive correction kernel for small-step iterations to generate amplitude and phase correction increments containing only necessary changes and pre-planned target effective frame numbers. This effectively improves the stability and convergence accuracy of beam control and reduces the bandwidth requirements of the control link. Simultaneously, by triggering frame-level atomic switching on the array front-end FPGA based on the target effective frame number, the received increments are instantaneously fused with the local old weights at strictly synchronized time slot boundaries. This ensures strict synchronization, phase consistency, and update reliability of beam state switching for all elements of a large-scale phased array. Thus, while guaranteeing high-precision beamforming quality, this invention solves the key problems of massive control data volume and difficult real-time synchronization.

[0137] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A centralized phased array beam control method based on FPGA, characterized in that, include: By centrally controlling the FPGA, the phased array operation monitoring information is obtained to perform array error estimation and obtain the array amplitude and phase error. At the same time, according to the beam control task, the reference beam pointing weight is generated. Based on the reference beam pointing weight and the array amplitude and phase error, the incremental adaptive correction kernel in the centralized control FPGA performs real-time iterative calculations to obtain the amplitude and phase correction increment and the corresponding target effective frame number. The amplitude and phase correction increments and the corresponding target effective frame numbers are incrementally differentially encoded in the centralized control FPGA to generate incremental differential beam control messages. The incremental differential beam control message is sent to the array front-end element FPGA. According to the target effective frame number, the frame-level atomic switching is performed. During the switching process, the amplitude and phase correction increment is fused with the old beam control weights stored locally to obtain the final array element beam control weights. Based on the final array element beam control weights, a real-time beam control pattern is generated; and the array amplitude and phase errors for the next control cycle are updated according to the real-time beam control pattern.

2. The FPGA-based centralized phased array beam control method as described in claim 1, characterized in that, The method for obtaining the array amplitude and phase error and the reference beam pointing weight includes: Based on the phased array operation monitoring information, the FPGA is centrally controlled to perform amplitude and phase error calculation, obtain the amplitude deviation and phase change of the array elements, and obtain the array amplitude and phase error; Based on the pointing requirements of the beam control task, the centralized control FPGA, combined with the array's geometric layout and target pointing angle, determines the amplitude and phase pointing reference that each array element should have in this cycle, and generates the reference beam pointing weights.

3. The FPGA-based centralized phased array beam control method as described in claim 2, characterized in that, The method for obtaining the amplitude and phase correction increment and the corresponding target effective frame number includes: The centralized control FPGA performs element-by-element amplitude and phase differential calculations on the reference beam pointing weights and the array amplitude and phase errors to extract error information. Based on error information, the centralized control FPGA calls its internal incremental adaptive correction core, and gradually adjusts the amplitude compensation and phase compensation of each array element according to the current working state of the array and the error change trend. The amplitude and phase correction increment that conforms to the current control cycle is obtained through multiple rounds of small step iteration. The centralized control FPGA, combined with the link transmission delay, the FPGA switching rhythm of the array elements, and the refresh frequency of the beam control task, performs time alignment evaluation on the amplitude and phase correction increment to determine the target effective frame number corresponding to the amplitude and phase correction increment.

4. The FPGA-based centralized phased array beam control method as described in claim 3, characterized in that, The method for generating incremental differential beam control messages includes: The centralized control FPGA uses the old beam control weights of the previous cycle of the array element as the differential reference to calculate the amplitude and phase difference of each array element based on the amplitude and phase compensation amount. The difference between the new and old amplitude and phase control amounts is quantized, compressed and reorganized into fields, and expressed in the incremental form of the minimum necessary amplitude and phase change amount to form an amplitude and phase correction increment suitable for low bandwidth link transmission. The amplitude and phase correction increments suitable for low-bandwidth link transmission are structured and organized with the target effective frame number in frame order; by combining the amplitude increment domain, phase increment domain, and effective frame number domain, a compact incremental differential code is formed, reducing the amount of data sent for beam control parameters. The structured fields of incremental differential encoding are encapsulated into downlink-parseable incremental differential beam control messages.

5. The FPGA-based centralized phased array beam control method as described in claim 4, characterized in that, The execution of frame-level atomic switching includes: The incremental differential beam control message is sent to the array front-end element FPGA via the downlink; after receiving the incremental differential beam control message, the amplitude compensation amount and phase compensation amount in it are cached in the pre-update register, and compared with the local frame counter according to the target effective frame number carried in the message. When the local frame counter reaches the target effective frame number, a register group switch is triggered at the boundary of a single time slot, so that the buffered amplitude and phase correction increments and the old beam control weights stored locally are synchronized into the fusion path.

6. The FPGA-based centralized phased array beam control method as described in claim 5, characterized in that, The method for obtaining the final array element beam control weights includes: Within the same time slot boundary where the register group completes the switching, the amplitude and phase correction increments that will be synchronously entered into the fusion path will be synthesized item by item in the amplitude and phase domains with the old beam control weights of the previous cycle stored locally, according to the array element correspondence. Amplitude and phase domain fusion is achieved by adding amplitude compensation to the old amplitude control and phase compensation to the old phase control, resulting in the final array element beam control weights that conform to the current target effective frame number.

7. The FPGA-based centralized phased array beam control method as described in claim 6, characterized in that, The method for generating a real-time beam control pattern includes: The final array element beam control weights are loaded in parallel to the amplitude control unit and phase control unit of all transceiver components in the array through the control interface of the front-end array element FPGA. The transceiver component is driven by the digital control circuit built into it, which converts the final array element beam control weights into digital adjustment parameters required by the radio frequency link, and adjusts the signal amplitude and phase of each array element to obtain the radio frequency signal. Radio frequency signals are spatially synthesized to form an electromagnetic beam with target pointing and desired pattern characteristics in free space, and the real-time beam control pattern for the current control cycle is output.

8. The FPGA-based centralized phased array beam control method as described in claim 7, characterized in that, The step of updating the array amplitude and phase error for the next control cycle based on the real-time beam control pattern includes: The centralized control FPGA evaluates the deviation of the real-time beam control pattern, compares the pattern characteristic index with the corresponding index of the preset pattern expression specification, and obtains the pattern deviation. The radiation pattern deviation is correlated with the final element beam control weights of the current cycle, and the amplitude contribution error and phase contribution error are calculated according to the element dimension to form the initial error signal. The initial error signal is synchronously compared with the instantaneous array operating state of the current period, and the initial error signal is corrected and compensated in the time domain according to the historical change pattern of the array error in the stable operating range. The corrected error signal is used as the array amplitude and phase error for the next control cycle and written into the error update register, so that it serves as the error reference for the amplitude and phase correction increment solution process in the next control cycle.

9. The FPGA-based centralized phased array beam control method as described in claim 5, characterized in that, The method for triggering register group switching at a single time slot boundary when the local frame counter reaches the target effective frame number includes: The array front-end element FPGA continuously receives the global synchronization clock from the centralized control FPGA and runs the local frame counter through the clock synchronization logic to ensure that the counters of all elements are strictly aligned with the frame timing of the centralized control FPGA. The array front-end element FPGA performs real-time cycle-by-cycle comparison between the value of the local frame counter and the target effective frame number carried in the incremental differential beam control message; when the value of the local frame counter is equal to the target effective frame number, the array element FPGA immediately triggers the control signal when it receives the rising edge of the next clock cycle. The trigger control signal acts simultaneously on the pre-update register and the locally stored old beam control weights in the front-end array element; causing the amplitude and phase correction increments and the old beam control weights to unlock at the same time and enter the fusion path synchronously.

10. A centralized phased array beam control system based on FPGA, based on the centralized phased array beam control method based on FPGA as described in any one of claims 1 to 9, characterized in that, include: The acquisition module is used to acquire phased array operation monitoring information through centralized control FPGA, perform array error estimation, obtain array amplitude and phase error, and generate reference beam pointing weights according to beam control tasks. The incremental calculation module is used to perform real-time iterative calculations based on the reference beam pointing weight and the array amplitude and phase error through the incremental adaptive correction kernel in the centralized control FPGA to obtain the amplitude and phase correction increment and the corresponding target effective frame number. The message generation module is used to perform incremental differential encoding on the amplitude and phase correction increment and the corresponding target effective frame number in the centralized control FPGA to generate incremental differential beam control messages. The synchronous fusion module is used to send incremental differential beam control messages to the array front-end element FPGA, perform frame-level atomic switching according to the target effective frame number, and fuse the amplitude and phase correction increment with the old beam control weights stored locally during the switching process to obtain the final element beam control weights. The update module is used to generate a real-time beam control pattern based on the final array element beam control weights. The array amplitude and phase error for the next control cycle is updated based on the real-time beam control pattern.

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