Resource allocation method, processor and computing platform

Abstract

The invention discloses a resource allocation method, a processor and a computing platform, which are used for improving the resource utilization rate of chips including a GPU (Graphics Processing Unit), an NPU (Network Processing Unit) and the like and reducing the chip area and static power consumption loss. The processor comprises a computing unit pool, and the computing unit pool comprises a plurality of computing units; each idle computing unit in the plurality of computing units can be called as required, and the number of different types of computing units in the plurality of computing units is positively correlated with the calling times of the type of computing units. According to the method, the computing units in the processing chips including the NPU, the GPU and the like are pooled, so that each computing unit can be called by an upper-layer application as required when the computing unit is idle, the resource utilization rate can be improved, the static power consumption loss of the computing units is reduced, and the chip area is reduced.

Description

Resource allocation method, processor and computing platform Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a resource allocation method, a processor, and a computing platform. Background Art

[0002] With the rise of fields such as machine learning, artificial intelligence (AI), autonomous driving, and industrial simulation, general-purpose processors (such as central processing units (CPUs)) are increasingly encountering performance bottlenecks when processing massive amounts of computation and massive amounts of data / images, such as low parallelism, insufficient bandwidth, and high latency. To meet the demands of diversified computing, more and more scenarios are introducing chips such as graphics processing units (GPUs) or neural processing units (NPUs), which together with general-purpose processors form heterogeneous computing platforms. Chips such as NPUs and GPUs contain a variety of computing resources, such as tensor computing units, vector computing units, and scalar computing units. In the NPUs and GPUs produced by existing chip manufacturers, the proportions of various types of computing resources are fixed, and the same computing resources are replicated many times.

[0003] For example, see Figure 1, which shows the Xavier system-on-chip (SoC) schematic, including a GPU, CPU, vision accelerator, deep learning accelerator (DLA), video encoder, video decoder, camera ingest, and internet service provider (ISP). The GPU includes multiple independent streaming multiprocessors (SMs), each of which contains a compute unified device architecture (CUDA) core, and each CUDA core contains a variety of computing units. Moreover, various mathematical operations (such as exponential (exp), reciprocal (1 / x), logarithm (log), square root (sqrt), addition (add), subtraction (sub), multiplication (mul), etc.) correspond to separate physical computing units; even in order to meet different data types (such as 8-bit integers (int8), 16-bit floating-point numbers (fp16), 32-bit floating-point numbers (fp32), 4-bit integers (int4), etc.), computing units of various specifications are placed, which require stacking multiple resources in CUDA Core.

[0004] For example, see Figure 2, which shows a schematic diagram of the Huawei Ascend chip SoC, including the NPU, CPU, task scheduler, network card, universal serial bus (USB) interface, external memory interface, high-speed serial computer expansion bus (PCIE) interface, general-purpose input / output (GPIO) interface, etc. The NPU includes multiple AI cores, and each AI core is internally stacked with the same computing resources, such as the same type and number of tensor computing units and vector computing units.

[0005] However, in actual applications, not all computing resources of NPU, GPU and other chips are used at the same time when they are running. Therefore, the design methods of NPU, GPU and other chips in the existing technology not only waste chip area, but also have the problem of static power consumption loss.

[0006] How to improve the resource utilization of chips including NPU, GPU, etc. is the problem to be solved in this application.

[0007] Summary of the Invention

[0008] The present application provides a resource allocation method, processor, and computing platform to improve resource utilization of chips including GPUs, NPUs, etc., and reduce chip area and static power consumption losses.

[0009] In a first aspect, a processor is provided, which includes a computing unit pool, which includes multiple computing units; each idle computing unit in the multiple computing units can be called on demand, and the number of different types of computing units in the multiple computing units is positively correlated with the number of times the computing unit of that type is called.

[0010] It can be understood that the processor can be a processing chip for implementing parallel computing, such as an NPU or a GPU or other processing chips for implementing parallel computing.

[0011] This application pools the computing units in processing chips including NPU and GPU for implementing large-scale parallel computing, so that each computing unit can be called on demand by upper-level applications when it is idle, which can improve resource utilization, reduce static power consumption loss of computing units, and reduce chip area.

[0012] In one possible design, all computing units in the processor are pooled, that is, all computing units in the processor are included in the computing unit pool.

[0013] All computing units of the processor are pooled, which can minimize the static power consumption loss of the processor and reduce the chip area.

[0014] In another possible design, only some of the computing units in the processor are pooled, that is, only some of the computing units are included in the computing unit pool.

[0015] Pooling some of the processor's computing units can reduce static power consumption and reduce the processor's chip area. At the same time, retaining a small number of computing units without pooling (for example, in the form of AI cores) can ensure good forward compatibility of the processor.

[0016] In one possible design, the types correspond to the algorithms executed by the multiple computing units. In other words, the types of computing units can be divided according to the algorithms they execute. For example, a computing unit that executes an addition algorithm is of type add computing unit, a computing unit that executes a logarithm algorithm is of type log computing unit, and so on.

[0017] In one possible design, each of the multiple computation units corresponds to a low-level arithmetic instruction. For example, the add computation unit corresponds to the addition instruction, and the log computation unit corresponds to the log instruction. It is understood that in actual applications, different computation units may correspond to the same low-level arithmetic instruction. The scale of the low-level arithmetic operation varies depending on the processor's capabilities and is specifically designed based on the processor's chip specifications. The same low-level arithmetic instruction may be executed in parallel by multiple computation units at the low level.

[0018] In one possible design, the computing unit pool includes one or more of a tensor computing unit pool, a vector computing unit pool, and a scalar computing unit pool.

[0019] Pooling tensor computing units, vector computing units, and scalar computing units separately can improve resource management efficiency and the efficiency of resource scheduling by upper-layer applications.

[0020] In one possible design, the processor is used to: receive a request to execute a first application; determine the computing resource requirements of the first application, and allocate computing units to the first application from a computing unit pool based on the computing resource requirements to implement the first application, where the computing resource requirements include one or more of tensor computing units, vector computing units, and vector computing units, as well as the number of each type of computing units.

[0021] Through the above method, it is possible to dynamically schedule resources for upper-layer applications according to their requests, thereby improving the flexibility of resource allocation and increasing resource utilization.

[0022] In one possible design, the processor is also used to: determine multiple processes corresponding to the first application; determine the computing resource requirements of each of the multiple processes, and allocate computing units to each process from a computing unit pool based on the computing resource requirements of each process to implement the first application; wherein the computing units allocated to each process are different from the computing units allocated to other processes.

[0023] Through the above manner, it is possible to allocate a computing unit from the computing unit pool to each process of the first application according to the computing resource requirements of each process, thereby improving resource utilization.

[0024] In one possible design, the processor is also used to: determine whether the computing unit allocated to the first application meets the needs of the first application; when the computing unit allocated to the first application cannot meet the needs of the first application, adjust the computing resource allocation result of the first application, and allocate a computing unit to the first application from the computing unit pool based on the adjusted computing resource allocation result.

[0025] In one possible design, the processor is further configured to establish a correspondence between the first application and a computing unit allocated to the first application.

[0026] Through the above manner, it can be ensured that the resources allocated to the first application can meet its needs, and the reliability of resource allocation can be improved.

[0027] In a second aspect, a resource allocation method is provided, which is applied to a processor, wherein the processor includes a computing unit pool, and the computing unit pool includes multiple computing units; each idle computing unit in the multiple computing units can be called on demand, and the number of different types of computing units in the multiple computing units is positively correlated with the number of times the computing unit of that type is called; the method includes: receiving a request to execute a first application; determining the computing resource requirements of the first application, and allocating computing units to the first application from the computing unit pool according to the computing resource requirements to implement the first application, wherein the computing resource requirements include one or more of tensor computing units, vector computing units, and vector computing units, and the number of each type of computing units.

[0028] In one possible design, the computing resource requirements of a first application are determined, and computing units are allocated to the first application from a computing unit pool based on the computing resource requirements to implement the first application, including: determining multiple processes corresponding to the first application; determining the computing resource requirements of each of the multiple processes, and allocating computing units to each process from a computing unit pool based on the computing resource requirements of each process to implement the first application; wherein the computing units allocated to each process are different from the computing units allocated to other processes.

[0029] In one possible design, the method also includes: determining whether the computing unit allocated to the first application meets the needs of the first application; when the computing unit allocated to the first application cannot meet the needs of the first application, adjusting the computing resource allocation result of the first application, and allocating a computing unit to the first application from the computing unit pool based on the adjusted computing resource allocation result.

[0030] In one possible design, the method further includes: establishing a correspondence between the first application and the computing unit allocated to the first application.

[0031] In a third aspect, a processing device is provided, which includes modules / units / technical means for executing the method described in the second aspect or any possible design of the second aspect.

[0032] Exemplarily, the device may include: a transceiver module for receiving a request to execute a first application; a processing module for determining the computing resource requirements of the first application, and allocating computing units to the first application from the computing unit pool of the processor according to the computing resource requirements to implement the first application, wherein the computing resource requirements include one or more of tensor computing units, vector computing units, and vector computing units, and the number of each computing unit; wherein the computing unit pool includes multiple computing units; each idle computing unit in the multiple computing units can be called on demand, and the number of different types of computing units in the multiple computing units is positively correlated with the number of times the computing unit of that type is called.

[0033] In one possible design, the processing module can also be used to: determine multiple processes corresponding to the first application; determine the computing resource requirements of each of the multiple processes, and allocate computing units to each process from the computing unit pool based on the computing resource requirements of each process to implement the first application; wherein the computing units allocated to each process are different from the computing units allocated to other processes.

[0034] In one possible design, the processing module can also be used to: determine whether the computing unit allocated to the first application meets the needs of the first application; when the computing unit allocated to the first application cannot meet the needs of the first application, adjust the computing resource allocation result of the first application, and allocate computing units to the first application from the computing unit pool based on the adjusted computing resource allocation result.

[0035] In one possible design, the processing module may also be used to establish a correspondence between the first application and the computing unit allocated to the first application.

[0036] In a fourth aspect, a computing platform is provided, comprising the processor described in the first aspect and the processing device described in the third aspect.

[0037] In a fifth aspect, a computer-readable storage medium is provided, which stores computer-executable instructions. When the computer-executable instructions are called by a computer, the method described in the second aspect or any possible design of the second aspect is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG1 is a schematic diagram of a SoC;

[0039] FIG2 is a schematic diagram of another SoC;

[0040] FIG3 is a schematic diagram of a processor provided in an embodiment of the present application;

[0041] Figure 4 is a schematic diagram of all computing units in the NPU being pooled;

[0042] Figure 5 is a schematic diagram showing that some computing units in the NPU are pooled;

[0043] FIG6 is a statistical diagram of the frequency of use of operators;

[0044] FIG7 is a flow chart of a resource allocation method provided in an embodiment of the present application;

[0045] FIG8A is a schematic diagram of a possible resource allocation provided in an embodiment of the present application;

[0046] FIG8B is a schematic diagram of another possible resource allocation provided in an embodiment of the present application;

[0047] FIG9 is a schematic diagram of a possible computing unit pool 11 provided in an embodiment of the present application;

[0048] FIG10 is a schematic diagram of a processing device provided in an embodiment of the present application;

[0049] FIG11 is a schematic diagram of a computing platform provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0051] Referring to FIG. 3 , which is a schematic diagram of a processor 01 provided in an embodiment of the present application, the processor 01 includes a computing unit pool 11 , and the computing unit pool 11 includes a plurality of computing units 111 .

[0052] It can be understood that the computing units in the computing unit pool 11 are pooled computing units, or computing units that can be shared, for example, they can be called by different upper-layer applications. In specific implementation, for each computing unit in the computing unit pool 11, when it is not called (or not running), it is an idle computing unit and can be called by an upper-layer application. Each idle computing unit in the multiple computing units 111 can be called on demand, for example, according to the needs of the upper-layer application, that is, if any upper-layer application needs it, and there is an idle computing unit in the computing unit pool 11, then the idle computing unit can be called by the upper-layer application.

[0053] The processor 01 may be a processing chip for implementing parallel computing, such as an NPU or GPU, or other processing chips for implementing parallel computing. The multiple computing units 111 in the computing unit pool 11 may be computing units in a chip for implementing parallel computing, such as computing units in an NPU or GPU. In other words, the computing unit pool 11 may be obtained by pooling computing units in an NPU or GPU, or other processing chips for implementing parallel computing.

[0054] The above solution pools the computing units in processing chips used for massive parallel computing, including NPUs and GPUs, so that each computing unit can be called on demand by upper-layer applications when it is idle. Compared with the existing technology of stacking multiple identical computing resources in designs such as SMs or AI Cores, it can improve resource utilization. Under the condition of the same resource usage, the static power consumption loss of the computing units can be reduced, reducing the chip area of ​​processor 01.

[0055] For ease of description, the following mainly uses NPU as an example for description, but the same implementation can be applied to other chips such as GPU.

[0056] In one possible design, all computing units in the NPU are pooled, that is, all computing units in the NPU are included in computing unit pool 11. For example, as shown in Figure 4, all computing units 111 in the NPU are in computing unit pool 11. In other words, every idle computing unit in all computing units of the NPU can be called on demand.

[0057] In the above manner, all computing units of the NPU are pooled, which can minimize the static power consumption loss of the processor 01 and reduce the chip area of ​​the processor 01.

[0058] In another possible design, only some of the computing units in the NPU are pooled, that is, only some of the computing units are included in the computing unit pool 11. For example, as shown in Figure 5, some computing units 111 in the NPU are in the computing unit pool 11, while other computing units 111 are not in the computing unit pool 11 but are configured in the AI ​​Core.

[0059] In this way, some computing units of the NPU are pooled, which can reduce static power consumption and reduce the chip area of ​​processor 01. At the same time, a small number of computing units are retained in the form of AI cores, which can ensure good forward compatibility of processor 01.

[0060] In one possible design, the computing unit pool 11 may include different types of computing units, where the computing unit type corresponds to the algorithm executed by the computing unit. The number of different types of computing units 111 in the multiple computing units 111 is positively correlated with the number of times the computing unit 111 of that type is called. In other words, the more times a computing unit 111 of a certain type is called, the greater its number in the computing unit pool 11. Alternatively, the more times an algorithm is called, the greater the number of computing units 111 corresponding to that algorithm in the computing unit pool 11. For example, if the add computing unit is called more often, then there can be more add computing units in the computing unit pool 11, and if the log computing unit is called less often, then there can be fewer log computing units in the computing unit pool 11.

[0061] In a specific implementation, each computing unit 111 corresponds to a bottom-level operation instruction of the processor 01. In other words, each computing unit 111 in the multiple computing units 111 corresponds to a bottom-level operation instruction. It is understandable that in actual applications, different computing units 111 can correspond to the same bottom-level operation instruction, and the scale of the bottom-level operation varies according to the capabilities of the processor 01, and is specifically designed according to the chip specifications of the processor 01. For example, for an add instruction, when the amount of data to be processed corresponding to the instruction is large, in order to improve the processing power (i.e., parallelism) of the processor 01 at the same time, multiple add computing units can perform parallel calculations on different data at the bottom level. Therefore, for the same add instruction, the bottom level may perform multiple additions.

[0062] As an example, the proportion of various computing units used by various operators in the model (such as a neural network model) run by the processor 01 in actual applications can be analyzed and statistically analyzed, and the number of various computing units in the computing resource pool 11 can be configured according to the resource requirements that meet actual requirements. It is understandable that one operator can correspond to one or more computing units 111.

[0063] For example, see Figure 6, which is a statistical chart of the usage frequency of various operators in the model. The functions of each operator in Figure 6 are explained as follows:

[0064] Conv: convolution;

[0065] Relu: rectified linear unit;

[0066] Dequant: Dequantization;

[0067] Mul: multiplication;

[0068] Slice: Slice;

[0069] Gather: gather;

[0070] Shape: plastic surgery;

[0071] BatchNormalization: batch normalization;

[0072] Resize: zoom;

[0073] Pad: data expansion;

[0074] ConstantOfShape: Generates a tensor with a given value and shape;

[0075] Tanh: activation function;

[0076] LeakyRelu: leaky retified linear unit;

[0077] GlobalAveragePool: global average pooling;

[0078] Floor: round down;

[0079] ConvTranspose: transposed convolution, also known as Deconvolution;

[0080] Softmax: normalization;

[0081] Exp: exponent;

[0082] Flatten: dimensionality reduction;

[0083] Equal: determines whether the sequence is equal;

[0084] Expand: expand;

[0085] MatMul: matrix multiplication operation;

[0086] And: AND operation;

[0087] ReduceMean: reduction layer in convolutional neural networks;

[0088] ReduceMax: Take the maximum value.

[0089] It is understandable that FIG6 only shows some operator types. In actual applications, there may be other operator types, and this application does not limit them.

[0090] As can be seen from Figure 6, the usage frequency of operators such as Conv, Relu, AscendDequant is relatively high. Therefore, more computing units 111 can be configured for operators such as Conv, Relu, AscendDequant in the computing unit pool 11, while the usage frequency of operators such as Softmax, Exp, Flatten, Equal, Expand, MatMul, And, ReduceMean, ReduceMax is relatively low. Therefore, fewer computing units 111 can be configured for operators such as Conv, Relu, AscendDequant in the computing unit pool 11.

[0091] It is understandable that, in specific implementations, the actual number of each type of computing unit 111 may be slightly greater than the number corresponding to the number of times that type of computing unit 111 is called, to ensure that the processor 01 has sufficient performance to cope with emergencies.

[0092] This design approach, by configuring the number of different types of computing units 111 in the computing unit pool 11 to be positively correlated with the number of times the computing unit 111 of that type is called, can reduce the static power consumption loss of the processor 01 while ensuring the operating performance of the processor 01.

[0093] It should be noted that the above is to distinguish the types of computing units 111 based on the underlying operation instructions (or the algorithm type executed by the computing unit 111, or the mathematical operation type performed by the computing unit 111). In actual application, the computing units 111 can also be classified based on other aspects.

[0094] In a possible example, based on the algorithm dimension, the multiple computing units 111 may include one or more types of tensor computing units (or matrix computing units) 111A, vector computing units (or vector computing units) 111B, and scalar computing units 111C. The tensor computing unit 111A is used to perform matrix calculations, the vector computing unit 111B is used to perform vector calculations, and the scalar computing unit 111C is used to perform scalar calculations.

[0095] In another possible example, in one possible example, based on the data type corresponding to the algorithm, multiple computing units 111 may include one or more types of eight-bit integer (int8) computing units, 16-bit floating-point (fp16) computing units, 32-bit floating-point (fp32) computing units, 4-bit integer (int4) computing units, etc.

[0096] It can be understood that the above methods of dividing computing unit types are only examples and not limitations, and there are actually other division methods.

[0097] In practical applications, the above-mentioned classification methods can be combined with each other. For example, all computing units 11 are first divided into tensor computing units 111A, vector computing units 111B, and scalar computing units 111C, and then further subdivided according to mathematical operation type and / or data type within the tensor computing unit 111A.

[0098] In one possible design, the processor 01 may schedule resources for the upper-layer application from the computing unit pool 11 upon receiving a request from the upper-layer application.

[0099] For example, see FIG7 , which is a flowchart of a resource allocation method provided in an embodiment of the present application. The method can be executed by the processor 01 in FIG3 , or by another processing device other than the processor 01. The method includes:

[0100] S701: Receive a request to execute a first application;

[0101] S702. Determine the computing resource requirements of the first application; allocate computing units to the first application from the computing unit pool according to the computing resource requirements to implement the first application, where the computing resource requirements include one or more of tensor computing units, vector computing units, and vector computing units, as well as the number of each type of computing units.

[0102] When the above method is executed by the processor 01, it can be specifically the NPU in the processor 01 or other processing units specially configured to implement resource allocation to execute the above method, and this application does not impose any restrictions.

[0103] Optionally, you can first determine multiple processes corresponding to the first application; then determine the computing resource requirements of each of the multiple processes, and allocate a computing unit to each process from a computing unit pool based on the computing resource requirements of each process to implement the first application; wherein the computing unit allocated to each process is different from the computing units allocated to other processes, in other words, different processes in the multiple processes are allocated to different computing units.

[0104] As an example, see Figure 8A, which is a schematic diagram of possible resource allocation. During the chip design phase, resources such as add, sub, mul, and exp are each placed in processor 01, with multiple copies of matrix multiplication. Assume that application 0 and application n are to be executed simultaneously, where application 0 requires the computing resources matrix multiplication, add, and sub, and application n requires the computing resources matrix multiplication, mul, and exp. When allocating resources, the resources allocated to application 0 can be as shown in resource group 0, including matrix multiplication, add, and sub, and the resources allocated to application n can be as shown in resource group n, including matrix multiplication, mul, and exp. In this way, different types of computing resources can be allocated to different applications, achieving the goals of reducing chip area, reducing costs, and reducing static power consumption, while not reducing the chip's processing performance.

[0105] As an example, see Figure 8B, which is a schematic diagram of another possible resource allocation. During the chip design phase, two copies of each of the resources, such as add, sub, mul, and exp, are placed in processor 01, while multiple copies are placed in matrix multiplication. Assuming that application 0 and application n are to be executed simultaneously, where application 0 has a high demand for add and application n has a low demand for add, when allocating resources, the resources allocated to application 0 can be as shown in resource group 0, including matrix multiplication, add, sub, mul, and exp, with two copies of add. The resources allocated to application n can be as shown in resource group n, including matrix multiplication, sub, mul, and exp. In this way, different amounts of computing resources can be allocated to different applications, achieving the goals of reducing chip area, reducing costs, and reducing static power consumption, while not reducing the chip's processing performance.

[0106] Through this design, resources can be dynamically scheduled according to the requests of upper-layer applications, improving the flexibility of resource allocation.

[0107] In one possible design, after allocating computing units to the first application from the computing unit pool based on computing resource requirements, it can also be determined whether the computing units allocated to the first application meet the needs of the first application; when the computing units allocated to the first application cannot meet the needs of the first application, the computing resource allocation result of the first application is adjusted, and computing units are allocated to the first application from the computing unit pool 11 based on the adjusted computing resource allocation result.

[0108] For example, if the computing unit 111a allocated to the first application cannot meet the indicators required by the first application (such as latency) during calculation, the computing resource allocation result of the first application is adjusted, and more computing units, such as computing units 111b and 111c, are allocated to the first application to meet the indicators required by the first application.

[0109] Through the above approach, it can be ensured that the resources allocated to the first application can meet its needs, thereby improving the reliability of resource allocation.

[0110] In one possible design, a correspondence between the first application and the computing unit allocated to the first application can also be established. In other words, after the computing unit is allocated to the first application, the computing unit allocated to the first application is fixed (i.e., it is changed from an idle computing unit to a non-idle computing unit) and is only available to the first application. During the period when the first application is using the computing unit, other applications cannot access the allocated computing unit.

[0111] By adopting the above-mentioned method, the problem of allocating the resources allocated to the first application to other resources, which causes the first application to be interrupted, can be avoided, and the stable operation of the first application can be ensured.

[0112] Optionally, after the first application has finished using the computing units allocated to the first application, the computing units may be released (for example, by deleting the corresponding relationship) so that the computing units can be called by other applications. In this way, resource utilization can be further improved.

[0113] Optionally, after the first application has finished using the computing units allocated to it, the computing units may not be released (e.g., the corresponding relationship is retained), so that the computing units are not called by other applications. Instead, the computing units are reserved for the first application. In this way, the first application can directly use the computing units the next time it runs without the need for resource allocation. In this way, the performance of the first application can be prioritized.

[0114] In one possible design, the computing unit pool 11 includes one or more of a tensor computing unit pool, a vector computing unit pool, and a scalar computing unit pool.

[0115] For example, as shown in Figure 9, the computing unit pool 11 includes a tensor computing unit pool 11A, a vector computing unit pool 11B and a scalar computing unit pool 11C. The tensor computing unit pool 11A includes one or more tensor computing units 111A, the vector computing unit pool 11B includes one or more vector computing units 111B, and the scalar computing unit pool 11C includes one or more scalar computing units 111C.

[0116] When allocating a computing unit to the first application, a corresponding computing unit pool may be first found according to the corresponding algorithm dimension, and then a computing unit may be determined from the computing unit pool.

[0117] Pooling tensor computing units, vector computing units, and scalar computing units separately can improve resource management efficiency and the efficiency of resource scheduling by upper-layer applications.

[0118] It is understandable that the above-mentioned design methods can be implemented separately or in combination with each other.

[0119] Based on the same technical concept, an embodiment of the present application further provides a processing device 100, which includes modules / units / technical means for executing the method shown in FIG. 7 .

[0120] For example, referring to FIG10 , the processing device 100 may include:

[0121] The transceiver module 1001 is configured to receive a request to execute a first application;

[0122] Processing module 1002 is used to determine the computing resource requirements of the first application, and allocate computing units to the first application from the computing unit pool of the processor according to the computing resource requirements to implement the first application, wherein the computing resource requirements include one or more of tensor computing units, vector computing units, and vector computing units, and the number of each type of computing units; wherein the computing unit pool includes multiple computing units; each idle computing unit in the multiple computing units can be called on demand, and the number of different types of computing units in the multiple computing units is positively correlated with the number of times the computing unit of that type is called.

[0123] It should be understood that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0124] Based on the same technical concept, referring to FIG. 11 , an embodiment of the present application further provides a computing platform 1100 , including the processor 01 and the processing device 100 described above.

[0125] Based on the same technical concept, an embodiment of the present application further provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are called by a computer, the method shown in Figure 7 is executed.

[0126] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0127] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each flow and / or box in the flow chart and / or block diagram, as well as the combination of the flow chart and / or box in the flow chart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more flow charts and / or one or more boxes in the block diagram.

[0128] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0129] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0130] Obviously, those skilled in the art may make various modifications and variations to this application without departing from the scope of protection of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A processor, characterized in that: The processor includes a computing unit pool, and the computing unit pool includes a plurality of computing units; Each idle computing unit in the plurality of computing units can be called as needed, and the number of different types of computing units in the plurality of computing units is positively correlated with the number of times the computing units of the type are called.

2. The processor according to claim 1, wherein: Each of the multiple computing units corresponds to a low-level operation instruction.

3. The processor according to claim 1 or 2, characterized in that The computing unit pool includes one or more of a tensor computing unit pool, a vector computing unit pool, and a scalar computing unit pool.

4. The processor according to any one of claims 1 to 3, characterized in that The processor is configured to: receiving a request to execute a first application; Determine the computing resource requirements of the first application, and allocate computing units to the first application from the computing unit pool based on the computing resource requirements to implement the first application, wherein the computing resource requirements include one or more of tensor computing units, vector computing units, and vector computing units, and the number of each type of computing units.

5. The processor according to claim 4, wherein: The processor is further configured to: Determining multiple processes corresponding to the first application; Determine the computing resource requirements of each of the multiple processes, and allocate a computing unit from the computing unit pool to each process based on the computing resource requirements of each process to implement the first application; wherein the computing unit allocated to each process is different from the computing units allocated to other processes.

6. The processor according to claim 4 or 5, characterized in that The processor is further configured to: determining whether the computing unit allocated to the first application meets the needs of the first application; When the computing unit allocated to the first application cannot meet the needs of the first application, the computing resource allocation result of the first application is adjusted, and a computing unit is allocated to the first application from the computing unit pool according to the adjusted computing resource allocation result.

7. The processor according to claim 4 or 5, characterized in that The processor is further configured to: A correspondence between the first application and a computing unit allocated to the first application is established.

8. The processor according to any one of claims 1 to 7, characterized in that: The types correspond to algorithms executed by the plurality of computing units.

9. A resource allocation method, characterized in that: Applied to a processor, the processor includes a computing unit pool, the computing unit pool includes multiple computing units; each idle computing unit in the multiple computing units can be called on demand, and the number of different types of computing units in the multiple computing units is positively correlated with the number of times the computing units of the type are called; The method comprises: receiving a request to execute a first application; Determine the computing resource requirements of the first application, and allocate computing units to the first application from the computing unit pool based on the computing resource requirements to implement the first application, wherein the computing resource requirements include one or more of tensor computing units, vector computing units, and vector computing units, and the number of each type of computing units.

10. The method according to claim 9, characterized in that The determining the computing resource requirement of the first application, and allocating a computing unit from the computing unit pool to the first application according to the computing resource requirement to implement the first application, includes: Determining multiple processes corresponding to the first application; Determine the computing resource requirements of each of the multiple processes, and allocate a computing unit from the computing unit pool to each process based on the computing resource requirements of each process to implement the first application; wherein the computing unit allocated to each process is different from the computing units allocated to other processes.

11. The method according to claim 9 or 10, characterized in that The method further comprises: determining whether the computing unit allocated to the first application meets the needs of the first application; When the computing unit allocated to the first application cannot meet the needs of the first application, the computing resource allocation result of the first application is adjusted, and a computing unit is allocated to the first application from the computing unit pool according to the adjusted computing resource allocation result.

12. The method according to claim 9 or 10, characterized in that The method further comprises: A correspondence between the first application and a computing unit allocated to the first application is established.

13. A processing device, characterized in that: include: a transceiver module, configured to receive a request to execute a first application; a processing module, configured to determine a computing resource requirement of the first application, and allocate computing units to the first application from a computing unit pool of a processor according to the computing resource requirement to implement the first application, wherein the computing resource requirement includes one or more of tensor computing units, vector computing units, and vector computing units, and the number of each type of computing units; The computing unit pool includes multiple computing units; each idle computing unit in the multiple computing units can be called on demand, and the number of different types of computing units in the multiple computing units is positively correlated with the number of times the computing unit of the type is called.

14. The device according to claim 13, characterized in that The processing module is further configured to: Determining multiple processes corresponding to the first application; Determine the computing resource requirements of each of the multiple processes, and allocate a computing unit from the computing unit pool to each process based on the computing resource requirements of each process to implement the first application; wherein the computing unit allocated to each process is different from the computing units allocated to other processes.

15. The device according to claim 13 or 14, characterized in that The processing module is further configured to: determining whether the computing unit allocated to the first application meets the needs of the first application; When the computing unit allocated to the first application cannot meet the needs of the first application, the computing resource allocation result of the first application is adjusted, and a computing unit is allocated to the first application from the computing unit pool according to the adjusted computing resource allocation result.

16. The device according to claim 13 or 14, characterized in that The processing module is further configured to: A correspondence between the first application and a computing unit allocated to the first application is established.

17. A computing platform, characterized in that The method comprises the processor according to any one of claims 1 to 3 and the apparatus according to any one of claims 13 to 16.

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