Photoelectric device and processing method thereof

Abstract

The invention relates to an optoelectronic device comprising a structured semiconductor layer stack having at least one of an n-doped layer and a p-doped layer and a structured active region arranged on a respective one of the n-doped layer and the p-doped layer. A regrown conductive barrier layer covers the active region, the regrown conductive barrier layer comprising a material adjacent to the active region, the material having a larger band gap than the active region. Contact layers are electrically coupled to the n-doped layer and the p-doped layer, respectively, wherein one of the contact layers is in electrical contact with the regrown conductive barrier layer covering the structured boundary of the active region. Further, the first current blocking layer is arranged adjacent to the active region and surrounded by the material of the regrown conductive barrier layer. The contact layer is in electrical contact with the regrown conductive barrier layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to German application DE 10 2022 122 479.1, filed September 5, 2022, the contents of which are incorporated herein by reference. Technical Field

[0003] The invention relates to a photoelectric device and a processing method thereof. Background Art

[0004] Mesa etching of micrometer-scale LEDs (μ-LEDs) is performed to optically and electrically isolate individual devices, or to isolate individual devices that form pixels in an array. Mesa etching will cause damage at the etch boundaries, resulting in crystal defects, dangling bonds, and other regularities in the crystal structure. These irregularities cause non-radiative recombination (NRR) of carriers at the mesa edges.

[0005] At large pixels (where the ratio of total area to perimeter is large), the above defects do not significantly degrade device performance. However, for small devices, the impact of such defects becomes larger. Current spreading in layers above and below the active area and through the active area contributes to carriers at the edges of the pixel, which can then recombine non-radiatively, thereby reducing the quantum efficiency of the device.

[0006] The effect is particularly pronounced for InGaAlP-based μ-LEDs, which are commonly used for red emission. This is due to the long diffusion lengths and high surface recombination velocities of charge carriers within the dimensions of μ-LED devices.

[0007] The object of the present application is to overcome these and other problems, particularly for μ-LEDs. Summary of the invention

[0008] This and other objects are solved by the subject-matter of the independent claims. Features and further aspects of the proposed principle are outlined in the dependent claims.

[0009] Depending on the material system, different methods for passivating the mesa edges have been employed so that the number of defects is reduced and thus the performance is improved. For the InGaAlP material system, which is typically used for yellow / red emission, there are two main approaches to reduce the NRR at the mesa facets. These are called quantum well intermixing (QWI) and regrowth.

[0010] QWI is a method of intentionally diffusing impurities or vacancies into the active region (impurity-free QWI). Impurities and vacancies cause mixing of quantum wells in the active region with adjacent high-bandgap barriers, resulting in an overall increase in the local bandgap. When applied at the edges of the active region and device, this results in a lateral barrier for charge carriers to avoid leakage from the core of the active region to its circumferential edges.

[0011] However, quantum well intermixing has technological limitations, especially when processing small device sizes.

[0012] As an alternative, a so-called multi-step epitaxy (regrowth method) can be performed. Typically, an initial epitaxial layer (epi) including the active area is grown, and then the top surface is covered with a structured hard mask. The hard mask is used to etch the wafer surface, removing parts of the active area, leaving a quantum well (QW) isolated point at the center of the device defined later. The structure is then regrown on the same wafer with a high bandgap material to encapsulate the QW isolated point. Further etching can be performed outside the QW isolated point to form a pixel larger than the isolated point.

[0013] In this way, a potential barrier appears between the pixel core and the mesa facets, hindering the diffusion of charge carriers to the surface. For GaN / InGaN-based μLEDs, passivation dielectrics such as Al2O3 and SiO2 provided by atomic layer deposition (ALD) are used to reduce the NRR at the pixel side facets. To reduce the NRR, pre-passivation etching and cleaning methods are also used to remove, for example, native oxides and defects. Depending on the chip size and epi configuration, some of these techniques cannot be used or are still insufficient for high-efficiency μLEDs. Especially for pixel sizes <10 micrometers (μm).

[0014] The inventors have proposed a new concept for a regrowth method, that is, one type of charge carrier (electron or hole) is injected around the edge of the active area core, rather than injected from above or below through the core. That is, one type of charge carrier is injected along the edge or sidewall of the active area, while the other type of charge carrier is injected from the top or below through the center of the active area. Therefore, the side-injected carriers are spread throughout the core active area and radiatively recombine with the core-injected carriers. This is particularly useful for very small etched cores in some material systems, where the diffusion length of the side-injected carriers is within the size range of the active area.

[0015] The proposed concept can be realized by mesa etching the core, as in some conventional regrowth processes, but on a stack including a specific barrier layer on top of the active area, preventing charge carriers from entering the active area from the central part. That is, the barrier layer on top of the active area prevents charge carriers from being injected from the top. Charge carriers (i.e. holes) are forced to be injected around the edge of the active area, rather than through the top. This will therefore shield the NRR effect at the edge of the active area.

[0016] The barrier layer is preferably realized with the same semiconductor material as the layer stack, ie a non-dielectric material is used, although a dielectric material may be possible.

[0017] In some aspects, the inventors propose an optoelectronic device comprising a structured semiconductor layer stack having at least one of an n-doped layer and a p-doped layer and a structured active region arranged on a respective one of the n-doped layer and the p-doped layer. The structured active region is configured to emit light during operation of the device. Processing of the structured layer stack can follow conventional techniques, namely wafer fabrication and epitaxial processing.

[0018] The regrown conductive barrier layer covers the structured border of the active region. The regrown conductive barrier layer includes a material adjacent to the active region, the material including a larger band gap than the active region. Specifically, the regrown conductive barrier layer covers the edge with a material having a larger bandwidth, thereby preventing charge carriers from reaching the center of the NRR.

[0019] In addition, the corresponding contact layers are electrically coupled to the n-doped layer and the p-doped layer, respectively, wherein one of the contact layers is in electrical contact with the regrown conductive barrier layer covering the structured boundary of the active area. This will ensure that the carriers are injected into the active area along the edge and boundary of the active area through the regrown conductive barrier layer. According to the proposed principle, the first current blocking layer is arranged adjacent to the active area and surrounded by the material of the regrown conductive barrier layer. Therefore, it is impossible to inject through the central part of the active area.

[0020] The device forms a vertical μLED structure, in which the conductive contact area and the metal contact area in some aspects are located in opposite positions and face each other. Therefore, any further processing can follow conventional techniques, which reduces the number of necessary modifications during the manufacturing process. The resulting optoelectronic device shows improved performance and improved quantum efficiency, but can be further processed using well-established processes.

[0021] The proposed concept is independent of the structure of the active region, i.e. the active region may comprise a quantum well structure, one or more quantum dots or a multi-quantum well structure. Heterogeneous structures are also possible. In order to prevent the diffusion of doped materials into the active region, the active region may be covered by one or more, in particular undoped, cladding layers. One of these cladding layers may be adjacent to the current blocking layer.

[0022] In some aspects, the regrown conductive barrier layer grows onto the first current blocking layer. Since the regrown conductive barrier layer is also doped, the growth on the first current blocking layer forms the other of the n-doped layer and the p-doped layer. In an alternative solution, the other of the n-doped layer and the p-doped layer is actually omitted, and the material of the contact layer that is in electrical contact with the regrown conductive barrier layer covering the structured boundary is deposited directly onto the regrown conductive barrier layer. Additionally and optionally, the material of the contact layer can also be deposited on the first current blocking layer.

[0023] In some aspects, the contact layer and other layers are absorbent to some extent. In order to reduce the absorption of light relative to the main emitting surface, it is suitable in some aspects to further create a reflective layer deposited on the first current blocking layer, in particular a dielectric layer. Such a layer can be in the form of a DBR structure to reflect incident light generated in the active area. In this regard, the material of the contact layer can also be reflective, or at least some reflective metal can be arranged on the contact layer.

[0024] In some aspects, the regrown conductive barrier layer includes a heterostructure of at least two semiconductor layers. It may be suitable to utilize a doped semiconductor material that is also used for the other of the p-doped layer and the n-doped layer of the layer stack. Thus, the material used for the other of the n-doped layer and the p-doped layer can be reused in the regrowing process to form a regrown conductive barrier layer on the doped layer at the edge of the active region and above the barrier layer. The thickness of the regrown conductive barrier layer can be as thin as tens of nanometers (nm), for example, between 20nm and 100nm or between 20nm and 50nm. Therefore, the overall size of the device remains small, and the regrown layer provides a high enough barrier to significantly reduce diffusion.

[0025] Some additional aspects relate to the material of the regrown conductive barrier layer, and more specifically to the material of its heterostructure. As previously mentioned, some materials correspond to the respective other of the n-doped layer and the p-doped layer. The regrown conductive barrier layer may include an InAlP layer adjacent to the active region, in particular a doped InAlP layer. Alternatively, a ZnSSe layer may be grown adjacent to the active region because ZnSSe may be lattice matched.

[0026] In some cases, the conductive barrier layer includes a heterostructure, which includes at least a doped InGaAlP layer and a doped InAlP layer, and the doped InAlP layer is grown on the boundary material of the active region. In some cases, the first current blocking layer includes a semiconductor multilayer. The multiple layers have different doping types. Specifically, when viewed from the direction of the active region, it is a pnpn multilayer.

[0027] In some cases, the contact layer includes a metal and / or a conductive oxide.

[0028] Some other aspects relate to further reduction of leakage current. In some cases, a portion of the regrown conductive barrier layer extends substantially parallel to at least one of the n-doped layer and the p-doped layer, thereby surrounding the active layer. Such an extension may be necessary to fully reduce any NRR and prevent charge carriers from reaching the surface of the device. In addition, it should be noted that alignment may be difficult to achieve during the mesa etching step, so a safety margin is increased when processing the device. The regrown and often doped conductive barrier layer extending substantially parallel to at least one of the n-doped layer and the p-doped layer forms a new pn junction, resulting in leakage current. In order to reduce such current, a second current blocking layer is arranged on the portion of the regrown conductive barrier layer, and the second current blocking layer includes an opening. Therefore, the second blocking layer is located between different doping regions, thereby preventing leakage current caused by the doped regrown conductive barrier layer. Charge carriers are injected into the active area along its boundary by the regrown conductive barrier layer. Any charge carrier injection from the regrown conductive barrier layer to another doped layer is prevented by the second blocking layer.

[0029] In some cases, at least one of the n-doped layer and the p-doped layer extends through the opening, thereby connecting the active area. The second current blocking layer may include a semiconductor multilayer, which includes multiple layers of different doping types, especially npnp, when viewed from the direction of the active area. The second blocking layer may have the same heterostructure as the first blocking layer.

[0030] In some cases, the first current blocking layer and / or the second current blocking layer may include a thickness in the range of 50nm to 300nm and in particular less than 250nm. In some aspects, the thickness of the different layers may be substantially equal. The thickness of each layer in the plurality of layers may be as thin as tens of nm. Each layer may be based on the same material system, but with different doping to form the above-mentioned pnpn and npnp multilayers, respectively. In some other cases, the material for the current blocking layer is the same as one of the n-doped layer and the p-doped layer, in particular a layer in conductive contact with the regrown conductive material. More specifically, one or more doped layers of the current blocking layer are based on InAlP semiconductor material.

[0031] The material of the first current blocking layer and / or the second current blocking layer may include 1E15 / cm 3 To 1E19 / cm 3 This is optimized in each layer to maximize current blocking.

[0032] In some other cases, the optoelectronic device includes a dielectric layer, in particular one of Al2O3 and SiO2, covering a portion of the regrown conductive barrier layer facing away from the active region. In addition, the optoelectronic device may include a structured inclined sidewall extending from one of the contact layers electrically contacting the regrown conductive barrier layer along a first portion having a first angle and along a second portion having a second angle toward another contact layer.

[0033] Another aspect relates to processing optoelectronic devices. After providing a growth substrate, such as a GaAs substrate having a (111) growth direction, a semiconductor layer stack is epitaxially grown on the growth substrate. The semiconductor stack includes one of an n-doped layer and a p-doped layer and an active region arranged on a corresponding one of the n-doped layer and the p-doped layer. A first current blocking layer on the active region is epitaxially grown onto the active region. Then, a mask layer is provided on the first current blocking layer, and the mask layer is subsequently constructed to cover a portion above the active region. Using a structured mask, a first etch is performed to form a mesa structure exposing a boundary of the active region.

[0034] The resulting mesa structure with exposed sidewalls of the active area is then overgrown by a conductive barrier layer. The regrown conductive barrier layer includes a material adjacent to the active area that has a larger bandgap than the active area. Finally, a contact layer is deposited that is electrically coupled to the regrown conductive barrier layer that covers the structured boundary of the active area. The contact layer is at least partially disposed on the first current blocking layer.

[0035] The proposed method provides a current blocking layer that prevents charge carriers from being injected into the central region of the active layer, and instead forces the charge carriers to enter the active region from the side edges or surrounding boundaries. This is achieved by regrowing a conductive barrier layer that also acts as a barrier to generate a potential around the active region boundary. Furthermore, the regrowing conductive barrier layer reduces the amount of NRR at the active region boundary. With the proposed method, the overall performance of the optoelectronic device is improved, especially at very small sizes in the range of a few μm.

[0036] In some aspects, the conductive barrier layer is also regrown on the first current blocking layer. This will make it easier to process and can improve the current spreading characteristics of the barrier layer. The contact layer can be at least partially deposited on the regrown conductive barrier layer covering the boundary of the active area. The material of the contact layer can also extend to the current blocking layer. As another alternative, a reflective dielectric layer can be deposited on the first current blocking layer, and the reflective dielectric layer includes at least one of a DBR structure and / or a reflective material. The DBR structure can be configured to reflect light emitted from the active area, thereby improving overall performance and light efficiency.

[0037] Some aspects relate to the conductive barrier layer. An InAlP layer, in particular a doped InAlP layer, can be grown adjacent to the active region. As an alternative, a lattice-matched ZnSSe layer is also suitable for growth adjacent to the active region. Furthermore, alternatively, a heterostructure can be grown, which includes at least a doped InGaAlP layer and a doped InAlP layer.

[0038] In some cases, a doped GaP layer is grown, optionally adjacent to a contact layer.Since GaP is lattice mismatched, other layers for lattice matching (such as those described above) are suitable.

[0039] In some aspects, the regrowing the conductive barrier layer is followed by the step of performing a second etch to remove a portion of the regrown conductive barrier layer surrounding the layer stack so that a portion of the regrown conductive barrier layer extending substantially parallel to at least one of the n-doped layer and the p-doped layer remains. This is done to electrically isolate and later optically isolate each pixel.

[0040] In this regard, providing a semiconductor stack may include the step of growing a second current blocking layer on one of the n-doped layer and the p-doped layer. Subsequently, the second current blocking layer is constructed to form an opening that exposes the surface of one of the n-doped layer and the p-doped layer below. A doped layer of the same doping type as one of the n-doped layer and the p-doped layer is grown into the opening, an active area is formed thereon, and a second current blocking layer is formed on the structure. The second blocking layer significantly reduces any leakage current that enters the n-doped layer or the p-doped layer through the edge of the conductive barrier layer.

[0041] The second barrier layer may comprise a structure similar to the first barrier layer, comprising a plurality of differently doped layers, in particular an npnp multilayer when viewed from the direction of the active region. The multilayer is epitaxially grown using different doping types and subsequently structured. The doping is optimized to increase the barrier.

[0042] In some cases, the first current blocking layer and / or the second current blocking layer comprises a thickness in the range of 100 nm to 300 nm, in particular less than 250 nm.Alternatively or additionally, the thickness of each of the plurality of layers may be as thin as tens of nm.

[0043] In some other cases, the same material as used in one of the n-doped layer and the p-doped layer is used, in particular the layer in conductive contact with the regrown conductive material. For example, the first current blocking layer and / or the second current blocking layer may include a plurality of differently doped InAlP semiconductor material layers. In some other cases, the first current blocking layer and / or the second current blocking layer may include a dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Other aspects and embodiments according to the proposed principles will become apparent with respect to the various embodiments and examples described in detail in conjunction with the accompanying drawings, in which

[0045] Figure 1 A first embodiment of an optoelectronic device according to some aspects of the proposed principles is shown;

[0046] Figure 2 A second embodiment of an optoelectronic device according to some aspects of the proposed principles is shown;

[0047] Figure 3 A third embodiment of an optoelectronic device according to some aspects of the proposed principles is shown;

[0048] Figure 4 A fourth embodiment of an optoelectronic device according to some aspects of the proposed principles is shown;

[0049] FIG. 5A to FIG. 5L An embodiment of a method of processing an optoelectronic device according to some aspects of the proposed principles is shown;

[0050] FIG. 6A to FIG. 6C Some further aspects of methods of processing optoelectronic devices according to some aspects of the proposed principles are shown;

[0051] Figure 7 Implementations of current blocking layers according to some aspects of the proposed principles are shown. DETAILED DESCRIPTION

[0052] The following embodiments and examples disclose various aspects and combinations thereof according to the proposed principles. Embodiments and examples are not always drawn to scale. Similarly, different elements may be displayed in enlarged or reduced sizes to emphasize various aspects. It goes without saying that the various aspects of the embodiments and examples shown in the drawings can be combined with each other without further explanation, and this will not contradict the principles of the present invention. Some aspects show regular structures or forms. It should be noted that in practice, slight differences and deviations from the ideal form may occur, however, this does not contradict the concept of the present invention.

[0053] In addition, the various figures and aspects are not necessarily shown in the correct size, and the ratios between the various elements are not necessarily substantially correct. Some aspects are highlighted by being shown enlarged. However, with respect to the elements in the drawings, terms such as "above", "above", "below", "below", "larger", "smaller", etc. are correctly represented. Therefore, such relationships between elements can be derived based on the drawings.

[0054] It is also noted herein that a given base material system such as InAlP or InGaAlP may have variations in its contents. This is an exemplary system for illustrative purposes, and the principles presented should not be limited to such a system. For example, the material InGaAlP may include different percentages of In, Ga, and Al contents, and may also be made of InAlP. y (Ga x Al 1-x )P represents, while x and y are corresponding parameters and can be varied according to the desired wavelength of the emitted light and / or the appropriate barrier difference in the band gap. For example, in a multiple quantum well heterostructure, the Al content can be varied between 0 and 1 to provide a quantum well layer or a barrier layer. The parameter x is 0, and x=0 corresponds to an InAlP layer. Changing the In content generally changes the lattice constant and can be used to induce strain in the crystal, which also changes the band gap. Therefore, different In contents are used to tune the emitted light to the desired wavelength.

[0055] Figure 1 A first implementation according to some aspects of the proposed principles is shown. It should be noted that Figure 1 Embodiments and further embodiments show optoelectronic devices with current blocking layers on their respective p-doped sides. However, those skilled in the art will recognize that the respective current blocking layers proposed in the present application can also be implemented on the n-doped side. Variations in the structure of the n-doped and p-doped layers in terms of material composition or doping concentration and the structure of the optoelectronic device can be implemented without departing from the proposed concept.

[0056] The optoelectronic device includes a carrier wafer substrate 10, which can be used as a wafer for further processing of the optoelectronic device, but in other embodiments may also include circuits for addressing the optoelectronic device during operation and providing corresponding currents and voltages thereto. The optoelectronic device is embedded in a mirror and bonding metal 11, which surrounds the semiconductor stack layer including the active area 41. The mirror and bonding layer 11 serves the purpose of providing electrical contact with the layer stack, but also provides a reflective surface to improve the overall emission efficiency. During the processing of the device, the mirror and bonding metal layer 11 is deposited to cover the layer stack, thereby ensuring re-bonding and a stable structure. The layer 11 is retained afterwards.

[0057] The semiconductor layer stack includes inclined sidewalls which resemble a pyramid structure when viewed from the direction of the contact hole 12. The inclined sidewalls and the pyramid structure are formed by two mesa etching processes, as will be explained in subsequent figures.

[0058] The optoelectronic device comprises a bottom opening 12, which connects the conductive metal of the mirror and the bonding metal 11 to the conductive contact layer 14 of the layer stack. The contact layer 14 of this embodiment is made of a conductive transparent oxide. The contact layer 14 is covered by a dielectric layer 13, which extends upward from the bottom contact hole 11 on the side wall of the layer stack, separating the mirror and the bonding metal 11 from the n-doped layer 50 structure.

[0059] The contact layer 14 is electrically connected to the conductive barrier layer 20, which includes a GaP layer 23, a p-doped indium gallium aluminum phosphide, an InGaAlP layer 22, and a p-doped indium aluminum phosphide InAlP barrier layer 21. Therefore, the conductive barrier layer 20 includes a heterostructure of several p-doped layers and undoped layers for transmitting the corresponding charge carriers induced by the contact layer 14 toward the active area 41. As shown in the figure, the conductive barrier layer 20 extends on the sidewalls of the layer stack and on the bottom of the layer stack (the bottom is the part of the layer stack with the smallest diameter).

[0060] According to the present invention, a first current blocking layer 30 is provided between the conductive barrier layer 20 and the active region 41. Between the current blocking layer 30 and the active region 41, an undoped cladding layer made of indium gallium aluminum phosphide InGaAlP 40 is provided. A second cladding layer 42 made of the same material is grown on the active region 41 opposite to the first cladding layer 40. Both cladding layers are optional, but in this embodiment should prevent the diffusion of unwanted dopants into the active region 41. Their thickness is in the range of several tens of nm.

[0061] The active region 41 includes an undoped quantum well or undoped multiple quantum well structure made of indium gallium aluminum phosphide InGaAlP with different aluminum contents to provide a plurality of alternating barrier layers and quantum well layers, respectively. The cladding layer 42 also partially extends onto a portion of the barrier layer 21 extending substantially parallel to the n-doped layer structure 50.

[0062] When viewed from the bottom, an undoped indium aluminum phosphide InAlP barrier layer 51 is arranged on top of the second cladding layer 42 and its lateral dimensions are limited by the dielectric layer 13. Two current spreading layers of n-doping type corresponding to the layer structure 50, namely layers 52 and 53, are arranged on the undoped indium aluminum phosphide, the InAlP barrier layer 51 and the dielectric layer 13. The n-doped layer structure 50 comprises an n-doped indium aluminum phosphide spreading layer 52 and an n-doped indium gallium aluminum phosphide contact layer 53. Finally, a grid structure 54 is provided for carrier injection.

[0063] When viewed from the direction of the active layer 41, the first barrier layer 30 comprises a pnpn doped multilayer. This structure prevents any charge carriers from the layers 23, 22 and 21 from being injected into the active region 41 through its main surface. Instead, any charge carriers will flow along the inclined sidewalls of the conductive barrier layer 20 and enter the active region 41 along its corresponding side edges. That is, the conductive barrier layer provides effective lateral injection and spreading of charge carriers from the side to the active region, while the current blocking layer 30 prevents injection from the top or bottom. Therefore, the current blocking layer 30 prevents or significantly reduces vertical electron overflow, which otherwise may lead to non-radiative recombination.

[0064] As shown, the conductive barrier layer 20 comprises a heterostructure of three different layers 21, 22 and 23, which themselves are made of different materials. This results in a corresponding increase in the band gap compared to the band gap of the active region 41. While the active region 41 comprises a band gap of, for example, about 2.0 eV, the indium aluminum phosphide InAlP barrier material of layer 21 already comprises a higher band gap of about 2.2 eV. The third layer 23 made of gallium phosphide GaP comprises an even higher band gap of about 2.3 eV.

[0065] Instead of using materials for the conductive barrier layer as shown herein, other crystal-matched materials are suitable. Examples of such materials are ZnSSe or AlAs, which include even higher band gaps with approximately the same lattice. The thickness of the barrier layer depends on the size of the pixel and can be as thin as tens of nm. The thickness of the first current blocking layer 30 depends on the individual layers of the multilayer and is in the range of about 100 nm or more. When a pnpn structure is used, the thickness of each layer is greater than tens of nm and the doping concentration is in the range of 1E15 / cm 3 To 1E19 / cm 3 range, optimized to maximize blocking.

[0066] In such Figure 1 In the embodiment shown, a small portion of the conductive barrier layer is in direct contact with the undoped cladding layer 42, thereby creating a PIN structure along the outer edge of the layer stack. This artificial PIN junction will generate current leakage, which leads to reduced efficiency and non-radiative recombination along the outer edge of the layer stack during the operation of the device. In order to prevent current leakage, a second current blocking layer 60 can be arranged between the conductive barrier layer and the n-doped current spreading layers 52 and 53, respectively.

[0067] Figure 2A corresponding embodiment is shown. As shown, the conductive barrier layer encapsulates the active area and the barrier layer 30 along its inclined sidewalls, but also extends at least partially parallel to the n-doped layers 52 and 53 in the outer region, respectively. This extension of the conductive barrier layer 20 is due to the etching process of the mesa etching and the subsequent regrowth process. Specifically, the second mesa etching of the material of the etching conductive barrier layer requires a higher tolerance due to possible mismatch, resulting in the configuration shown with a small portion extending parallel to the n-doped layer. In order to prevent the above-mentioned leakage current caused by the artificial pin junction or pn junction, a second barrier layer 60 is provided between the p-doped barrier layer 21 and the n-doped layer 52. When viewed from the direction of the active area, the second barrier layer 60 also includes an npnp multilayer. The npnp multilayer produces an electrical blocking barrier and acts as a thyristor (without a gate connection) to prevent current flow.

[0068] An opening in the second barrier layer 60 is provided and filled with a conductive indium aluminum phosphide InAlP material 51. Thus, charge carriers from the n-doped current spreading layers 52 and 53 are respectively injected into the active region 41 through layer 51, while holes are injected by the conductive barrier layer 20 into the sidewalls of the active region 41. At the same time, the npnp structure of the second barrier layer 60 prevents any artificial current from bypassing the active region from the conductive barrier layer to the n-doped layer.

[0069] Figure 3 Another alternative of an optoelectronic device having two barrier layers 30 and 60, respectively, is shown. In this embodiment, the overall height of the optoelectronic device is further reduced by applying the contact layer 14 directly on top of the first barrier layer 30. This enables very thin optoelectronic devices. During manufacturing and subsequent regrowth, the conductive barrier layer 20 grows on top of the barrier layer 30 and on the mesa-etched sidewalls of the layer stack. However, since the current blocking layer 30 will prevent any carriers from being injected into the active area 41 through the corresponding main surface (the main top or bottom of the active area 41), the material of the conductive barrier layer 20 can be removed from the top of the current blocking layer 30 and replaced by the material of the contact layer 14.

[0070] This implementation is Figure 3, where the transparent conductive oxide of the contact layer 14 is deposited directly on top of the current blocking layer 30. This can be achieved by using a dielectric etch and a selective area regrowth mask (not shown) for etching of the mesa and regrowth of the conductive barrier layer so that regrowth does not occur on the top of the barrier layer and only occurs on the side of the structure. The mask can then be removed and the contact layer 14 can be deposited. The structure can also be achieved by additional etching or polishing processes without using a selective regrowth mask. After the regrowth of the conductive barrier layer 20, the material of the conductive barrier layer 20 is covered by a structured mask layer (if removed by etching, it does not need to be removed by polishing), thereby exposing the portion of the conductive barrier layer 20 on top of the current blocking layer 30. Those exposed portions are removed in a subsequent etching process. Similarly, polishing can remove the layer 20 on top, and after removing the mask material, the contact layer 14 is deposited on the sidewalls of the remaining conductive barrier layer 20 and the top portion of the current blocking layer 30.

[0071] The dielectric material 13 in this embodiment is typically made of silicon dioxide (SiO2) or any other transparent non-conductive material. In the operation of the device, the active region 41 will emit photons in every direction. The metallic material of layer 11 is partially used to reflect the light emitted in the direction of the bottom of the layer stack (the bottom is the portion of the layer stack with its smallest diameter). However, there is a possibility that the photons emitted by the active region 41 are subsequently absorbed in the contact layer 14 or the conductive material barrier layer 20. In order to reduce such undesirable photon absorption and improve the overall emission efficiency, a reflective layer 70 can be provided on the top of the current blocking layer 30 and the adjacent side of the conductive barrier layer 20. The reflective additional layer 70 will increase the reflective properties and reduce the possibility of absorbing photons emitted in the bottom direction.

[0072] Figure 4 A corresponding embodiment is shown. The optoelectronic device 1 includes a layer stack as explained in more detail previously, wherein the first current blocking layer 30 is grown on the active area 41 and encapsulated by the conductive barrier layer material 20. The contact layer 14 contacts the metal contact 12 through the central opening of the dielectric material 13 of the cover layer stack, and extends along the sidewalls on the conductive barrier layer 20. According to this embodiment, a reflective layer portion 70 is disposed between the contact layer 14 and the barrier layer 30, extending on the edge surface of the barrier layer 30 and on the surrounding conductive barrier layer 20. In some aspects, the reflective layer 70 is the remainder of the hard mask for the mesa etching and re-growth process of the layer 20. In some cases, the reflective layer 70 is a distributed Bragg reflection (DBR) structure (which can also be used as a hard mask for the mesa etching and re-growth process) to reflect any light emitted toward the bottom area of ​​the device. This will reduce absorption in the contact layer 14.

[0073] Figure 5A )to Figure 5L ) shows several steps for processing optoelectronic devices according to some aspects of the proposed principles. Figure 5A ) shows a first step of growing a plurality of n-doped layers 53 and 52 on a respective growth substrate 54. The growth substrate may, for example, comprise GaAs. Such a substrate supports the growth of subsequent layers, thereby reducing crystal mismatch and defects during the growth of each layer.

[0074] Layers 53 and 52 are n-doped with different or constant doping profiles to provide good contact with the metal layer for contacting the subsequently grown semiconductor stack and to provide current spreading. For example, layer 53 comprises an Indium Gallium Aluminum Phosphide InGaAlP contact layer with a doping range of >1E17 atoms / cm 3 The subsequently grown layer 52 comprises an interspersed layer of InP, which is also n-doped to a concentration of >1E17 atoms / cm 3 Before growing the two n-doped layers 53 and 52, further layers may be applied to the growth substrate, between them or even on top of them. Additional growth regulating layers between the substrate 54 and the n-doped layer 53 may be used to adjust the crystal structure and reduce the lattice mismatch.

[0075] continue Figure 5B ), a current blocking structure 60 based on an indium aluminum phosphide InAlP material system is grown on the top surface of the n-doped current spreading layer 52. The current blocking layer 60 includes a plurality of layers with different doping types. In view of the growth direction, the different doping types follow, for example, a doping level of 1E17 atoms / cm 3 and 1E19 atoms / cm 3 The current blocking layer 60 will prevent current leakage between the n-doped layer and the different p-doped layers of the subsequently regrown layer stack and thus reduce current leakage through the optoelectronic device in operation.

[0076] exist Figure 5C ), the current blocking layer 60 is then structured by applying a structured resist or electrolyte mask layer 601 to its surface and etching a portion of the current blocking layer 60 to expose the underlying n-doped current spreading layer 52. The exposed area will then form the seed for the layer stack for the optoelectronic device. Figure 5D As shown, the openings are overgrown using an indium aluminum phosphide InAlP layer 51. The mask 601 may optionally be removed before or after the regrowth of the layer 51 (only in the case of an electrolyte mask). Figure 5D This is for the case where the mask 601 is a dielectric and is removed after the regrowth of layer 51 .

[0077] The conductive layer 51 ensures the transport of charge carriers from the n-doped current spreading layer 52 to the active region subsequently grown on the surface of the current blocking layer 60 and the layer 51, as shown in FIG. Figure 4 shown.

[0078] Specifically, Figure 5E ), a small undoped cladding layer 42 (tens of nm thick) is grown on the top surface, followed by a multi-quantum well structure 41 made of a plurality of barrier layers and quantum well layers, respectively. The base material for the multi-quantum well structure is a ternary or quaternary system, for example, consisting of indium gallium aluminum phosphide InGaAlP, wherein the barrier layers and quantum well layers have different aluminum contents, respectively. On top of the active region 41, a second cladding layer 40 is grown. Both cladding layers 42 and 40 comprise undoped indium gallium aluminum phosphide InAlGaP layers. Their thickness is in the range of tens of nm. The composition of the Ga, Al and In amounts of the various cladding layers 40 and 42 on the one hand and the active region on the other hand can be varied to obtain certain band gap transitions within the structure to capture charge carriers therein. Undoped cladding layers are optionally added, for example to prevent dopants from diffusing into the active region during processing and subsequent operation.

[0079] Now the next Fig. 5F ) is the next process step shown in the figure, namely the growth of another current blocking layer 30 based on the indium aluminum gallium phosphide InGaAlP material system. The multilayer again includes a plurality of differently doped layers. In this case, when observed from the active area 41, a pnpn multilayer is grown. The thickness of both current blocking layers 60 and 30 can be, for example, in the range of about 100nm to 200nm respectively. The individual p-doped layers and n-doped layers in each current blocking layer can be, for example, each between 25nm and 50nm thick. The doping level of the p-doped and n-doped multilayers in the corresponding layers is between 1E15 atoms / cm 3 To 1E19 atoms / cm 3 Within the given range, the doping concentration and the thickness are set to a range in which tunneling of charge carriers does not occur or substantially does not occur.

[0080] exist Figure 5G In a next processing step shown in ), a hard mask material is deposited on top of the current blocking layer 30 and is subsequently structured to provide a column of mask layer material 301 arranged substantially centrally in the region of the undoped layer 51.

[0081] In a subsequent step, a first mesa etching step is performed using the mask layer 301 down to the second current blocking layer 60, exposing the sidewalls of the active region 40, the blocking layer 30, and the two cladding layers 41 and 42. In a top view, the mesa etching is performed in a pyramid-like structure with exposed sidewalls. The resulting structure is Figure 5H Shown in.

[0082] In this embodiment, after removing the hard mask 301, Fig.5I ), a p-doped material layer 21 is formed on the top surface of the current blocking layer 30 and on the sidewalls of the exposed active region 40 partially extending onto the top surface of the second current blocking layer 60. As shown in the figure, the layer 21 forms the first layer of the conductive barrier layer 20.

[0083] More specifically, the material of layer 21 includes p-doped indium aluminum phosphide InAlP barrier material, with a doping concentration greater than 1E16 atoms / cm 3 On top of layer 21, a second layer 22 of p-doped indium gallium aluminum phosphide InGaAlP is grown, which in turn is covered by a gallium phosphide GaP layer 23, which is also a semiconductor contact layer. The three layers 21, 22 and 23 form a conductive barrier and contact layer 20 connecting the active area 40 from the side edges of the active area 40. Finally, as Figure 5J ), a contact layer 14 made of a transparent conductive oxide is deposited on top of the gallium phosphide, and a GaP layer 23 covers the top, the sidewalls and partially extends on the second current blocking layer 60.

[0084] Then still Figure 5J ) is shown in Figure 1 , the structure is partially covered by a structured mask layer 230, which extends through the entire layer stack, its sidewalls and over a portion of the conductive barrier material and the contact layer 14 parallel to the current blocking layer 60 is covered by the material of the mask layer 230. The lateral dimensions of the mask layer 230 are set so that any misalignment of the mask layer 230 still covers the layer stack, but also leaves some space so that the charge carriers that diffuse into the conductive barrier material are essentially away from the outer edges of the conductive barrier material (which are subsequently formed by etching).

[0085] exist Figure 5K In the subsequent step shown, a second mesa etch is performed to form a second sidewall that exposes the conductive barrier layers 21, 22 and 23 and the contact layer 14. The second mesa etch is performed until the top surface of the n-doped layer 52 is exposed. The inclination of the two mesa etches can be the same as shown in the exemplary method, but can also be different, for example, as shown in FIG. Figures 1 to 4 A dielectric material 13 , for example made of SiO 2 , is deposited on top of the n-doped layer 52 and on top of the corresponding exposed sidewall portions and the contact layer 14 .

[0086] The obtained structure is shown in Figure 5L). After providing an opening in the dielectric material of layer 13 to expose a portion of the transparent conductive oxide 14, a reflective metal stack is deposited to provide contact with the conductive layer 14. The metal stack also stabilizes the structure and facilitates rejoining and removal of the growth substrate 54. After removing the growth substrate 54 (not shown here), additional processing may be performed, such as applying a metal contact grid.

[0087] The resulting structure is similar to and corresponds to Figure 2 By omitting the growth and structuring of the current blocking layer 60, it is possible to achieve Figure 1 The structure of the implementation method.

[0088] Fig. 6A )to Figure 6B ) shows the process for processing according to Figure 4 Two further steps of the optoelectronic device of an embodiment of the present invention are performed. In this particular case, the mask layer 301' is disposed on the top surface of the current blocking layer 30. However, in the present case, the mask layer 301' comprises a DBR structure, i.e. a heterostructure of materials having different refractive indices, to reflect the light emitted in the active region toward the heterostructure 301'. After structuring the mask layer 301' and the active layer, similar steps are performed to grow the conductive barrier material layers 21, 22 and 23. In the present example, the growth of the corresponding materials is selective, i.e. the materials are mainly grown on the exposed side walls of the active region 41 and the cladding layers 40, 42 and on the top of the current blocking layer 60. This can be achieved, for example, by carefully adjusting the growth parameters during the regrowth process.

[0089] Figure 6B ) shows the result of the regrowth process, where the material of the conductive barrier layer 20 is mainly grown on the top surface of the current blocking layer 60 and on the exposed sidewalls of the semiconductor layer stack having the active area 41, the two cladding layers 40 and 42 and the current blocking layer 30, but not grown on the top of the mask layer 301'. Finally, a transparent conductive oxide or metal layer 14 is deposited on the conductive barrier 20 and on the top surface of the mask layer 301'. Therefore, the mask layer 301 remains in the optoelectronic device to form the above-mentioned DBR structure or other reflective structure to improve the outcoupling of the light generated in the active area.

[0090] Figure 6C ) shows slightly different process steps during and after the regrowth process. In this example, the mask layer 301' covering the top portion of the current blocking layer 30 is removed after the regrowth process of the conductive barrier layer 20, and the transparent conductive oxide layer 14 is deposited on the sidewalls of the conductive barrier layer and on the top portion of the current blocking layer 30. This embodiment corresponds to Figure 3 implementation method, and when combined with Figure 1This embodiment allows smaller vertical dimensions of the optoelectronic device and reduced absorption due to the omission of the layer 20 above the barrier layer. As in the previous embodiment, charge carriers provided by the contact layer 14 are injected into the active region 40 through the conductive barrier 20 along the sidewalls.

[0091] Figure 7 An example of a current blocking layer multilayer is shown, such as an npnp layer stack grown as current blocking layer 60 or a pnpn layer stack for current blocking layer 30. The npnp layer stack or pnpn layer stack comprises several differently doped layers, each having a thickness of several tens of nm. The structure is similar to a thyristor lacking a gate connection.

[0092] Reference Mark List

[0093] 1 Optoelectronic devices

[0094] 10 Carrier

[0095] 11Mirror and bonding layer

[0096] 12 Contact

[0097] 13 Dielectric Materials

[0098] 14Contact layer

[0099] 20Conductive barrier layer

[0100] 21 Barrier layer

[0101] 22, 23 Barrier layer

[0102] 30 Current blocking layer

[0103] 40 cladding

[0104] 41 quantum well layer, light emitting area

[0105] 42 cladding

[0106] 50n doped layer

[0107] 51 doping layer

[0108] 52 Current spreading layer

[0109] 53 contact layer

[0110] 54 grid structure

[0111] 60 second current blocking layer

[0112] 70DBR structure

Claims

1. A photoelectric device, comprising: - a structured semiconductor layer stack having at least one of an n-doped layer and a p-doped layer and a structured active region arranged on a respective one of the n-doped layer and the p-doped layer; The structured active region is configured to emit light; - a regrown conductive barrier layer, the regrown conductive barrier layer covering the structured boundary of the active area, the regrown conductive barrier layer comprising a material adjacent to the active area, the material having a larger band gap than the active area; - a respective contact layer electrically coupled to at least one of the n-doped layer and the p-doped layer, wherein one of the contact layers is in electrical contact with the regrown conductive barrier layer covering the structured boundary of the active area; - a first current blocking layer arranged adjacent to the active area and surrounded by material of the regrown conductive barrier layer.

2. The optoelectronic device according to claim 1, wherein The one of the contact layers in electrical contact with the regrown conductive barrier layer is disposed on the regrown conductive barrier layer.

3. The optoelectronic device according to claim 1 or 2, wherein: The active region includes one of the following: - Quantum wells; -Multiple quantum wells; - Heterogeneous structures; as well as - One or more quantum dots. - one or more cladding layers, in particular undoped cladding layers, one of said cladding layers being adjacent to the current-blocking layer.

4. An optoelectronic device according to any one of the preceding claims, wherein: The regrown conductive barrier layer grows onto the first current blocking layer, thereby forming the other of the n-doped layer and the p-doped layer.

5. An optoelectronic device according to any one of the preceding claims, wherein: The material of the contact layer, which is in electrical contact with the regrown conductive barrier layer covering the structured boundary, is grown on the regrown conductive barrier layer and optionally on the first current blocking layer.

6. An optoelectronic device according to any one of the preceding claims, further comprising a reflective dielectric layer deposited on the first current blocking layer.

7. An optoelectronic device according to any one of the preceding claims, wherein: The regrown conductive barrier layer includes a heterostructure of at least two semiconductor layers, and the at least two semiconductor layers include different material compositions and doping.

8. An optoelectronic device according to any one of the preceding claims, wherein: The thickness of the regrown conductive barrier layer is in the range of several tens of nm.

9. An optoelectronic device according to any one of the preceding claims, wherein: The regrown conductive barrier layer comprises at least one of the following: - a GaP layer, the GaP layer optionally being adjacent to the contact layer; - an InAlP layer, in particular a doped InAlP layer, said InAlP layer being adjacent to said active region; - a ZnSSe layer, the ZnSSe layer being adjacent to the active region; A heterostructure comprising at least a doped InGaAlP layer and a doped InAlP layer.

10. An optoelectronic device according to any one of the preceding claims, wherein: The first current blocking layer comprises a semiconductor multilayer comprising a plurality of layers of different doping types, in particular a pnpn stack when viewed from the direction of the active region.

11. An optoelectronic device according to any one of the preceding claims, wherein: The contact layer includes metal and / or transparent conductive oxide.

12. An optoelectronic device according to any one of the preceding claims, wherein: A portion of the regrown conductive barrier layer extends substantially parallel to at least one of the n-doped layer and the p-doped layer so as to surround the active layer, and further comprises: - a second current blocking layer arranged between the portion of the regrown conductive barrier layer and at least one of the n-doped layer and the p-doped layer, the second current blocking layer comprising an opening.

13. The optoelectronic device according to claim 12, wherein: At least one of the n-doped layer and the p-doped layer extends through the opening to connect the active region.

14. The optoelectronic device according to claims 12 to 13, wherein: The second current blocking layer comprises a semiconductor stack comprising a plurality of layers of different doping types, in particular an npnp multilayer when viewed from the direction of the active region.

15. An optoelectronic device according to any one of the preceding claims, wherein: The first current blocking layer and / or the second current blocking layer includes at least one of the following: - a thickness of about 100 nm or more; - the thickness of each of the plurality of layers is in the range of several tens of nm; - a material identical to one of the n-doped and p-doped layers, in particular a layer in electrically conductive contact with the regrown electrically conductive material; - One or more doped layers of InAlP semiconductor material.

16. An optoelectronic device according to any one of the preceding claims, wherein: The material of the first current blocking layer and / or the second current blocking layer includes more than 1E15 atoms / cm 3 The doping concentration is within the range of .

17. The optoelectronic device according to any of the preceding claims, further comprising a dielectric layer, in particular one of Al2O3 and / or SiO2, which covers the portion of the regrown conductive barrier layer facing away from the active region.

18. The optoelectronic device according to any of the preceding claims, further comprising a structured inclined sidewall, wherein the structured inclined sidewall extends from one of the contact layers that is in electrical contact with the regrown conductive barrier layer, along a first portion having a first angle and along a second portion having a second angle, toward another contact layer.

19. A method for processing an optoelectronic device, comprising the steps of: - providing a semiconductor stack on a growth substrate, the semiconductor stack having one of an n-doped layer and a p-doped layer and an active region arranged on a respective one of the n-doped layer and the p-doped layer; - growing a first current blocking layer on the active area; - providing a structured mask layer on the first current blocking layer, wherein a mask material is arranged on parts of the active area; - performing a first etching to form a mesa structure exposing the boundary of the active area; - regrowing a conductive barrier layer on the structured boundary of the active region, the regrown conductive barrier layer comprising a material adjacent to the active region, the material having a larger band gap than the active region; - providing a contact layer which is electrically coupled to the regrown conductive barrier layer covering the structured boundary of the active area and which is optionally arranged at least partially on the first current blocking layer.

20. The method according to claim 18, wherein: Providing a semiconductor stack includes one of the following: -Growing quantum well structures; -Growing multiple quantum well structures; -Growing heterostructures; - growing one or more quantum dots; and - growing one or more cladding layers, in particular undoped cladding layers, one of said cladding layers being adjacent to said current blocking layer.

21. The method according to claim 18 or 19, wherein: - the step of regrowing the conductive barrier layer comprises the step of regrowing the conductive barrier layer on the current blocking layer, and / or - the step of providing a contact layer comprises the step of depositing a contact layer material, in particular a metal or a transparent conductive oxide, at least partially on said regrown conductive barrier layer covering said borders of said active area.

22. The method according to any one of claims 18 to 20, further comprising the step of depositing a reflective dielectric layer on the first current blocking layer, the reflective dielectric layer comprising at least one of a DBR structure and / or a reflective material.

23. The method according to any one of claims 18 to 21, wherein: Regrowing the conductive barrier layer includes at least one of the following: - growing an InAlP layer, in particular a doped InAlP layer, adjacent to the active region; - growing a ZnSSe layer adjacent to the active region; - growing a heterostructure comprising at least a doped InGaAlP layer and a doped InAlP layer; - growing a GaP layer, optionally adjacent to the contact layer.

24. The method according to any one of claims 18 to 22, wherein: The regrowing of the conductive barrier layer comprises the following steps: - performing a second etch to remove a portion of the regrown conductive barrier layer surrounding the layer stack such that a portion of the regrown conductive barrier layer extending substantially parallel to at least one of the n-doped layer and the p-doped layer remains.

25. The method according to any one of claims 18 to 23, wherein: Setting up a semiconductor stack includes the following steps: - growing a second current blocking layer on one of the n-doped layer and the p-doped layer; - configuring the second current blocking layer to form an opening exposing a surface of one of the underlying n-doped layer and the p-doped layer; - growing a doped layer having the same doping type as one of the n-doped layer and the p-doped layer into the opening; - growing the active region on the doped layer and the structured second current blocking layer.

26. The method according to any one of claims 18 to 24, wherein: The step of growing the first current blocking layer and / or the second current blocking layer comprises the step of growing a plurality of differently doped layers, in particular a pnpn layer stack.

27. The method according to any one of claims 18 to 25, wherein: The first current blocking layer and / or the second current blocking layer includes at least one of the following: - a thickness of about 100 nm or more; - the thickness of each of the plurality of layers is in the range of several tens of nm; - a layer of the same material as one of the n-doped layer and the p-doped layer, in particular in conductive contact with the regrown conductive material; - One or more doped layers of InAlP semiconductor material.

28. The method according to any one of claims 18 to 26, wherein: The active region includes one of the following: - Quantum wells; -Multiple quantum wells; - Heterogeneous structures; as well as - One or more quantum dots. - one or more cladding layers, in particular undoped cladding layers, one of said cladding layers being adjacent to said current-blocking layer.

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