Soft decoding method, system, control platform and storage medium for a resolver

Abstract

The application discloses a kind of soft decoding method, system, control platform and storage medium of resolver, wherein, method is based on DSP chip and FPGA chip, including: by DSP chip generation enable signal, and enable signal is input to FPGA chip, wherein, FPGA chip generates high-frequency excitation signal applied to resolver according to enable signal;By DSP chip, the feedback signal of resolver is acquired, and the interrupt signal of FPGA chip is acquired, wherein, resolver generates feedback signal according to high-frequency excitation signal, and FPGA chip generates interrupt signal according to the phase delay time caused by resolver;By DSP chip, according to feedback signal and interrupt signal, resolver angle value and / or speed value are acquired.Thereby, by DSP chip enable FPGA chip, high-frequency excitation signal applied to resolver is generated by FPGA chip, so that, reduce the burden of DSP chip when excitation signal is applied to resolver, help to improve soft decoding speed and accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of resolver soft decoding, and particularly relates to a resolver soft decoding method, a computer readable storage medium, a resolver soft decoding system and a resolver. BACKGROUND

[0002] The resolver is widely used in motor drive and electronic technology application because of its high precision and strong anti-interference ability, and the size of the output voltage of the resolver changes with the rotor angular displacement, and the voltage amplitude of the output winding is in a sine and cosine function relationship with the rotor angle. However, the decoding chip used with the resolver has a high cost, therefore, the soft decoding of the resolver with high precision not only can save space in the design and manufacturing process, but also has a lower cost, which helps to reduce the overall cost of the product.

[0003] Then, the problem of the related art is that the soft decoding based on the DSP needs to control the part to generate the high-frequency excitation signal at the same time, and sample and demodulate the resolver feedback signal, which causes a large resource burden on the DSP and affects the processing capability of the DSP, and further, leads to low soft decoding efficiency and low soft decoding precision. SUMMARY

[0004] The present application aims to at least solve one of the technical problems in the related art. To this end, the first object of the present application is to provide a resolver soft decoding method, which can reduce the burden of the DSP chip when the excitation signal is applied to the resolver, and help to improve the soft decoding speed and precision.

[0005] The second object of the present application is to provide a computer readable storage medium.

[0006] The third object of the present application is to provide a resolver soft decoding system.

[0007] The fourth object of the present application is to provide a resolver.

[0008] To achieve the above object, the soft decoding method of the resolver according to an embodiment of the present application is based on a DSP chip and an FPGA chip, and comprises: generating an enable signal by the DSP chip, and inputting the enable signal to the FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the resolver according to the enable signal; acquiring a feedback signal of the resolver by the DSP chip, and acquiring an interrupt signal of the FPGA chip, wherein the resolver generates the feedback signal according to the high-frequency excitation signal, and the FPGA chip generates the interrupt signal according to a phase delay time caused by the resolver; and acquiring a resolver angle value and / or a speed value by the DSP chip according to the feedback signal and the interrupt signal.

[0009] The soft decoding method of the resolver according to an embodiment of the present application generates an enable signal by a DSP chip, and inputs the enable signal to an FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the resolver according to the enable signal, and then, a feedback signal of the resolver is acquired by the DSP chip, and an interrupt signal of the FPGA chip is acquired, wherein the resolver generates the feedback signal according to the high-frequency excitation signal, the FPGA chip generates the interrupt signal according to a phase delay time caused by the resolver, and a resolver angle value and / or a speed value are acquired by the DSP chip according to the feedback signal and the interrupt signal. Thus, the FPGA chip is enabled by the DSP chip, the high-frequency excitation signal applied to the resolver is generated by the FPGA chip, so as to reduce the burden of the DSP chip when the excitation signal is applied to the resolver, and to help improve the soft decoding speed and accuracy.

[0010] In addition, the soft decoding method of the resolver according to the above embodiment of the present application can also have the following additional technical features:

[0011] According to an embodiment of the present application, the feedback signal comprises a sine signal and a cosine signal.

[0012] According to an embodiment of the present application, the FPGA chip generates a high-frequency excitation signal applied to the resolver according to the enable signal, comprising: generating a high-frequency PWM signal by the FPGA chip according to the enable signal, and inputting the high-frequency PWM signal to an excitation signal amplification circuit; filtering the high-frequency PWM signal by the excitation signal amplification circuit, and converting the high-frequency PWM signal into the high-frequency excitation signal.

[0013] According to an embodiment of the present application, the excitation signal amplification circuit comprises a Boost voltage boosting unit, an excitation pre-amplification unit and an excitation power amplification unit.

[0014] According to one embodiment of the present application, the FPGA chip generates the interrupt signal according to the phase delay time caused by the resolver, including: recording, by the FPGA chip, the peak time and the valley time of the high-frequency excitation signal; recording, by the DSP chip, the peak time and the valley time of the feedback signal and feeding back to the FPGA chip; obtaining, by the FPGA chip, the phase delay time according to the peak time and the valley time of the high-frequency excitation signal and the peak time and the valley time of the feedback signal.

[0015] According to one embodiment of the present application, the obtaining of the resolver angle value and / or the speed value includes: determining, by the DSP chip, the peak sampling value and the valley sampling value of the sine signal and the cosine signal according to the interrupt signal; and performing, by the DSP chip, the arctangent calculation on the peak sampling value and the valley sampling value of the sine signal and the cosine signal to obtain the resolver angle value and / or the speed value.

[0016] According to one embodiment of the present application, the DSP chip obtains the feedback signal through a feedback signal sampler, wherein the feedback signal sampler includes a secondary side signal conditioning circuit.

[0017] To achieve the above object, the second aspect of the present application provides a computer readable storage medium, which stores a soft decoding program of a resolver, and the soft decoding program of the resolver is executed by a processor to implement the soft decoding method of the resolver according to the above embodiment of the present application.

[0018] The computer readable storage medium according to the embodiment of the present application can reduce the burden of the DSP chip when the excitation signal is applied to the resolver, and help to improve the soft decoding speed and accuracy by executing the soft decoding program of the resolver stored thereon.

[0019] To achieve the above object, the third aspect of the present application provides a soft decoding system of a resolver, which includes a DSP chip and an FPGA chip, wherein the DSP chip is configured to generate an enable signal and input the enable signal to the FPGA chip, and the FPGA chip is configured to generate a high-frequency excitation signal applied to the resolver according to the enable signal; the DSP chip is further configured to obtain a feedback signal of the resolver and an interrupt signal of the FPGA chip, wherein the resolver generates the feedback signal according to the high-frequency excitation signal, and the FPGA chip generates the interrupt signal according to the phase delay time caused by the resolver; and the DSP chip is further configured to obtain a resolver angle value and / or a speed value according to the feedback signal and the interrupt signal.

[0020] The soft decoding system of the resolver according to the embodiment of the present application generates an enable signal through a DSP chip and inputs the enable signal to an FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the resolver according to the enable signal, and further, the DSP chip acquires a feedback signal of the resolver and acquires an interrupt signal of the FPGA chip, wherein the resolver generates the feedback signal according to the high-frequency excitation signal, the FPGA chip generates the interrupt signal according to a phase delay time caused by the resolver, and the resolver angle value and / or the speed value are acquired by the DSP chip according to the feedback signal and the interrupt signal. Thus, the FPGA chip is enabled by the DSP chip, the high-frequency excitation signal applied to the resolver is generated through the FPGA chip, so as to reduce the burden of the DSP chip when the excitation signal is applied to the resolver, and to help improve the soft decoding speed and accuracy.

[0021] To achieve the above object, the control platform of the resolver according to the fourth aspect of the embodiment of the present application comprises the soft decoding system of the resolver according to the embodiment of the present application.

[0022] The control platform of the resolver according to the embodiment of the present application can reduce the burden of the DSP chip when the excitation signal is applied to the resolver by adopting the soft decoding system of the resolver, and help improve the soft decoding speed and accuracy.

[0023] Additional aspects and advantages of the present application will be described in the following description and become apparent from the following description or will be learned by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a flowchart of a soft decoding method of a resolver according to an embodiment of the present application;

[0025] Figure 2 is a flowchart of a soft decoding method of a resolver according to an embodiment of the present application;

[0026] Figure 3 is a flowchart of a soft decoding method of a resolver according to an embodiment of the present application;

[0027] Figure 4 is a timing diagram of an FPGA chip and an interrupt sampling point according to a specific embodiment of the present application;

[0028] Figure 5 is a flowchart of phase delay time calculation according to a specific embodiment of the present application;

[0029] Figure 6 is a flowchart of a soft decoding method of a resolver according to an embodiment of the present application;

[0030] Figure 7 is a flowchart of a method for calculating a resolver angle value and / or a speed value according to an embodiment of the present application;

[0031] Figure 8 is a structural diagram of a soft decoding system of a resolver according to an embodiment of the present application;

[0032] Figure 9 is a block diagram of a control platform of a resolver according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] Embodiments of the present application are described in detail below with reference to the accompanying drawings, in which the same or similar components have the same or similar designations and functions throughout various figures and / or like reference numerals, and embodiments described below are examples for explaining the present application and are not intended to be limiting of the present application.

[0034] A soft decoding method of a resolver, a computer readable storage medium, a soft decoding system of a resolver, and a resolver according to embodiments of the present application are described below with reference to the accompanying drawings.

[0035] Figure 1 is a flowchart of a soft decoding method of a resolver according to an embodiment of the present application.

[0036] Specifically, in some embodiments of the present application, a soft decoding method of a resolver is based on a DSP (Digital Signal Processing) chip and a FPGA (Field Programmable Gate Array) chip, as shown in Figure 1 The method includes the following steps.

[0037] S101, a DSP chip generates an enable signal and inputs the enable signal to a FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the resolver according to the enable signal.

[0038] It can be understood that, compared with a method of generating an excitation signal by using a DSP chip alone, in this embodiment of the present application, the excitation signal is generated by the DSP chip and the FPGA chip together, specifically, the DSP chip sends an enable signal to the FPGA chip, and the FPGA chip outputs a PWM signal of any high frequency immediately after receiving the enable signal, and the PWM signal is filtered and modulated by a hardware circuit to output a high-frequency excitation signal required by the resolver.

[0039] S102, acquiring, by the DSP chip, a feedback signal of the resolver and an interrupt signal of the FPGA chip, wherein the resolver generates the feedback signal according to a high-frequency excitation signal, and the FPGA chip generates the interrupt signal according to a phase delay time caused by the resolver.

[0040] It can be understood that, in the embodiment of the application, the feedback signal of the resolver is used to represent the rotor position at different moments, and the interrupt signal of the FPGA chip is used to trigger the DSP chip to sample the feedback signal in time.

[0041] S103, acquiring, by the DSP chip, a resolver angle value and / or a speed value according to the feedback signal and the interrupt signal.

[0042] It can be understood that, in the embodiment of the application, the feedback signal of the resolver is sampled in time after the DSP chip receives the interrupt signal output by the FPGA chip, in combination with the phase delay time caused by the resolver. Figure 2 It can be understood that, in the embodiment of the application, the feedback signal of the resolver is sampled in time after the DSP chip receives the interrupt signal output by the FPGA chip, in combination with the phase delay time caused by the resolver.

[0043] Specifically, in the above-mentioned embodiment of the application, when powered on for the first time, the FPGA chip is enabled by the DSP chip to generate a PWM signal of high-frequency excitation applied to the resolver, and the phase delay time caused by the resolver is acquired by the DSP chip in cooperation with the FPGA chip, and the sampling moment corresponding to the phase delay time is determined, and then the feedback signal of the resolver is sampled in time by the DSP chip when the interrupt signal of the FPGA chip is detected, wherein the feedback signal of the resolver is generated by the resolver according to the high-frequency excitation signal corresponding to the PWM signal of high-frequency excitation, the interrupt signal is generated by the FPGA chip according to the sampling moment, and the resolver angle value and / or the speed value are acquired by the DSP chip according to the sampled value. Thus, the burden of the DSP chip when applying the excitation signal to the resolver is reduced, which helps to improve the soft decoding speed and accuracy of the resolver and facilitates subsequent motor control.

[0044] Further, in some embodiments of the application, the feedback signal includes a sine signal and a cosine signal.

[0045] It can be understood that, in the embodiment of the application, the resolver can feed back the rotor position information at different moments to the DSP chip in the form of two-way sine signal and cosine signal.

[0046] Further, in some embodiments of the application, as Figure 3As shown, the FPGA chip generates a high-frequency excitation signal applied to the resolver according to the enable signal, including:

[0047] S201, the FPGA chip generates a high-frequency PWM signal according to the enable signal, and inputs the high-frequency PWM signal to the excitation signal amplification circuit.

[0048] It can be understood that in this embodiment of the application, the FPGA chip can output a high-frequency PWM signal to the excitation signal amplification circuit according to the enable signal from the DPS chip in each cycle (any frequency of 400K and above can be output due to the parallel advantage of FPGA).

[0049] S202, the excitation signal amplification circuit filters the high-frequency PWM signal and converts the high-frequency PWM signal into a high-frequency excitation signal.

[0050] It can be understood that in this embodiment of the application, the excitation signal amplification circuit can filter the high-frequency PWM signal output by the FPGA chip and convert it into a high-frequency excitation signal sinωt.

[0051] Further, in some embodiments of the application, the excitation signal amplification circuit includes a Boost unit, an excitation amplification front-end unit and an excitation power amplification unit.

[0052] It can be understood that in this embodiment of the application, the excitation signal amplification circuit increases the excitation voltage amplitude through the Boost unit, filters and applies common-mode voltage to the excitation signal through the excitation amplification front-end unit, and amplifies the driving capability of the excitation signal through the excitation power amplification unit.

[0053] It should be noted that in the above embodiments of the application, different types of resolver adjustment correspond to different amplification multiples of the Boost unit, and different driving capabilities of the resolver correspond to different amplification multiples of the excitation power amplification unit.

[0054] Further, in some embodiments of the application, the DSP chip acquires a feedback signal through a feedback signal sampler, wherein the feedback signal sampler includes a secondary signal conditioning circuit.

[0055] Specifically, in this embodiment of the application, the feedback signal sampler amplifies the sine signal and the cosine signal of the resolver respectively, and through the secondary signal conditioning circuit, the sine signal and the cosine signal are conditioned to a signal range acceptable by the ADC (Analog-to-digital converter) sampling circuit of the DSP chip, for the DSP chip to calculate the resolver angle value and / or speed value.

[0056] Further, in some embodiments of the present application, as shown in Figure 4 the FPGA chip generates an interrupt signal according to the phase delay time caused by the resolver, including:

[0057] S301, the FPGA chip records the peak time and valley time of the high-frequency excitation PWM signal.

[0058] It can be understood that in this embodiment of the present application, the FPGA chip records the peak time (i.e. the time t1 when the high-frequency excitation signal appears peak as shown in Figure 2 ) and the valley time (i.e. the time t2 when the high-frequency excitation signal appears valley as shown in Figure 2 ) of the high-frequency excitation PWM signal.

[0059] S302, the DSP chip records the peak time and valley time of the feedback signal and feeds back to the FPGA chip.

[0060] It can be understood that in this embodiment of the present application, the DSP chip records the peak time (i.e. the time d1 when the feedback signal appears peak as shown in Figure 2 ) and the valley time (i.e. the time d2 when the feedback signal appears valley as shown in Figure 2 ) of the feedback signal and feeds back to the FPGA chip.

[0061] S303, the FPGA chip acquires the phase delay time according to the peak time and valley time of the high-frequency excitation PWM signal and the peak time and valley time of the feedback signal.

[0062] It can be understood that in this embodiment of the present application, the first phase delay time is determined according to the difference between the peak time of the high-frequency excitation PWM signal and the peak time of the feedback signal, and the second phase delay time is determined according to the valley time of the high-frequency excitation PWM signal and the valley time of the feedback signal, and then the final phase delay time is determined by verifying whether the first phase delay time and the second phase delay time are consistent.

[0063] The process of generating the interrupt signal by the FPGA chip will be described in detail below in combination with Figure 5 and specific embodiments of the present application. Specifically, as shown in Figure 5 , after the DSP chip is powered on and the FPGA chip outputs the high-frequency excitation PWM signal triggered by the enable signal output by the DSP chip, step S1 is executed.

[0064] S10, the FPGA chip records the peak time t1 and the valley time t2 of the high-frequency excitation PWM signal.

[0065] S11, the DSP chip records the peak time d1 and the valley time d2 of the feedback signal and feeds back to the FPGA chip.

[0066] S12, the FPGA chip verifies whether d1-t1 is equal to d2-t2, if yes, step S13 is executed, if not, step S10 is returned to execute.

[0067] S13, the FPGA chip determines the phase delay time delay=d1-t1=d2-t2, and sets the trigger interrupt signal to t1+delay time and t2+delay time.

[0068] S14, the FPGA chip generates the interrupt signal at t1+delay time and t2+delay time and outputs to the DSP chip.

[0069] Further, in some embodiments of the present application, as shown in Figure 6 the rotation angle value and / or the speed value are obtained, including:

[0070] S401, the DSP chip determines the peak sampling value and the valley sampling value of the sine signal and the cosine signal according to the interrupt signal.

[0071] It can be understood that in this embodiment of the present application, when the DSP chip receives the interrupt signal output by the FPGA chip, the feedback signal (sine signal and cosine signal) of the resolver is sampled to obtain the peak sampling value and the valley sampling value of the sine signal and the cosine signal.

[0072] S402, the DSP chip performs arctangent calculation on the peak sampling value and the valley sampling value of the sine signal and the cosine signal to obtain the rotation angle value and / or the speed value.

[0073] It can be understood that in this embodiment of the present application, after the peak and valley values of the sine signal and the cosine signal are sampled by the DSP chip, the rotation angle is obtained through arctangent calculation and the corresponding interval, and then the speed of the motor is calculated.

[0074] In the following Figure 7 and specific embodiments of the present application, the resolver calculation is described accordingly, specifically, as shown in Figure 7 after the FPGA chip outputs the interrupt signal, step S20 is executed:

[0075] S20, the DSP chip judges whether the peak sampling and the valley sampling of the sine signal and the cosine signal are completed, if yes, step S21 is executed, if not, the peak sampling and the valley sampling of the sine signal and the cosine signal are continued.

[0076] S21, the DSP chip determines the peak sampling value and the trough sampling value of the sine signal and the cosine signal.

[0077] S22, the DSP chip performs an arctangent calculation on the peak sampling value and the trough sampling value of the sine signal and the cosine signal, and cooperates with the corresponding angle interval to finally obtain the resolver angle value and / or the speed value.

[0078] Specifically, in some embodiments of the present application, when powered on for the first time, the DSP chip generates an enable signal and inputs the enable signal to the FPGA chip, wherein the FPGA chip generates a high-frequency excitation PWM signal applied to the resolver according to the enable signal, the resolver generates a feedback signal according to the high-frequency excitation signal, and at the same time, the DSP chip scans the entire feedback outer envelope signal of the resolver, cooperates with the FPGA chip to jointly confirm the phase delay time between the feedback signal and the excitation signal caused by the resolver, and records the delay time as the corresponding sampling time. After that, the FPGA chip outputs an interrupt signal to the DSP chip according to the recorded sampling time. Thus, the DSP chip obtains the feedback sine sampling value and the cosine sampling value at the current time according to the interrupt signal, and finally obtains the resolver angle value and / or the speed value.

[0079] In summary, according to the soft decoding method of the resolver proposed in the embodiments of the present application, the DSP chip generates an enable signal and inputs the enable signal to the FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the resolver according to the enable signal, and then the DSP chip obtains the feedback signal of the resolver and the interrupt signal of the FPGA chip, wherein the resolver generates a feedback signal according to the high-frequency excitation signal, the FPGA chip generates an interrupt signal according to the phase delay time caused by the resolver, and the DSP chip obtains the resolver angle value and / or the speed value according to the feedback signal and the interrupt signal. Thus, the DSP chip enables the FPGA chip, and the FPGA chip generates a high-frequency excitation signal applied to the resolver, thereby reducing the burden of the DSP chip when applying the excitation signal to the resolver, which helps to improve the soft decoding speed and accuracy.

[0080] Based on the soft decoding method of the resolver of the foregoing embodiments of the present application, the embodiments of the present application propose a computer readable storage medium having a resolver soft decoding program stored thereon, which, when executed by a processor, implements the soft decoding method of the resolver of the foregoing embodiments of the present application.

[0081] It should be understood that the specific implementation of the computer readable storage medium of the embodiments of the present application can refer to the specific implementation of the soft decoding method of the resolver of the foregoing embodiments of the present application. To reduce redundancy, it will not be described here.

[0082] In summary, the computer readable storage medium according to the embodiment of the present application can reduce the burden of the DSP chip when the excitation signal is applied to the resolver by executing the soft decoding program stored thereon, and help to improve the soft decoding speed and accuracy.

[0083] Figure 5 is a block schematic diagram of a soft decoding system of a resolver according to an embodiment of the present application.

[0084] Specifically, in some embodiments of the present application, as shown in Figure 8 The soft decoding system 1000 of the resolver includes a DSP chip 100 and an FPGA chip 200.

[0085] The DSP chip 100 is configured to generate an enable signal and input the enable signal to the FPGA chip 200, and the FPGA chip 200 generates a high-frequency excitation signal applied to the resolver according to the enable signal; the DSP chip 100 is further configured to acquire a feedback signal of the resolver and acquire an interrupt signal of the FPGA chip 200, wherein the resolver generates the feedback signal according to the high-frequency excitation signal, and the FPGA chip 200 generates the interrupt signal according to the phase delay time caused by the resolver; and the DSP chip 100 is further configured to acquire a resolver angle value and / or a speed value according to the feedback signal and the interrupt signal.

[0086] Further, in some embodiments of the present application, the feedback signal includes a sine signal and a cosine signal.

[0087] Further, in some embodiments of the present application, as shown in Figure 8 The FPGA chip 200 generates a high-frequency PWM signal according to the enable signal and inputs the high-frequency PWM signal to an excitation signal amplification circuit; and the excitation signal amplification circuit filters the high-frequency PWM signal and converts the high-frequency PWM signal into a high-frequency excitation signal.

[0088] Further, in some embodiments of the present application, the excitation signal amplification circuit includes a Boost voltage boosting unit, an excitation pre-amplification unit and an excitation power amplification unit.

[0089] Further, in some embodiments of the present application, the FPGA chip 200 records the peak time and the valley time of the high-frequency excitation signal; the DSP chip 100 records the peak time and the valley time of the feedback signal and feeds back to the FPGA chip 200; and the FPGA chip 200 acquires the phase delay time according to the peak time and the valley time of the high-frequency excitation signal and the peak time and the valley time of the feedback signal.

[0090] Further, in some embodiments of the present application, the obtaining the resolver angle value and / or the speed value comprises: determining, by the DSP chip 100, the peak sampling value and the valley sampling value of the sine signal and the cosine signal according to the interrupt signal; and performing, by the DSP chip 100, the arctangent calculation on the peak sampling value and the valley sampling value of the sine signal and the cosine signal to obtain the resolver angle value and / or the speed value.

[0091] Further, in some embodiments of the present application, as shown in Figure 8 the DSP chip 100 obtains the feedback signal through a feedback signal sampler, wherein the feedback signal sampler comprises a secondary side signal conditioning circuit.

[0092] It should be understood that the specific implementation of the soft decoding system 100 of the resolver according to the embodiments of the present application corresponds to the specific implementation of the soft decoding method of the resolver according to the aforementioned embodiments of the present application one by one, and to reduce redundancy, it will not be repeated here.

[0093] In summary, according to the soft decoding system of the resolver according to the embodiments of the present application, the DSP chip generates an enable signal and inputs the enable signal to the FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the resolver according to the enable signal, and further, the DSP chip obtains the feedback signal of the resolver and the interrupt signal of the FPGA chip, wherein the resolver generates the feedback signal according to the high-frequency excitation signal, the FPGA chip generates the interrupt signal according to the phase delay time caused by the resolver, and the DSP chip obtains the resolver angle value and / or the speed value according to the feedback signal and the interrupt signal. Therefore, the FPGA chip is enabled by the DSP chip, and the high-frequency excitation signal applied to the resolver is generated by the FPGA chip, thereby reducing the burden of the DSP chip when applying the excitation signal to the resolver, which helps to improve the soft decoding speed and accuracy.

[0094] Figure 9 is a block schematic diagram of a control platform of a resolver according to an embodiment of the present application.

[0095] Specifically, in some embodiments of the present application, as shown in Figure 9 the control platform 2000 of the resolver comprises the soft decoding system 1000 of the resolver according to the aforementioned embodiments of the present application.

[0096] It should be understood that the specific implementation of the control platform 2000 of the resolver according to the embodiments of the present application can refer to the specific implementation of the soft decoding method of the resolver according to the aforementioned embodiments of the present application, and to reduce redundancy, it will not be repeated here.

[0097] In summary, the control platform of the resolver according to the embodiment of the application can reduce the burden of the DSP chip when the excitation signal is applied to the resolver, and help to improve the soft decoding speed and accuracy by using the soft decoding system of the resolver.

[0098] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a list of executable instructions for implementing logic functions, and can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor- based system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions, or in conjunction with which the instructions can be executed. For purposes of this specification, a "computer-readable medium" can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection having one or more wires (electrical apparatus), a portable computer diskette (magnetic apparatus), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber (optical apparatus), and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium can even be paper or another suitable medium upon which the program can be printed, as the program can be electronically captured, for example, via the optical scanner of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and stored in a computer memory.

[0099] It should be understood that various parts of the present application can be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, a plurality of steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, and as in another embodiment, any of the following technologies known in the art or their combinations can be used: discrete logic circuit with logic gates for implementing logic functions on data signals, application specific integrated circuit with suitable combination logic gates, programmable gate array (PGA), field programmable gate array (FPGA), etc.

[0100] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0101] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the purpose of facilitating the description of the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0102] In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0103] In the present application, unless otherwise specifically defined and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integral; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise specifically limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0104] In the present application, unless otherwise explicitly specified and limited, a first feature is "on" or "under" a second feature can mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature is "over", "above" and "on top of" the second feature can mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature. The first feature is "under", "below" and "underneath" the second feature can mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is horizontally lower than the second feature.

[0105] Although the embodiments of the present application have been shown and described above, it is to be understood that the above-described embodiments are exemplary only, and are not to be construed as limiting the present application, and that changes, modifications, substitutions and variations can be made thereto by those skilled in the art without departing from the scope of the present application.

Claims

1. A soft decoding method for a rotary transformer, characterized in that, Based on DSP chips and FPGA chips, the method includes: The DSP chip generates an enable signal and inputs the enable signal to the FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the rotary transformer based on the enable signal; The DSP chip obtains the feedback signal from the rotary transformer and the interrupt signal from the FPGA chip, wherein the rotary transformer generates the feedback signal based on the high-frequency excitation signal, and the FPGA chip generates the interrupt signal based on the phase delay time caused by the rotary transformer. The DSP chip obtains the resolver angle value and / or speed value based on the feedback signal and the interrupt signal; The FPGA chip generates the interrupt signal based on the phase delay time caused by the rotary transformer, including: The FPGA chip records the peak and trough times of the high-frequency excitation signal; The DSP chip records the peak and trough times of the feedback signal and feeds them back to the FPGA chip. The FPGA chip obtains the phase delay time based on the peak and valley times of the high-frequency excitation signal and the peak and valley times of the feedback signal.

2. The soft decoding method for a rotary transformer according to claim 1, characterized in that, The feedback signal includes a sine signal and a cosine signal.

3. The soft decoding method for a rotary transformer according to claim 2, characterized in that, The FPGA chip generates a high-frequency excitation signal applied to the resolver based on the enable signal, including: The FPGA chip generates a high-frequency PWM signal based on the enable signal, and inputs the high-frequency PWM signal to the excitation signal amplification circuit; The high-frequency PWM signal is filtered by the excitation signal amplification circuit and converted into the high-frequency excitation signal.

4. The soft decoding method for a rotary transformer according to claim 3, characterized in that, The excitation signal amplification circuit includes a boost unit, an excitation amplification preamplifier unit, and an excitation power amplification unit.

5. The soft decoding method for a rotary transformer according to claim 2, characterized in that, The acquisition of the rotation angle value and / or velocity value includes: The DSP chip determines the peak and valley sampling values ​​of the sine and cosine signals based on the interrupt signal. The DSP chip performs arctangent calculation on the peak and valley sample values ​​of the sine and cosine signals to obtain the resolver angle value and / or velocity value.

6. The soft decoding method for a rotary transformer according to claim 1, characterized in that, The DSP chip acquires the feedback signal through a feedback signal sampler, wherein the feedback signal sampler includes a secondary signal conditioning circuit.

7. A computer-readable storage medium, characterized in that, It stores a software decoding program for a rotary transformer, which, when executed by a processor, implements the software decoding method for a rotary transformer as described in any one of claims 1-6.

8. A soft decoding system for a rotary transformer, characterized in that, The system includes a DSP chip and an FPGA chip, wherein, The DSP chip is used to generate an enable signal and input the enable signal to the FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the rotary transformer according to the enable signal; The DSP chip is also used to acquire the feedback signal of the rotary transformer and the interrupt signal of the FPGA chip, wherein the rotary transformer generates the feedback signal according to the high-frequency excitation signal, and the FPGA chip generates the interrupt signal according to the phase delay time caused by the rotary transformer. The DSP chip is also used to obtain the resolver angle value and / or speed value based on the feedback signal and the interrupt signal; Specifically, the FPGA chip records the peak and valley times of the high-frequency excitation signal; the DSP chip records the peak and valley times of the feedback signal and feeds them back to the FPGA chip; and the FPGA chip obtains the phase delay time based on the peak and valley times of the high-frequency excitation signal and the peak and valley times of the feedback signal.

9. A control platform for a rotary transformer, characterized in that, The control platform includes the soft decoding system for the rotary transformer according to claim 8.

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