A method for suppressing leakage current in static testing of semiconductor power devices

Abstract

The application discloses a kind of semiconductor power device static test leakage current suppression method, comprising the following operating steps: cooperate with three coaxial interface to carry out PCB design, in PCB design stage, optimization design is carried out using Guard line technology, Guard line is all enclosed in high voltage line, i.e., Hi line and SENSE Hi line, while avoiding contact with low voltage line, i.e., Lo line and SENSE Lo line, realize the equal potential surrounding protection of input signal line, while realizing the leakage current of connecting line, test fixture and auxiliary equipment is suppressed;Instrument is connected with PCB through double-end three coaxial interface, and the three coaxial interface of instrument is connected with the three coaxial interface on PCB board.The semiconductor power device static test leakage current suppression method disclosed in the application utilizes the Guard line of three coaxial interface, realizes the suppression of leakage current on connecting line, test fixture and auxiliary equipment, effectively improves the accuracy of leakage current test in power device static test, and enhances the reliability of system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of static testing of semiconductor power devices, and particularly relates to a method for suppressing leakage current in static testing of semiconductor power devices. BACKGROUND

[0002] The method for suppressing leakage current in static testing of semiconductor power devices is a method for performing static testing of semiconductor power devices. Leakage current of a semiconductor power device generally refers to a small unintended current generated in the device due to imperfections of materials, such as crystal defects, impurities, and interface states, in the absence of an external signal or in an off state. The presence of leakage current may cause additional power consumption in the power device. In static testing of the power device, accurate measurement of leakage current is crucial for evaluating the insulation performance of the device. With the continuous development of technology, people have higher and higher requirements for the method for suppressing leakage current in static testing of semiconductor power devices.

[0003] The existing method for static testing of semiconductor power devices has certain drawbacks in use. Although the existing leakage current testing method can suppress leakage current to a certain extent, non-target leakage current generated by other parts of the test circuit, such as connecting lines, test fixtures, and auxiliary equipment, may interfere with the test results and cause measurement errors. Therefore, it is necessary to effectively suppress leakage current generated by circuit parts other than the power device under test when performing leakage current testing of semiconductor power devices. To this end, the present application provides a method for suppressing leakage current in static testing of semiconductor power devices. SUMMARY

[0004] The technical problem solved by the present application is that the present application provides a method for suppressing leakage current in static testing of semiconductor power devices, which uses the Guard line of a three-coaxial interface to suppress leakage current on connecting lines, test fixtures, and auxiliary equipment, effectively improves the accuracy of leakage current testing in static testing of power devices, enhances the reliability of the system, and effectively solves the problems in the background art.

[0005] The technical solution adopted by the present application to achieve the above-mentioned purpose is as follows: a method for suppressing leakage current in static testing of semiconductor power devices, comprising the following operation steps:

[0006] S1: Cooperate with a three-coaxial interface to design a PCB. In the PCB design stage, the Guard line technology is used for optimization design. The Guard line surrounds all high-voltage lines, i.e. Hi lines and SENSE Hi lines, while avoiding contact with low-voltage lines, i.e. Lo lines and SENSE Lo lines, to realize equal-potential ring protection of input signal lines and suppression of leakage current of connecting lines, test fixtures, and auxiliary equipment.

[0007] S2: The instrument is connected to the PCB through the double-end three-coaxial interface, and the three-coaxial interface of the instrument is connected to the three-coaxial interface on the PCB, so as to avoid the introduction of additional noise or error caused by poor contact;

[0008] S3: The MOS tube to be tested is inserted into the socket, and the semiconductor power device MOS tube to be tested is inserted into the special test socket on the PCB, so as to ensure that the MOS tube is correctly and accurately electrically connected to the test system, and to prepare for the subsequent leakage current test;

[0009] S4: Start the leakage current static test, and the experimental environment required for the leakage current test has been built, so the leakage current static test of the MOS tube can be started;

[0010] S5: The high level output of the Hi end of the instrument and the low level output of the Lo end are that the Hi port and the Lo port of the instrument output the set high level and low level respectively, and the voltage is transmitted from the double-port three-coaxial connection line to the Hi end and the Lo end of the PCB, and then is added to the D end and the S end of the semiconductor power device MOS tube to be tested through the special test socket;

[0011] S6: The instrument displays the leakage current of the MOS tube, and since the level of the Guard line on the PCB is consistent with the Hi end, the leakage current generated by the circuit part outside the measured power device is suppressed, so that the leakage current measured by the instrument is the leakage current of the MOS tube itself;

[0012] S7: The leakage current static test is completed, and the leakage current static test of the MOS tube is completed, and the accuracy of the leakage current test is improved through the method.

[0013] As a preferred technical solution of the present application, the three-coaxial interface, the leakage resistance and the leakage capacitor, the measured semiconductor power device DUT and the PCB, the PCB is provided with a Hi line, a SENSE Hi line, a Guard line, a Lo line and a SENSE Lo line, the three-coaxial interface is used to provide high and low levels to the measured semiconductor power device DUT and measure the leakage current of the measured semiconductor power device DUT, and the three-coaxial interface comprises a center signal line, a Guard line and a GROUND line.

[0014] As a preferred technical solution of the present application, the center signal line is located at the center of the three-coaxial interface, and the purpose is to provide high and low levels to the measured semiconductor power device DUT and measure the leakage current of the measured semiconductor power device DUT, the high level is transmitted through the Hi line in the three-coaxial interface, the low level is transmitted through the Lo line in the three-coaxial interface, the stability and anti-interference ability of the signal are enhanced, and the accuracy of the leakage current test is improved.

[0015] As a preferred technical solution of the present application, the Guard line is in the middle layer of the three coaxial interface, and surrounds the Hi line and the Lo line of the center signal line respectively, wherein the potential of the Guard line is equal to the potential of the Hi line, and the potential matching ensures that the current on the Hi line will not leak through the Guard line, thereby realizing the equipotential surrounding protection of the input signal line.

[0016] As a preferred technical solution of the present application, the GROUND line is in the outermost layer of the three coaxial interface, and the GROUND line in the outermost layer of the Hi line and the GROUND line in the outermost layer of the Lo line are connected together to provide a common reference potential for the center signal line in the three coaxial interface, thereby ensuring the accuracy and stability of the signal.

[0017] As a preferred technical solution of the present application, the leakage resistance and the leakage capacitance come from the connecting lines, test fixtures and auxiliary equipment in the leakage current test loop from the Hi line, the Guard line to the Lo line, including the leakage resistance R and the leakage capacitance C between the Hi line and the Guard line and the leakage resistance R and the leakage capacitance C between the Lo line and the Guard line.

[0018] As a preferred technical solution of the present application, the leakage resistance R and the leakage capacitance C do not exist leakage current, and since the potential of the Hi line is equal to the potential of the Guard line, the current of the Hi line will not leak to the Guard line through the leakage resistance R and the leakage capacitance C.

[0019] As a preferred technical solution of the present application, the leakage resistance R and the leakage capacitance C exist leakage current, and since the potential of the Guard line is equal to the potential of the Hi line, the leakage current of the Guard line will flow to the Lo line through the leakage resistance R and the leakage capacitance C, and will not flow through the measured semiconductor power device DUT, the leakage current of the Guard line to the Lo line is provided by the Guard line voltage, the Guard line voltage is obtained after the Hi line passes through the voltage follower, and since the voltage follower is a high-impedance input, the current of the Guard line has no effect on the current of the Hi line, so the leakage current flowing through the measured semiconductor power device DUT is the current output by the instrument on the Hi line.

[0020] Beneficial effects: compared with the prior art, the application provides a semiconductor power device static test leakage current suppression method, which has the following beneficial effects: the semiconductor power device static test leakage current suppression method uses the Guard line of the three coaxial interfaces to suppress the leakage current on the connecting line, test fixture and auxiliary equipment, effectively improves the accuracy of the leakage current test in the static test of the power device, and enhances the reliability of the system; the method is simple and easy to implement, and high-precision leakage current test can be realized by cooperating with PCB design, which reduces the operation difficulty, reduces the additional equipment investment and maintenance cost, and improves the economy of the test; the method is not only suitable for semiconductor power device leakage current test, but also can be popularized to other electronic test and measurement fields, improves the performance and reliability of the electronic system, and the semiconductor power device static test leakage current suppression method has simple structure, convenient operation and better effect than the traditional method. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 It is a semiconductor power device static test leakage current suppression method structure diagram of the application.

[0022] Figure 2 It is a semiconductor power device static test leakage current suppression method structure diagram of the application.

[0023] Figure 3 It is a semiconductor power device static test leakage current suppression method structure diagram of the application.

[0024] In the figure: 1, three coaxial interfaces; 2, leakage resistance and leakage capacitance; 3, the measured semiconductor power device DUT; 4, Hi line; 5, SENSE Hi line; 6, Guard line; 7, Lo line; 8, SENSE Lo line. DETAILED DESCRIPTION

[0025] The technical solutions of the application will be described clearly and completely below in combination with the drawings and specific embodiments, but those skilled in the art will understand that the following described embodiments are part of the embodiments of the application, not all the embodiments, and are only used to illustrate the application, and should not be regarded as limiting the scope of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application. The specific conditions are not specified in the embodiments, and are carried out according to the conventional conditions or the conditions recommended by the manufacturer. The reagents or instruments used are not specified by the manufacturer, and are conventional products that can be purchased on the market.

[0026] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0028] like Figures 1-3 As shown, a method for suppressing leakage current during static testing of semiconductor power devices includes the following steps:

[0029] S1: PCB design is carried out in conjunction with the three coaxial interfaces. During the PCB design stage, the Guard line technology is used for optimization design. The Guard line surrounds all the high voltage lines, namely Hi line and SENSE Hi line, while avoiding contact with the low voltage lines, namely Lo line and SENSELo line, to achieve equipotential protection of the input signal lines, and at the same time suppress leakage current of the connection lines, test fixtures and auxiliary equipment.

[0030] S2: The instrument is connected to the PCB via a dual-ended three-coaxial interface. Connecting the instrument's three-coaxial interface to the three-coaxial interface on the PCB avoids introducing additional noise or error due to poor contact.

[0031] S3: Insert the MOSFET under test into the socket. Insert the MOSFET into the dedicated test socket on the PCB board to ensure that the electrical connection between the MOSFET and the test system is correct, in order to prepare for the subsequent leakage current test.

[0032] S4: Start the static leakage current test. The experimental environment required for the leakage current test has been set up and the static leakage current test of the MOSFET can begin.

[0033] S5: The high level output of the Hi terminal and the low level output of the Lo terminal of the instrument refers to the high level and low level output of the Hi terminal and the Lo terminal of the instrument respectively, and the voltage is transmitted from the double-terminal triaxial connecting line to the Hi terminal and the Lo terminal of the PCB board and then added to the D terminal and the S terminal of the semiconductor power device MOS tube to be tested through the special test socket;

[0034] S6: The instrument displays the drain current of the MOS tube. Since the level of the Guard line on the PCB board is consistent with that of the Hi terminal, the drain current generated by the circuit part outside the power device to be tested is inhibited, so that the drain current measured by the instrument is the drain current of the MOS tube itself;

[0035] S7: The static test of the drain current is completed, and the static test of the drain current of the MOS tube is completed, and the accuracy of the drain current test is improved through the method.

[0036] Further, the triaxial interface 1, the leakage resistance and the leakage capacitance 2, the semiconductor power device DUT 3 and the PCB board, the Hi line 4, the SENSE Hi line 5, the Guard line 6, the Lo line 7 and the SENSE Lo line 8 are arranged on the PCB board, the triaxial interface 1 is used to provide high and low levels to the semiconductor power device DUT 3 to be tested and measure the drain current of the semiconductor power device DUT 3 to be tested, and the triaxial interface 1 includes a center signal line, a Guard line 6 and a GROUND line.

[0037] Further, the center signal line is in the center of the triaxial interface 1, which is used to provide high and low levels to the semiconductor power device DUT 3 to be tested and measure the drain current of the semiconductor power device DUT 3 to be tested, the high level is transmitted through the Hi line 4 in the triaxial interface 1, and the low level is transmitted through the Lo line 7 in the triaxial interface 1, which enhances the stability and anti-interference ability of the signal and improves the accuracy of the drain current test.

[0038] Further, the Guard line 6 is in the middle layer of the triaxial interface 1 and surrounds the Hi line 4 and the Lo line 7 of the center signal line respectively, wherein the potential of the Guard line 6 is equal to that of the Hi line 4, and the potential matching ensures that the current on the Hi line 4 will not leak through the Guard line 6, realizing the equipotential surrounding protection of the input signal line.

[0039] Further, the GROUND line is in the outermost layer of the triaxial interface 1, and the GROUND line in the outermost layer of the Hi line 4 and the GROUND line in the outermost layer of the Lo line 7 are connected together to provide a common reference potential for the center signal line in the triaxial interface 1, ensuring the accuracy and stability of the signal.

[0040] Further, the leakage resistance R1 and the leakage capacitance C1 do not have leakage current, because the potential of the Hi line 4 is equal to the potential of the Guard line 6, the current of the Hi line 4 will not leak to the Guard line 6 through the leakage resistance R1 and the leakage capacitance C1.

[0041] Further, the leakage resistance R1 and the leakage capacitance C1 do not have leakage current, because the potential of the Hi line 4 is equal to the potential of the Guard line 6, the current of the Hi line 4 will not leak to the Guard line 6 through the leakage resistance R1 and the leakage capacitance C1.

[0042] Further, the leakage resistance R1 and the leakage capacitance C1 do not have leakage current, because the potential of the Hi line 4 is equal to the potential of the Guard line 6, the current of the Hi line 4 will not leak to the Guard line 6 through the leakage resistance R1 and the leakage capacitance C1.

[0043] Embodiment:

[0044] Figure 1 A kind of conductor power device static test leakage current suppression method structure diagram, including three coaxial interfaces 1, leakage resistance and leakage capacitance 2 and the measured semiconductor power device DUT 3;

[0045] Three coaxial interfaces are used to provide high and low levels for the measured semiconductor power device DUT and measure the leakage current of the measured semiconductor power device DUT.Three coaxial interfaces include center signal line (Hi line and Lo line), Guard line (shielding net) and GROUND line (ground line);

[0046] Center signal line is in the center of three coaxial interfaces, the purpose is to provide high and low levels for the measured power device DUT and measure the leakage current of DUT, high level is transmitted by Hi line in three coaxial interfaces, low level is transmitted by Lo line in three coaxial interfaces, this separation design enhances the stability and anti-interference ability of signal, improves the accuracy of leakage current test;

[0047] The Guard line is in the middle layer of the three coaxial interface, and is respectively surrounded around the Hi line and the Lo line of the center signal line, wherein the potential of the Guard line is equal to the potential of the Hi line, and the potential matching ensures that the current on the Hi line will not leak through the Guard line, realizes the equipotential surrounding protection of the input signal line, and thus protects the integrity of the signal; the two Guard lines are connected together to form a continuous shielding path, further enhances the anti-interference ability, prevents external leakage current from reaching the input port, and affects the output voltage of the port, and meanwhile realizes the suppression of leakage current of the connecting line, test fixture and auxiliary equipment;

[0048] The GROUND line is in the outermost layer of the three coaxial interface, and the GROUND line in the outermost layer of the Hi line and the GROUND line in the outermost layer of the Lo line are connected together to provide a common reference potential for the center signal line in the three coaxial interface, and ensure the accuracy and stability of the signal;

[0049] The leakage resistance and the leakage capacitance come from the connecting line, the test fixture and the auxiliary equipment in the leakage current test loop from the Hi line, the Guard line to the Lo line, including the leakage resistance R1 and the leakage capacitance C1 between the Hi line and the Guard line, and the leakage resistance R2 and the leakage capacitance C2 between the Lo line and the Guard line;

[0050] The leakage resistance R1 and the leakage capacitance C1 do not exist leakage current, and since the potential of the Hi line is equal to the potential of the Guard line, the current of the Hi line will not leak to the Guard line through the leakage resistance R1 and the leakage capacitance C1;

[0051] The leakage resistance R2 and the leakage capacitance C2 exist leakage current, and since the potential of the Guard line is equal to the potential of the Hi line, the leakage current of the Guard line will flow to the Lo line through the leakage resistance R2 and the leakage capacitance C2, and will not pass through the measured semiconductor power device DUT, and the leakage current from the Guard line to the Lo line is provided by the Guard line voltage, and the Guard line voltage is obtained after the Hi line passes through the voltage follower, and since the voltage follower is a high-impedance input, the current of the Guard line has no effect on the current of the Hi line, and thus the leakage current flowing through the measured semiconductor power device DUT is the current output by the instrument on the Hi line.

[0052] The measured semiconductor power device DUT supports measuring various types of semiconductor power devices, such as MOS tubes, IGBTs and other power devices.

[0053] Figure 2 A PCB design corresponding to a semiconductor power device static test leakage current suppression method;

[0054] 4 is the Hi line, and provides a high voltage for the measured power device DUT;

[0055] 5 is SENSE Hi line, and Hi line is equal potential;

[0056] 6 is Guard line, and Hi line is equal potential, respectively, to surround the Hi line and SENSE Hi line, while avoiding contact with low-voltage lines (Lo line and SENSE Lo line).

[0057] 7 is Lo line, to provide low level for the measured power device DUT;

[0058] 8 is SENSE Lo line, and Lo line is equal potential.

[0059] Three coaxial interfaces cooperate with Guard line to suppress leakage current on connecting lines, test fixtures and auxiliary equipment.

[0060] Figure 3 It is a flow chart of a semiconductor power device static test leakage current suppression method;

[0061] S1 cooperates with three coaxial interfaces for PCB design refers to the PCB design stage, using Guard line technology for optimization design. Guard line surrounds all high-voltage lines (Hi line and SENSE Hi line), while avoiding contact with low-voltage lines (Lo line and SENSE Lo line), to achieve equal potential ring protection of input signal lines, and to suppress leakage current on connecting lines, test fixtures and auxiliary equipment;

[0062] S2 instrument is connected to PCB through double-ended three coaxial interface refers to connecting the three coaxial interface of the instrument with the three coaxial interface on the PCB board, to avoid contact failure to introduce additional noise or error;

[0063] S3 inserts the MOS tube to be measured into the socket refers to inserting the semiconductor power device MOS tube to be measured into the special test socket on the PCB board, to ensure that the MOS tube is correctly connected to the test system, and to prepare for the following leakage current test;

[0064] S4 starts leakage current static test refers to that the experimental environment required for leakage current test has been set up, and the leakage current static test of MOS tube can be started;

[0065] S5 instrument outputs high level at Hi end and low level at Lo end refers to that the Hi port and Lo port of the instrument respectively output the set high level and low level, and the voltage is transmitted from the double-port three coaxial connecting line to the Hi end and Lo end of the PCB board, and is added to the D end and S end of the semiconductor power device MOS tube to be measured through the special test socket;

[0066] S6 instrument display MOS tube drain current refers to the level of the PCB board on the Guard line and the Hi end, to achieve the suppression of the measured power device outside the circuit part of the drain current, so that the instrument measured drain current is the drain current of MOS tube itself;

[0067] S7 drain current static test end refers to the MOS tube drain current static test has been completed, and through the method to improve the accuracy of the drain current test.

[0068] It should be noted that in this paper, such as the first and second (one, two) and other relational terms are only used to distinguish one entity or operation with another entity or operation, and does not necessarily require or imply any such actual relationship or order between the entity or operation. Moreover, the term "includes", "contains" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes the elements inherent in such process, method, article or equipment. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or equipment including the element.

[0069] The above shows and describes the basic principles and main features of the present application and the advantages of the present application. Those skilled in the art should understand that the present application is not limited to the above examples, and the above examples and descriptions in the specification are only to illustrate the principles of the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the claimed present application.

Claims

1. A method for suppressing leakage current during static testing of semiconductor power devices, characterized in that: The following steps are included: S1: PCB design is carried out in conjunction with the three coaxial interfaces. During the PCB design stage, the Guard line technology is used for optimization design. The Guard line surrounds all the high voltage lines, namely Hi line and SENSE Hi line, while avoiding contact with the low voltage lines, namely Lo line and SENSE Lo line, to achieve equipotential protection of the input signal lines, and at the same time suppress leakage current of the connection lines, test fixtures and auxiliary equipment. S2: The instrument is connected to the PCB through a double-ended three-coaxial interface. Connect the instrument's three-coaxial interface to the three-coaxial interface on the PCB to avoid poor contact that could introduce additional noise or error. S3: Insert the MOSFET under test into the socket. Insert the MOSFET into the dedicated test socket on the PCB board to ensure that the electrical connection between the MOSFET and the test system is correct, in order to prepare for the subsequent leakage current test. S4: Start the static leakage current test. The experimental environment required for the leakage current test has been set up. Start the static leakage current test of the MOSFET. S5: The Hi terminal of the instrument outputs a high level and the Lo terminal outputs a low level, which means that the Hi port and Lo port of the instrument output the set high level and low level respectively. The voltage is transmitted from the dual-port three-coaxial connection line to the Hi terminal and Lo terminal of the PCB board, and applied to the D terminal and S terminal of the tested semiconductor power device MOS transistor (3) through a dedicated test socket. S6: The instrument displays the leakage current of the MOSFET. Since the level of the Guard line on the PCB is the same as that of the Hi terminal, the leakage current generated by the circuit part outside the power device under test is suppressed, so that the leakage current measured by the instrument is the leakage current of the MOSFET itself. S7: The static leakage current test is complete. The static leakage current test of the MOSFET has been completed, and this method has improved the accuracy of the leakage current test.

2. The method for suppressing leakage current during static testing of semiconductor power devices according to claim 1, characterized in that: The PCB board is provided with Hi line (4), SENSE Hi line (5), Guard line (6), Lo line (7) and SENSE Lo line (8). The three coaxial interface (1) is used to provide high and low levels to the MOSFET (3) under test and to measure the leakage current of the MOSFET (3) under test. The three coaxial interface (1) includes a center signal line, a Guard line (6) and a GROUND line.

3. The method for suppressing leakage current during static testing of semiconductor power devices according to claim 2, characterized in that: The center signal line is located at the center of the three-coaxial interface (1). Its purpose is to provide high and low levels to the MOSFET (3) under test and to measure the leakage current of the MOSFET (3). The high level is transmitted through the Hi line (4) in the three-coaxial interface (1), and the low level is transmitted through the Lo line (7) in the three-coaxial interface (1), which enhances the stability and anti-interference ability of the signal and improves the accuracy of leakage current testing.

4. The method for suppressing leakage current during static testing of semiconductor power devices according to claim 2, characterized in that: The Guard line (6) is located in the middle layer of the three coaxial interface (1) and is wrapped around the Hi line (4) and Lo line (7) of the center signal line respectively. The potential of the Guard line (6) is equal to that of the Hi line (4). This potential matching ensures that the current on the Hi line (4) will not leak through the Guard line (6), thus achieving equipotential protection for the input signal line.

5. The method for suppressing leakage current during static testing of semiconductor power devices according to claim 2, characterized in that: The GROUND line is on the outermost layer of the three coaxial interface (1). The GROUND lines on the outermost layers of the Hi line (4) and Lo line (7) are connected together to provide a common reference potential for the center signal line in the three coaxial interface (1), ensuring the accuracy and stability of the signal.

6. The method for suppressing leakage current during static testing of a semiconductor power device according to claim 2, characterized in that: The leakage resistance and leakage capacitance (2) come from the connection wires, test fixtures and auxiliary equipment in the leakage current test loop from Hi line (4), Guard line (6) to Lo line (7), including leakage resistance R1 and leakage capacitance C1 between Hi line (4) and Guard line (6) and leakage resistance R2 and leakage capacitance C2 between Lo line (7) and Guard line (6).

7. The method for suppressing leakage current during static testing of a semiconductor power device according to claim 6, characterized in that: The leakage resistor R1 and leakage capacitor C1 do not have leakage current. Since the potential of Hi line (4) is equal to the potential of Guard line (6), the current of Hi line (4) will not leak to Guard line (6) through leakage resistor R1 and leakage capacitor C1.

8. The method for suppressing leakage current during static testing of a semiconductor power device according to claim 6, characterized in that: The leakage resistor R2 and leakage capacitor C2 have leakage current. Since the potential of the Guard line (6) is equal to the potential of the Hi line (4), the leakage current of the Guard line (6) will flow to the Lo line (7) through the leakage resistor R2 and leakage capacitor C2, and will not pass through the MOS transistor of the semiconductor power device under test. The leakage current from the Guard line (6) to the Lo line (7) is provided by the voltage of the Guard line (6). The voltage of the Guard line (6) is obtained by passing the Hi line (4) through a voltage follower. Since the voltage follower is a high impedance input, the current of the Guard line (6) has no effect on the current of the Hi line (4). Therefore, the leakage current flowing through the MOS transistor of the semiconductor power device under test is the current output by the instrument on the Hi line (4).

Images