Chip testing method and device

Abstract

The invention provides a chip testing method and device. The chip testing method is applied to a semiconductor finished product testing stage and comprises the steps that first identification information of a chip is read, and the first identification information is used for identifying whether the chip is subjected to a direct current test or not; determining test item information written in the erasure chip based on the first identification information and preset identification information; when the first identification information is consistent with the preset identification information, erasing the test item information; performing a direct current test on the chip; writing the preset identification information as the first identification information for the chip which passes the direct current test and of which the first identification information is inconsistent with the preset identification information; performing function test on the chip; and completely erasing the chips passing the function test, and obtaining the chips passing the semiconductor finished product test stage. The chip testing method and the chip testing device have the technical effects of identifying whether the chip is repeatedly tested or not, reducing the number of times of erasing testing, improving the chip testing efficiency, and improving the reliability of a testing result and the product yield.

Description

Technical Field

[0001] The present disclosure relates to the field of chip testing technology, and in particular to a chip testing method and device. Background Art

[0002] Semiconductor finished product testing (Final Test, FT) is the last test stage of the chip after packaging. Its main purpose is to ensure the performance and reliability of the chip in actual applications, to solve various uncertainties, to find out whether there are problems such as excessive power consumption and high temperature during the operation of the chip, and to extract data and feedback to customers to help customers find problems and increase the yield of finished chips. If a defective chip is detected in the FT test stage, the defective chip may have a false positive situation, that is, it is not a real fault. At this time, a repeated test (Retest, RT) is required. In the repeated test, in order to re-evaluate these suspected defective chips, the data in the main area of ​​the chip needs to be cleared first to prevent the chip from having been functionally tested and written information, which affects the test results. However, when the proportion of defective products is high, it may lead to additional repeated tests and increase the test cost, because each defective chip may need to go through the process of erasing and retesting. Therefore, the efficiency of the semiconductor finished product testing process deserves attention. Summary of the invention

[0003] The present disclosure provides a chip testing method and device to improve the testing efficiency in the semiconductor finished product testing process. In the first aspect, a chip testing method is applied to the semiconductor finished product testing stage, including: reading the first identification information of the chip, the first identification information is used to identify whether the chip has undergone a DC test; based on the first identification information and the preset identification information, determining to erase the test item information written in the chip; when the first identification information is consistent with the preset identification information, erasing the test item information; performing a DC test on the chip; for a chip that passes the DC test and whose first identification information is inconsistent with the preset identification information, writing the preset identification information as the first identification information; performing a functional test on the chip; erasing the chip that has passed the functional test, and obtaining a chip that has passed the semiconductor finished product testing stage.

[0004] The above chip testing method determines whether the chip is a repeated test chip by comparing and identifying the first identification information in the chip with the preset identification information, thereby deciding whether to perform an erase test on it, reducing the test time of the overall test process and improving test efficiency; and marking the chip that has undergone DC testing so that it needs to be erased as necessary when performing repeated testing, thereby improving the accuracy of chip testing and the product yield in the overall chip testing process.

[0005] Optionally, the storage area of ​​the chip includes: an administrator area and a customer area, the first identification information and the preset identification information are stored in the administrator area, and the test item information is stored in the customer area.

[0006] Optionally, erasing the chip that has passed the functional test includes erasing one or all of the customer area or the administrator area in the chip that has passed the functional test.

[0007] Optionally, the method further includes: determining that a chip that fails the DC test is a failed chip.

[0008] Optionally, the method further includes: determining that a chip that fails the functional test is a failed chip; or,

[0009] Repeat the test on the chip that fails the functional test, and read the first identification information of the chip again.

[0010] Optionally, when the number of repeated tests on the chip reaches a preset number, the chip is determined to be a failed chip.

[0011] Optionally, it also includes: performing an operating system test on the device of the test chip, and the operating system test includes: one or more of a startup speed test, a driver verification, or a basic system function test.

[0012] In a second aspect, a chip testing device is provided, comprising: a reading unit for reading first identification information of a chip, the first identification information being used to identify whether the chip has undergone a DC test; a first erasing unit for determining to erase test item information written in the chip based on the first identification information and preset identification information; erasing the test item information when the first identification information is consistent with the preset identification information; a DC testing unit for performing a DC test on the chip after erasing the test item information, and for performing a DC test on the chip whose first identification information is inconsistent with the preset identification information; a writing unit for writing the preset identification information as the first identification information for the chip that has passed the DC test and whose first identification information is inconsistent with the preset identification information; a functional testing unit for performing a functional test on the chip; and a second erasing unit for erasing the entire chip that has passed the functional test to obtain a chip that has passed the semiconductor finished product testing stage.

[0013] Optionally, it also includes: a failure confirmation unit, used to determine that a chip that fails the DC test is a failed chip, and used to determine that a chip that fails the functional test is a failed chip; or, repeatedly testing the chip that fails the functional test, and reading the first identification information of the chip again based on the reading unit.

[0014] In a third aspect, a chip testing device is provided, wherein the processor is used to couple to a memory, wherein the memory includes instructions, and when the instructions are called by the processor, the processor executes the chip testing method provided in the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following is a brief introduction to the drawings used in describing the embodiments of the present disclosure:

[0016] Figure 1 A schematic flow chart of a chip testing method provided in some embodiments of the present application is shown;

[0017] Figure 2 A schematic diagram of the structure of a chip testing device provided in some embodiments of the present application is shown;

[0018] Figure 3 A schematic structural diagram of another chip testing device provided in some embodiments of the present application is shown. DETAILED DESCRIPTION

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the specific implementation methods of the present disclosure will be described below with reference to the accompanying drawings. The accompanying drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other accompanying drawings or embodiments can be obtained based on these accompanying drawings or embodiments without paying creative work. The adjustments and improvements made without departing from the concept of the present disclosure all belong to the protection scope of the present disclosure.

[0020] In order to simplify the drawings, each of the drawings schematically shows only the parts related to the embodiments, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, only some structures or components are schematically depicted, and there may be more or fewer similar structures or components in reality.

[0021] Semiconductor finished product testing is the last test stage of the chip after packaging. Its main purpose is to ensure the performance and reliability of the chip in actual applications, to solve various uncertainties, to find out whether there are problems such as excessive power consumption and high temperature during the operation of the chip, and to extract data and feedback to customers to help customers find problems and improve the yield of finished chips. If a defective chip is detected in the FT test stage, the defective chip may have a false positive situation, that is, it is not a real fault, and repeated testing is required at this time. In the repeated test, in order to re-evaluate these suspected defective chips, the data in the main area of ​​the chip needs to be cleared first to prevent the chip from having been functionally tested and written information, affecting the test results. However, when the proportion of defective products is high, additional repeated tests may be required, increasing the test cost, because each defective chip may need to go through the process of erasing and retesting. Among them, the full chip erase operation time of the chip depends on the characteristics of the product and the manufacturing process. For some products, this may take up about 15% of the entire test process. For example, for a total test cycle of 6 seconds, the erase process may take about 0.88 seconds. At the same time, in the FT test process, a key step is to perform an erase test before starting each test item. This is because the FT test involves the verification of the chip storage content, and the role of the Erase test is to clear all previously recorded information inside the chip, so as to facilitate accurate comparative analysis of new test items. Since the Erase test is an independent operation, for example, it takes up 15% of the total test time, which means that it has a certain impact on the overall test progress. In particular, after the wafer test, the chip will be in a "full empty" state to enter the FT test process. However, an Erase test must be performed before each round of FT testing, which means that even if the chip is ready for a new test, this part of the time is actually invalid due to the pre-Erase step, which may cause a certain degree of test time waste. The following is a description with the accompanying drawings:

[0022] Figure 1 A schematic flow chart of a chip testing method provided in some embodiments of the present application is shown. The chip testing method is applied to the semiconductor finished product testing stage and includes at least the following steps:

[0023] S110: reading first identification information of the chip, where the first identification information is used to identify whether the chip has undergone a DC test;

[0024] S120: Determine the test item information written in the erase chip based on the first identification information and the preset identification information;

[0025] S130: When the first identification information is consistent with the preset identification information, erasing the test item information;

[0026] S140: perform DC test on the chip;

[0027] S150: For a chip that has passed the DC test and whose first identification information is inconsistent with the preset identification information, write the preset identification information as the first identification information;

[0028] S160: Perform functional test on the chip;

[0029] S170: Fully erase the chips that have passed the functional test, and obtain the chips that have passed the semiconductor finished product test stage.

[0030] In an embodiment of the present application, a first identification information may be stored in a specific storage area of ​​a chip, and the first identification information may be used to identify whether the chip has undergone a DC test. Since the test results or other parameter information of a previous test may be written into the chip during the DC test, these data may affect the reliability of the chip during the subsequent DC test or functional test. For example, the first identification information may be represented by a set of base numbers, such as using hexadecimal FF to represent the first identification information, or using a combination of characters such as numbers and letters, so as to inform the system whether the first identification information identifies the chip has undergone a DC test. For another example, the first identification information may be a piece of empty information, indicating that the storage location of the first identification information is empty, that is, no data information is written to the location, which can also indicate that the chip has not undergone a DC test. The determination of the first identification information can be set based on user usage habits or system requirements, such as the first identification information is set based on the specific model, production batch or safety management requirements of the chip, which is not specifically limited here. The preset identification information is based on marking that the chip has undergone a DC test after the chip undergoes a DC test. For example, the preset identification information is "85". When the first identification information is "FF", it indicates that the chip has not undergone a DC test and can be considered as a new chip. Therefore, there is no relevant data written in the previous test process in the chip, that is, the chip does not need to be erased; when the first identification information is also "85", it indicates that the chip has been previously DC tested and may be a chip that has failed subsequent tests and thus needs to be repeatedly tested. Therefore, the chip may contain relevant data and test results that have been written in the previous test process. In order to avoid the influence of these data, an erase test is required to ensure the reliability of the test results and improve the product yield. In the present application, the reading of the first identification information and the comparison of the first identification information with the preset identification information can effectively reduce the need for erasure testing of each chip, thereby saving test time and improving test efficiency. Furthermore, after the DC test, the present application writes the first identification information of the chip based on the preset identification information, and can mark the tested chip, so that in the process of repeated testing, the chip can be identified and determined to be erased. For chips without the mark, there is no need to erase them, thereby saving testing time. When performing functional testing on the chip, the functional test can include: logical function testing, that is, by inputting a preset data mode into the chip and checking the output result, verifying whether each logic unit in the chip correctly performs calculations and processing tasks according to design requirements.Timing test, that is, to detect whether the timing relationship between the signal paths inside the chip meets the design specifications, including parameters such as setup time and hold time; performance test, that is, to evaluate the working speed, response time and data throughput of the chip to confirm its performance under high-speed operation, etc., which are not specifically limited here. A chip that can pass the functional test can be determined to be a chip with complete functions and meets the design requirements. At this time, the chip can be fully erased to obtain a chip product. In this application, when the items that need to be tested fail to pass the above steps, the failed chip can be retested based on the above steps to improve the yield rate and eliminate contingency. Since there are many test processes involved in the functional test stage, it takes a long time for the entire test process, and it is impossible to predict which specific stage of the functional test stage the tested chip will fail to pass the test and cause the chip to fail. Therefore, the chip that passes the DC test can be written with preset identification information before the functional test to prevent the chip from failing to pass the functional test and repeating steps S110-S140 in the subsequent retest process. The test items are not erased because they do not contain preset identification information, which affects the test effect of the functional test.

[0031] In some embodiments, the storage area of ​​the chip includes: an administrator area and a customer area, the first identification information and the preset identification information are stored in the administrator area, and the test item information is stored in the customer area.

[0032] In some embodiments, fully erasing a chip that has passed a functional test includes: erasing one or all of a customer area or an administrator area in the chip that has passed a functional test.

[0033] The administrator area is an area where chip manufacturers and testers store information such as chip identity model information and key test project information during related design management and test management. This area can be selectively not erased during chip erase test, thereby retaining relevant information that can identify the chip identity. The customer area can store some data that can be temporarily stored, such as test parameters and test results. The data in this area will be erased during the erase test to provide users with storage space for subsequent chip-related software and hardware design.

[0034] In some embodiments, it also includes: determining that the chip that fails the DC test is a failed chip. DC testing mainly refers to the process of verifying whether the electrical performance of the chip meets the design requirements by measuring the DC electrical characteristic parameters of the chip (such as current, voltage, and resistance). For example, it may include: power supply voltage testing, that is, measuring the current change of the chip under different voltages to determine the minimum and maximum power supply voltage range of the chip; ground pin testing, that is, measuring the ground voltage of the chip to ensure that the ground voltage meets the design specifications to avoid chip failure or other problems; resistance testing, that is, measuring the resistance between different components in the chip, and ensuring that it is within the reasonable range of design requirements to avoid resistance problems that may cause chip failure or other problems.

[0035] In some embodiments, the method further includes: determining that a chip that fails the functional test is a failed chip; or,

[0036] Repeat the test on the chip that failed the functional test and read the first identification information of the chip again. In order to avoid misdetection and unnecessary defective rate, the chip that failed the functional test can be repeatedly tested and FT test can be continued to improve the yield rate.

[0037] In some embodiments, when the number of times the chip is repeatedly tested reaches a preset number, the chip is determined to be a failed chip. The process of repeated testing can be limited to avoid endless repetition, which would make the chip testing process complicated. The preset number of times can be set independently according to the test requirements and manufacturing process, for example, set to 2 times, and when two repeated tests are reached, the chip is stopped from being repeatedly tested.

[0038] In some embodiments, the system also includes: performing an operating system test on the device of the test chip, and the operating system test includes: one or more of a startup speed test, a driver verification, or a basic system function test. The purpose of the operating system test is to improve the reliability and efficiency of the test process, and to avoid problems such as unsatisfactory chip test results and low test efficiency due to problems with the test platform.

[0039] Figure 2A schematic structural diagram of a chip testing device provided in some embodiments of the present application is shown, and the chip testing device 200 includes: a reading unit 210, used to read the first identification information of the chip, the first identification information is used to identify whether the chip has undergone a DC test; a first erasing unit 220, used to determine the test item information written in the erase chip based on the first identification information and preset identification information; when the first identification information is consistent with the preset identification information, the test item information is erased; a DC test unit 230, used to perform a DC test on the chip after the test item information is erased, and to perform a DC test on the chip whose first identification information is inconsistent with the preset identification information; a writing unit 240, used to write the preset identification information as the first identification information for the chip that has passed the DC test and whose first identification information is inconsistent with the preset identification information; a functional testing unit 250, used to perform a functional test on the chip; a second erasing unit 260, used to fully erase the chip that has passed the functional test and obtain the chip that has passed the semiconductor finished product test stage.

[0040] In some embodiments, it also includes: a failure confirmation unit, used to determine that a chip that fails a DC test is a failed chip, and used to determine that a chip that fails a functional test is a failed chip; or, repeatedly testing the chip that fails the functional test, and reading the first identification information of the chip again based on the reading unit.

[0041] Figure 3 A schematic diagram of the structure of another chip testing device provided in some embodiments of the present application is shown. The chip testing device 300 includes a processor 310, which is coupled to a memory 320. The memory 320 includes instructions. When the instructions are called by the processor 310, the processor 310 executes the chip testing method provided in the above embodiments.

[0042] The present application does not limit the type of processor. A processor is a circuit with signal processing capability. For example, a processor includes a circuit with instruction reading and running capability, such as a CPU, a microprocessor, a graphics processing unit (GPU) or a digital signal processor (DSP), etc.; for another example, a processor can be implemented through the logical relationship of a hardware circuit, and the logical relationship of the hardware circuit is fixed or reconfigurable, for example, a processor includes a hardware circuit implemented by an ASIC or PLD, such as a hardware circuit implemented by a field programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the processor loading a configuration document to implement the hardware circuit configuration can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. For another example, a processor includes a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as one or more of a neural network processing unit (NPU), a tensor processing unit (TPU), or a deep learning processing unit (DPU).

[0043] It can be seen that each unit in the above chip testing device can be one or more processors (or processing circuits) configured to implement the above method, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms.

[0044] In addition, all or part of the units in the above chip testing device can be integrated together, or can be implemented independently. In one implementation, these units are integrated together and implemented in the form of a system on a chip (SOC). The SOC may include at least one processor for implementing any of the above chip testing methods or implementing the functions of the above chip testing devices.

[0045] The present application does not limit the type of memory. For example, the memory may include a read-only memory (ROM) or a random access memory (RAM). For example, it may include a non-volatile memory or a volatile memory. For example, it may include an on-chip storage resource or an off-chip storage resource. ROM includes, for example, a mask ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash ROM, etc.; RAM includes, for example, a static random-access memory (SRAM) or a dynamic random-access memory (DRAM), etc. On-chip storage resources refer to storage circuits integrated inside the chip, which are integrated with other circuits of the chip (such as processing circuits) to provide storage space for the chip, such as static random access memory (SRAM) resources on the chip, or space resources of configuration registers on the chip, etc. Off-chip storage resources refer to independent storage circuits or chips, such as off-chip double data rate synchronous dynamic RAM (DDR SDRAM, abbreviated as DDR), etc.

[0046] In this disclosure, unless otherwise expressly specified and limited, ordinal numbers, such as "first", "second", etc., are only used to distinguish and describe related objects, and cannot be understood as indicating or implying the relative importance or order between related objects. In addition, ordinal numbers do not represent the number of related objects.

[0047] "Plurality" includes two or more, and other quantifiers are similar.

[0048] The terms "or" and "and / or" in the present disclosure are used to describe the relationship between associated objects, which represents non-exclusive inclusion. For example, "A and / or B" and "A or B" may include: "A alone", "B alone", or "A and B", where "A" and "B" may include a single object or multiple objects. For another example, "A, B and / or C", "A, B or C" and "A, B and C" may include: "A alone", "B alone", "C alone", "A and B", "A and C", "B and C", or "A, B and C", where "A", "B" and "C" may include a single object or multiple objects. In addition, " / " in the present disclosure is used to represent the "or" relationship between the associated objects before and after. In the present disclosure, "at least one of A or B" and "one or more of A and B" have the same meaning as the above "A or B", and "one or more of A, B and C" and "at least one of A, B or C" have the same meaning as the above "A, B or C". "One or more of A, B and C" has the same meaning as the above "A, B or C".

[0049] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A chip testing method, characterized in that: Applied in the semiconductor finished product testing stage, including: Reading first identification information of a chip, where the first identification information is used to identify whether the chip has undergone a DC test; Determine to erase the test item information written in the chip based on the first identification information and the preset identification information; When the first identification information is consistent with the preset identification information, erasing the test item information; Performing the DC test on the chip; For a chip that passes the DC test and for which the first identification information is inconsistent with the preset identification information, writing the preset identification information as the first identification information; Performing functional testing on the chip; The chips that have passed the functional test are fully erased to obtain chips that have passed the semiconductor finished product test stage.

2. The chip testing method according to claim 1, characterized in that: The storage area of ​​the chip includes: an administrator area and a customer area, the first identification information and the preset identification information are stored in the administrator area, and the test item information is stored in the customer area.

3. The chip testing method according to claim 2, characterized in that: The whole chip erasing of the chip that has passed the functional test includes: erasing one or all of the customer area or the administrator area in the chip that has passed the functional test.

4. The chip testing method according to claim 1, characterized in that: Also includes: The chips that fail the DC test are determined to be failed chips.

5. The chip testing method according to claim 1, characterized in that: Also includes: Determining that a chip that fails the functional test is a failed chip; or, Repeat the test on the chip that fails the functional test, and read the first identification information of the chip again. 6 . The chip testing method according to claim 5 , when the number of times the chip performs the repeated test reaches a preset number, the chip is determined to be a failed chip.

7. The chip testing method according to any one of claims 1 to 6, characterized in that: Also includes: An operating system test is performed on a device for testing the chip, wherein the operating system test includes one or more of a startup speed test, a driver program verification, or a basic system function test.

8. A chip testing device, characterized in that: include: A reading unit, used for reading first identification information of a chip, where the first identification information is used for identifying whether the chip has undergone a DC test; A first erasing unit, configured to determine to erase the test item information written in the chip based on the first identification information and preset identification information; When the first identification information is consistent with the preset identification information, erasing the test item information; A DC test unit, used for performing a DC test on the chip after erasing the test item information, and for performing the DC test on the chip whose first identification information is inconsistent with the preset identification information; a writing unit, configured to write the preset identification information as the first identification information to a chip that has passed the DC test and for which the first identification information is inconsistent with the preset identification information; A functional testing unit, used for performing a functional test on the chip; The second erasing unit is used to fully erase the chips that have passed the functional test to obtain chips that have passed the semiconductor finished product test stage.

9. The chip testing device according to claim 7, characterized in that: Also includes: A failure confirmation unit, used to determine that a chip that fails the DC test is a failed chip, and used to determine that a chip that fails the functional test is a failed chip; Or, the chip that fails the functional test is repeatedly tested, and the first identification information of the chip is read again based on the reading unit.

10. A chip testing device, characterized in that: A processor is used to couple to a memory, wherein the memory includes instructions, and when the instructions are called by the processor, the processor executes the chip testing method according to any one of claims 1 to 7.

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