HTOL test system and method of dual-mode HDC chip

Abstract

The invention discloses an HTOL test system and method for a dual-mode HDC chip, and relates to the technical field of semiconductors, and the test system comprises a PC, a main control unit, a sampling unit, a communication unit, a power supply unit, a high-temperature box, and a test board. The test board is arranged in the high-temperature box and is used for connecting at least one tested chip; the sampling unit, the communication unit and the power supply unit are respectively connected with the test board; the communication unit and the power supply unit are also connected with the main control unit; and the main control unit is also connected with the PC. Various test indexes of the tested chip can be displayed in real time through the PC, and the test state of the tested chip can be comprehensively displayed; problems can be quickly positioned according to the test indexes displayed by the PC, and then corresponding adjustment is performed through the main control unit, so that the test flexibility is improved; according to the invention, the communication unit communicates with the tested chips, so that the signal interference between the tested chips is reduced, and the test accuracy is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a HTOL test system and method for a dual-mode HDC chip. Background Art

[0002] The current chip testing scheme is to place the soldered printed circuit board PCBA (Printed Circuit Board Assembly) with a chip socket in a high temperature box, and place the chip under test in the chip socket. During the HTOL (High-Temperature Operating Life) test, the chips under test communicate with each other, and the red and green LED flashes during the communication process to indicate whether the communication is normal. The test of the above existing scheme can only judge whether the chip under test is working normally by the flashing of the LED light, and cannot quantify the specific status indicators of the chip under test, so that the results lack accuracy and comparability; during the test, all the chips under test are communicating, and there is signal interference between each other, resulting in unstable communication of some chips under test, affecting the accuracy and reliability of the test; because the working status of the chip under test can only be judged by the indication of the LED light, there is a lack of clear indication indicators, so once a problem occurs during the test, it is difficult to accurately locate the cause of the problem, which makes the problem difficult to solve and prolongs the test cycle. Summary of the invention

[0003] The main purpose of the embodiments of the present application is to provide a HTOL test system and method for a dual-mode HDC chip to improve the monitoring comprehensiveness and accuracy of the chip test process.

[0004] To achieve the above-mentioned purpose, one aspect of an embodiment of the present application provides a HTOL test system for a dual-mode HDC chip, the test system comprising: a PC, a main control unit, a sampling unit, a communication unit, a power supply unit, a high temperature box and a test board; Wherein, the test board is arranged in the high temperature box, and the test board is used to connect at least one chip under test; The sampling unit, the communication unit and the power supply unit are respectively connected to the test board; The communication unit and the power supply unit are also connected to the main control unit; The main control unit is also connected to the PC; The power supply unit is used to supply power; The sampling unit is used to collect the voltage and current of the chip under test; The communication unit is used to communicate with the chip under test and collect the communication state of the chip under test, and collect the register state of the chip under test; The main control unit is used to adjust the sampling channel of the sampling unit and the communication channel of the communication unit, and determine a plurality of test indicators corresponding to the chip under test according to the voltage and current collected by the sampling unit, and the communication state and the register state of the chip under test; The PC is used to display various test indicators of the chip under test.

[0005] In some embodiments, the sampling unit includes an analog-to-digital converter and a plurality of the sampling channels, each of the sampling channels including a first channel and a second channel; Wherein, the first channel is used for sampling the voltage of the chip under test connected to the corresponding sampling channel; the second channel is used for sampling the current of the chip under test connected to the corresponding sampling channel; A first end of the first channel is connected to the analog-to-digital converter, and a second end of the first channel is connected to the power supply unit; The second channel includes an operational amplifier and a resistor; the output end of the operational amplifier is connected to the analog-to-digital converter, the first input end of the operational amplifier is connected to the power supply unit, the second input end of the operational amplifier is connected to the correspondingly connected chip under test, and the resistor is connected between the first input end and the second input end of the operational amplifier.

[0006] In some embodiments, the communication unit includes a high-speed dual-mode communication chip and a plurality of different types of the communication channels; A first end of each of the communication channels is connected to the high-speed dual-mode communication chip, and a second end of each of the communication channels is connected to the chip under test.

[0007] In some embodiments, the communication channel comprises a power line carrier communication channel; Wherein, the power line carrier communication channel includes a linear driver, a carrier filter, a coupling transformer and a first attenuator; The linear driver is respectively connected to the high-speed dual-mode communication chip and the first coil of the coupling transformer; The carrier filter is connected to the high-speed dual-mode communication chip and the first coil respectively; A first end of the second coil of the coupling transformer is connected to a first end of the first attenuator, a second end of the second coil is grounded, and a second end of the first attenuator is connected to the chip under test.

[0008] In some embodiments, the communication channel comprises a high-speed wireless communication channel; Wherein, the high-speed wireless communication channel includes a radio frequency power amplifier, a radio frequency filter, a radio frequency switch and a second attenuator; The first end of the RF power amplifier is connected to the high-speed dual-mode communication chip, and the second end of the RF power amplifier is connected to the first end of the RF switch; The first end of the radio frequency filter is connected to the high-speed dual-mode communication chip, and the second end of the radio frequency filter is connected to the second end of the radio frequency switch; The third end of the radio frequency switch is connected to the first end of the second attenuator, and the second end of the second attenuator is connected to the chip under test.

[0009] In some embodiments, the power supply unit includes a DC-to-DC converter, a low voltage drop linear regulator, and a fuse; Wherein, the low voltage difference linear regulator is connected to the DC to DC converter and the fuse respectively; The fuse is also connected to the corresponding chip under test.

[0010] In some embodiments, the main control unit and the communication unit are connected and communicated using a pluggable SPI interface; The main control unit and the sampling unit are connected and communicated with each other using a pluggable SPI interface.

[0011] To achieve the above object, another aspect of an embodiment of the present application provides a HTOL test method for a dual-mode HDC chip. The test method is applied to a HTOL test system for a dual-mode HDC chip as described in the present application. The test method includes the following steps: Collecting the voltage of the chip under test and then determining whether the voltage of the chip under test meets a first preset condition; If the voltage of the chip under test meets the first preset condition, the current of the chip under test is collected to determine whether the current of the chip under test meets the second preset condition; If the current of the chip under test meets the second preset condition, performing a communication test on the chip under test to obtain a communication state of the chip under test; If the communication state of the chip under test is normal, performing a register test on the chip under test to obtain a register state of the chip under test; If the register state of the chip under test is normal, the number of successful tests of the chip under test is determined to be increased by one; The next chip under test is selected, and the process returns to the step of collecting the voltage of the chip under test and then determining whether the voltage of the chip under test meets the first preset condition, until the test of all the chips under test is completed.

[0012] In some embodiments, the testing method further comprises the following steps: If the voltage of the chip under test does not meet the first preset condition, the current of the chip under test does not meet the second preset condition, the communication state of the chip under test is abnormal, or the register state of the chip under test is abnormal, then the number of failed tests of the chip under test is increased by one; If the number of consecutive test failures of the chip under test reaches a preset threshold, the chip under test will no longer be tested and a corresponding alarm message will be output.

[0013] In some embodiments, the testing method further comprises the following steps: Display various test indicators of each test of the chip under test.

[0014] The embodiments of the present application include at least the following beneficial effects: The test system of the present application includes a PC, a main control unit, a sampling unit, a communication unit, a power supply unit, a high temperature box and a test board; wherein the test board is arranged in the high temperature box, and the test board is used to connect at least one chip under test; the sampling unit, the communication unit and the power supply unit are respectively connected to the test board; the communication unit and the power supply unit are also connected to the main control unit; the main control unit is also connected to the PC. The present application can display various test indicators of the chip under test in real time through the PC, and can comprehensively display the test status of the chip under test; moreover, the present application can quickly locate the problem according to the test indicators displayed by the PC, and then make corresponding adjustments through the main control unit, thereby improving the test flexibility; the present application communicates with the chip under test through a communication unit, thereby reducing the signal interference between the chips under test and improving the accuracy of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A schematic diagram of the structure of a HTOL test system for a dual-mode HDC chip provided in an embodiment of the present application; Figure 2 A schematic diagram of a flow chart of a HTOL test method for a dual-mode HDC chip provided in an embodiment of the present application; Figure 3 An example flow chart of a HTOL test method for a dual-mode HDC chip provided in an embodiment of the present application; Figure 4 An optional structural diagram of a sampling unit provided in an embodiment of the present application; Figure 5An optional structural diagram of a power supply unit provided in an embodiment of the present application; Figure 6 An optional structural diagram of a communication unit provided in an embodiment of the present application.

[0017] Reference numerals: main control unit 1 , communication unit 2 , sampling unit 3 , power supply unit 4 , PC 5 , high temperature box 6 , test board 7 , chips under test 71 , 72 , 73 . DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0019] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0020] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0022] Before describing the embodiments of the present application in detail, some of the related technologies and terms involved in the embodiments of the present application are first described as follows: HDC, or High-speed dual-mode communication, is an innovative communication technology that combines power line carrier communication (HPLC) and high-speed wireless communication (HRF). It is suitable for a variety of application scenarios, especially providing fast and reliable support for smart grid data transmission.

[0023] At present, HDC chips and their communication modules have been widely used in the power grid's centralized metering system. The power grid requires that metering products can maintain stable performance during their life cycle, including the accuracy of data collection, the reliability of data transmission, and the stability of the system. This requires that metering products use high-quality materials and advanced processes during the design and manufacturing process to ensure that they can operate stably and for a long time in harsh power grid environments. This requires that the chip life test can truly reflect the life of the chip.

[0024] Mean Time To Failures (MTTF) is an indicator used to evaluate the life of a chip. The calculation formula is as follows: ; when -Confidence = 90%; - degrees of freedom 2r+2, r failure number 0; at this time -The chi-square distribution result is 4.61; The calculation formula of AF-Acceleration Factor is as follows: ; - Failure reaction activation energy 0.7; - Boltzmann constant 8.617e-5; - Junction temperature under normal use conditions +273K; - Junction temperature +273K under accelerated conditions.

[0025] in -The calculation formula for equipment hours is as follows: ; is the number of test samples, It's time for testing.

[0026] According to the above formula, if you need to calculate MTTF, you can use the results of HTOL test (high temperature operating life test) to evaluate the chip life according to the test temperature, test duration, number of test samples, and number of failed samples of the HTOL test. In order to ensure the accuracy of life evaluation, the HTOL test results must be stable and reliable.

[0027] HTOL (High-Temperature Operating Life) testing, also known as high-temperature operating life testing, is a test method used to evaluate the reliability and life of semiconductor chips under high-temperature working conditions. HTOL testing is usually performed in a high-temperature environment, and the test temperature is usually determined according to the chip specifications and application requirements, but is generally higher than the normal operating temperature of the chip. During the test, the chip will be applied with the maximum operating voltage to simulate the voltage stress under actual working conditions. The test time requirement is usually longer to ensure that the reliability and life of electronic devices in high-temperature environments can be fully evaluated.

[0028] The standard duration of HTOL testing is usually 1000 hours. This duration is determined based on the need to simulate the long-term working performance of electronic devices and accelerate aging testing. Through 1000 hours of testing, the performance changes and life of electronic devices in high temperature environments can be more accurately evaluated. Testing is usually carried out at some key time nodes to monitor the performance changes of electronic devices. These key time nodes usually include 168 hours, 500 hours and 1000 hours. At these time points, power consumption tests, functional tests, and performance tests will be carried out to evaluate the reliability and life of electronic devices.

[0029] At present, ATE machines are usually used to test the indicators of the chip to be tested. After the test is completed, it is heated to 125°C in a high-temperature box. During the test, the indicator light can generally only show whether the chip is working normally or abnormally. At critical time nodes and after the test is completed, the various indicators of the chip can only be tested by the ATE machine. This makes it impossible to guarantee real-time data monitoring of the test process. This application can not only solve the problem of test monitoring, but also reduce test costs and improve test efficiency.

[0030] In summary, the prior art has the following problems: 1. The test process cannot be monitored in real time, and can only display whether the tested chip is in normal state; 2. The test results cannot be quantified, the test is easily interfered with, and the test is unreliable; 3. The test cost is high and the test efficiency is low. ATE machine testing is required at critical time points, which will extend the overall test time.

[0031] In order to solve at least one problem of the prior art, the present application provides a HTOL test system and method for a dual-mode HDC chip. The test system of the present application includes a PC, a main control unit, a sampling unit, a communication unit, a power supply unit, a high temperature box and a test board; wherein the test board is arranged in the high temperature box, and the test board is used to connect at least one chip under test; the sampling unit, the communication unit and the power supply unit are respectively connected to the test board; the communication unit and the power supply unit are also connected to the main control unit; the main control unit is also connected to the PC. The present application can display various test indicators of the chip under test in real time through the PC, and can comprehensively display the test status of the chip under test; moreover, the present application can quickly locate the problem according to the test indicators displayed by the PC, and then make corresponding adjustments through the main control unit, thereby improving the test flexibility; the present application communicates with the chip under test through a communication unit, thereby reducing the signal interference between the chips under test and improving the accuracy of the test.

[0032] Reference Figure 1 , the embodiment of the present application provides a HTOL test system for a dual-mode HDC chip, the test system comprising: a PC, a main control unit, a sampling unit, a communication unit, a power supply unit, a high temperature box and a test board; Wherein, the test board is arranged in the high temperature box, and the test board is used to connect at least one chip under test; The sampling unit, the communication unit and the power supply unit are respectively connected to the test board; The communication unit and the power supply unit are also connected to the main control unit; The main control unit is also connected to the PC; The power supply unit is used to supply power; The sampling unit is used to collect the voltage and current of the chip under test; The communication unit is used to communicate with the chip under test and collect the communication state of the chip under test, and collect the register state of the chip under test; The main control unit is used to adjust the sampling channel of the sampling unit and the communication channel of the communication unit, and determine a plurality of test indicators corresponding to the chip under test according to the voltage and current collected by the sampling unit, and the communication state and the register state of the chip under test; The PC is used to display various test indicators of the chip under test.

[0033] As an optional implementation, the sampling unit includes an analog-to-digital converter and a plurality of sampling channels, each of the sampling channels includes a first channel and a second channel; Wherein, the first channel is used for sampling the voltage of the chip under test connected to the corresponding sampling channel; the second channel is used for sampling the current of the chip under test connected to the corresponding sampling channel; A first end of the first channel is connected to the analog-to-digital converter, and a second end of the first channel is connected to the power supply unit; The second channel includes an operational amplifier and a resistor; the output end of the operational amplifier is connected to the analog-to-digital converter, the first input end of the operational amplifier is connected to the power supply unit, the second input end of the operational amplifier is connected to the correspondingly connected chip under test, and the resistor is connected between the first input end and the second input end of the operational amplifier.

[0034] As an optional implementation, the communication unit includes a high-speed dual-mode communication chip and a plurality of different types of communication channels; A first end of each of the communication channels is connected to the high-speed dual-mode communication chip, and a second end of each of the communication channels is connected to the chip under test.

[0035] Furthermore, the communication channel comprises a power line carrier communication channel; Wherein, the power line carrier communication channel includes a linear driver, a carrier filter, a coupling transformer and a first attenuator; The linear driver is respectively connected to the high-speed dual-mode communication chip and the first coil of the coupling transformer; The carrier filter is connected to the high-speed dual-mode communication chip and the first coil respectively; A first end of the second coil of the coupling transformer is connected to a first end of the first attenuator, a second end of the second coil is grounded, and a second end of the first attenuator is connected to the chip under test.

[0036] In another further embodiment, the communication channel comprises a high-speed wireless communication channel; Wherein, the high-speed wireless communication channel includes a radio frequency power amplifier, a radio frequency filter, a radio frequency switch and a second attenuator; The first end of the RF power amplifier is connected to the high-speed dual-mode communication chip, and the second end of the RF power amplifier is connected to the first end of the RF switch; The first end of the radio frequency filter is connected to the high-speed dual-mode communication chip, and the second end of the radio frequency filter is connected to the second end of the radio frequency switch; The third end of the radio frequency switch is connected to the first end of the second attenuator, and the second end of the second attenuator is connected to the chip under test.

[0037] As an optional implementation, the power supply unit includes a DC-to-DC converter, a low voltage drop linear regulator and a fuse; Wherein, the low voltage difference linear regulator is connected to the DC to DC converter and the fuse respectively; The fuse is also connected to the corresponding chip under test.

[0038] As an optional implementation, the main control unit and the communication unit are connected and communicated using a pluggable SPI interface; The main control unit and the sampling unit are connected and communicated with each other using a pluggable SPI interface.

[0039] Reference Figure 2 The embodiment of the present application provides a HTOL test method for a dual-mode HDC chip, and the test method is applied to a HTOL test system for a dual-mode HDC chip as described in the present application. The test method may include but is not limited to S200 to S250, as follows: S200: collecting the voltage of the chip under test and determining whether the voltage of the chip under test meets a first preset condition; S210: If the voltage of the chip under test meets the first preset condition, the current of the chip under test is collected to determine whether the current of the chip under test meets the second preset condition; S220: If the current of the chip under test meets the second preset condition, perform a communication test on the chip under test to obtain a communication state of the chip under test; S230: If the communication state of the chip under test is normal, performing a register test on the chip under test to obtain a register state of the chip under test; S240: If the register state of the chip under test is normal, determine that the number of successful tests of the chip under test is increased by one; S250: Select the next chip under test, and return to the step of collecting the voltage of the chip under test and then determining whether the voltage of the chip under test meets the first preset condition, until the test of all the chips under test is completed.

[0040] Optionally, the embodiment of the present application may further include the following steps: If the voltage of the chip under test does not meet the first preset condition, the current of the chip under test does not meet the second preset condition, the communication state of the chip under test is abnormal, or the register state of the chip under test is abnormal, then the number of failed tests of the chip under test is determined to be increased by one; If the number of consecutive test failures of the chip under test reaches a preset threshold, the chip under test will no longer be tested and a corresponding alarm message will be output.

[0041] Optionally, the embodiment of the present application may further include the following steps: Display various test indicators of each test of the chip under test.

[0042] Next, the solution of the embodiment of the present application will be introduced and explained in detail with reference to specific application examples.

[0043] In view of the problems of poor stability, lack of quantitative indicators, unreliable test results and repeated testing in the existing HTOL test solutions, this embodiment provides a HTOL test solution for a dual-mode HDC chip to solve the above problems. Figure 1 In this test system, the power supply unit provides the required working power for the test board. The sampling unit is responsible for sampling the power supply voltage and current, and passing the data to the main control unit to evaluate whether the chip on the test board is in a normal working state. The communication unit communicates with the test board through HPLC and HRF, and counts the communication success rate with the chip under test on the test board to determine whether the communication is normal. At the same time, the key register status of the chip under test is also fed back to the communication unit through communication. The communication unit feeds back the communication status and register status to the main control unit, and the main control unit collects this information and feeds it back to the PC to display the status information of each chip.

[0044] Exemplarily, the test system of this embodiment can be designed as a whole in a modular manner. The main control unit communicates with the communication unit and the sampling unit using a standard SPI interface, and the hardware is implemented using a standard pluggable interface to facilitate subsequent updates and replacements.

[0045] An exemplary test process is as follows: Figure 3 As shown: First, the main control unit controls the sampling unit to sample the voltage of the Nth chip, and takes the average value of 10 samples to determine whether the voltage meets the expected standard (the first preset condition). If the voltage fails to meet the standard, the chip test is directly determined to have failed, and the next chip is tested. If the voltage meets the standard, the current test phase is entered. Similarly, the current is sampled 10 times and the average value is taken to determine whether the current meets the expectation (the second preset condition). If the current test also fails to meet the standard, the chip test is determined to have failed, and the next chip is tested. If the current test meets the standard, the communication test phase is entered. The main control unit controls the communication unit to perform HPLC and HRF communication attempts with the chip under test for 10 times respectively. If all fail, the chip test is determined to have failed and the test of the next chip is continued. If at least one communication is successful, the register status test is transferred to. If the register status is abnormal, the chip test is determined to have failed. Regardless of whether the register status is normal, the test process of the next chip will be immediately entered after the register test is completed.

[0046] When all test items (test items include voltage, current, communication status and register status) are completed and all test items are successful, the success count of the chip under test will increase by 1. If any test item fails, the failure count will increase by 1. For the same chip under test, if the number of consecutive failures reaches or exceeds the preset threshold (for example, 10 times), the subsequent tests will no longer test the chip, and the abnormal warning light on the main control unit will light up and the buzzer will sound to remind the tester that there is a test abnormality.

[0047] The test results of each chip under test will be transmitted to the PC in real time by the main control chip. The host software on the PC will use EXCEL tables to provide detailed statistics and display of the voltage value, current value, communication times and communication status of each chip under test, as well as the key register values ​​of the chip, in order to improve the comprehensiveness and traceability of the test data.

[0048] Next, some optional implementations of the test system of this embodiment are described.

[0049] Figure 4 This is an optional structural diagram of the sampling unit. The sampling unit uses an analog to digital converter ADC (Analog to Digital Converter) to sample the voltage and current of each chip under test. The voltage of the chip under test can be obtained directly by sampling the power supply voltage, and the use of ADC sampling can monitor in real time whether the power supply voltage of each chip under test is the maximum power supply voltage. The current of the chip under test converts the current signal into a voltage signal through the sampling resistor R (Resistor), and then amplifies it to an appropriate amplitude through the operational amplifier OPA (Operational Amplifier) ​​for ADC sampling, thereby ensuring the sampling accuracy. Each ADC is equipped with multiple sampling channels, and the main control unit selects and controls these channels to achieve the purpose of time-sharing sampling of the current and voltage of different chips under test. Multiple groups of the above structures together constitute a sampling unit for sampling all chips under test.

[0050] Figure 5This is an optional structural diagram of the power supply unit. The power supply unit converts the high voltage of the external power supply to a low DC voltage through a DC-to-DC converter DCDC (Direct Current-to-Direct Current Converter), and then powers the chip under test through a low dropout linear regulator LDO (Low Dropout Regulator). As a linear power supply, LDO can effectively isolate the switching noise generated by the switching power supply DCDC from interfering with the chip under test, ensuring that a reliable power supply is provided to the chip under test. A fuse is added between the chip under test and the LDO to ensure that when any abnormal problem occurs in any chip under test, the fuse can quickly present a disconnected or high-impedance state, thereby protecting other chips under test from being affected. Multiple groups of the above structures together constitute a power supply unit, providing a stable and reliable power supply for each chip under test.

[0051] Figure 6 This is an optional structural diagram of the communication unit. The communication unit is composed of a standard HDC chip and peripheral circuits, and is mainly used to realize HPLC communication and HRF communication with the chip under test. The peripheral circuit includes a linear driver LD (Line Driver) for power amplification of the HPLC carrier signal sent by the HDC, a carrier filter PLC_Filter for filtering invalid signals outside the HPLC signal band, and a coupling transformer for isolation coupling and conversion of HPLC differential signals into single-ended signals. The RF power amplifier PA (Power Amplifier) ​​is used to amplify the HRF RF signal sent by the HDC, the RF filter RF_Filter for filtering invalid signals outside the RF signal band, and the RF switch for switching the HRF signal. In addition, an attenuator is installed between the chip under test and the communication unit to attenuate the power of the communication signal to ensure that the communication performance can still be evaluated in the HTOL test environment, so that the HTOL test results can more comprehensively reflect the performance of the chip. At the same time, the internal key registers of the chip under test are transmitted to the communication unit through the HPLC and HRF channels, so that the system can monitor the status of the chip under test in real time, and then reflect the change trend of the chip. The communication unit of this embodiment only needs one HDC chip to perform communication tests on different chips under test, thereby effectively preventing crosstalk between signals and ensuring the reliability of the test results.

[0052] The main control unit is mainly used for system coordination and control as well as data processing and analysis. It includes selecting the sampling ADC and the corresponding channel, processing and analyzing the ADC sampling data, controlling the communication between the communication unit and the chip under test, and statistical processing of the communication results. After the main control unit completes data collection, it feeds back the relevant information to the PC and presents it to the tester.

[0053] In summary, this embodiment can include the following beneficial effects: 1. Improve test efficiency: By real-time monitoring and recording of various test indicators of the chip under test during the test process, real-time acquisition and processing of test data is achieved, thereby improving test efficiency.

[0054] 2. Reduce test costs: The power supply unit, sampling unit and communication unit can be reused in different projects, and there is no need to remove the chip from the socket and put it into the ATE machine for testing during the test process, which reduces the test cost.

[0055] 3. Improve test accuracy: Through comprehensive data analysis and evaluation, accurate test reports and data analysis results are provided, providing a reliable basis for the research and development and production of HDC communication chips.

[0056] 4. Enhanced test flexibility: The test system and test method of this embodiment can be adaptively designed according to different packaging forms, pin numbers and power consumption of communication chips, thereby enhancing the flexibility and versatility of the test.

[0057] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0058] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0059] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place, or they may be distributed over multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0060] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0061] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0062] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A HTOL test system for a dual-mode HDC chip, characterized in that: The test system includes: a PC, a main control unit, a sampling unit, a communication unit, a power supply unit, a high temperature box and a test board; Wherein, the test board is arranged in the high temperature box, and the test board is used to connect at least one chip under test; The sampling unit, the communication unit and the power supply unit are respectively connected to the test board; The communication unit and the power supply unit are also connected to the main control unit; The main control unit is also connected to the PC; The power supply unit is used to supply power; The sampling unit is used to collect the voltage and current of the chip under test; The communication unit is used to communicate with the chip under test and collect the communication state of the chip under test, and collect the register state of the chip under test; The main control unit is used to adjust the sampling channel of the sampling unit and the communication channel of the communication unit, and determine a plurality of test indicators corresponding to the chip under test according to the voltage and current collected by the sampling unit, and the communication state and the register state of the chip under test; The PC is used to display various test indicators of the chip under test.

2. The HTOL test system of a dual-mode HDC chip according to claim 1, characterized in that: The sampling unit includes an analog-to-digital converter and a plurality of sampling channels, each of the sampling channels includes a first channel and a second channel; Wherein, the first channel is used for sampling the voltage of the chip under test connected to the corresponding sampling channel; the second channel is used for sampling the current of the chip under test connected to the corresponding sampling channel; A first end of the first channel is connected to the analog-to-digital converter, and a second end of the first channel is connected to the power supply unit; The second channel includes an operational amplifier and a resistor; the output end of the operational amplifier is connected to the analog-to-digital converter, the first input end of the operational amplifier is connected to the power supply unit, the second input end of the operational amplifier is connected to the correspondingly connected chip under test, and the resistor is connected between the first input end and the second input end of the operational amplifier.

3. The HTOL test system of a dual-mode HDC chip according to claim 1, characterized in that: The communication unit includes a high-speed dual-mode communication chip and a plurality of different types of communication channels; A first end of each of the communication channels is connected to the high-speed dual-mode communication chip, and a second end of each of the communication channels is connected to the chip under test.

4. The HTOL test system of a dual-mode HDC chip according to claim 3, characterized in that: The communication channel comprises a power line carrier communication channel; Wherein, the power line carrier communication channel includes a linear driver, a carrier filter, a coupling transformer and a first attenuator; The linear driver is respectively connected to the high-speed dual-mode communication chip and the first coil of the coupling transformer; The carrier filter is connected to the high-speed dual-mode communication chip and the first coil respectively; A first end of the second coil of the coupling transformer is connected to a first end of the first attenuator, a second end of the second coil is grounded, and a second end of the first attenuator is connected to the chip under test.

5. The HTOL test system of a dual-mode HDC chip according to claim 3, characterized in that: The communication channel comprises a high-speed wireless communication channel; Wherein, the high-speed wireless communication channel includes a radio frequency power amplifier, a radio frequency filter, a radio frequency switch and a second attenuator; The first end of the RF power amplifier is connected to the high-speed dual-mode communication chip, and the second end of the RF power amplifier is connected to the first end of the RF switch; The first end of the radio frequency filter is connected to the high-speed dual-mode communication chip, and the second end of the radio frequency filter is connected to the second end of the radio frequency switch; The third end of the radio frequency switch is connected to the first end of the second attenuator, and the second end of the second attenuator is connected to the chip under test.

6. The HTOL test system of a dual-mode HDC chip according to claim 1, characterized in that: The power supply unit includes a DC-to-DC converter, a low voltage drop linear regulator and a fuse; Wherein, the low voltage difference linear regulator is connected to the DC to DC converter and the fuse respectively; The fuse is also connected to the corresponding chip under test.

7. A HTOL test system for a dual-mode HDC chip according to any one of claims 1 to 6, characterized in that: The main control unit and the communication unit are connected and communicated using a pluggable SPI interface; The main control unit and the sampling unit are connected and communicated with each other using a pluggable SPI interface.

8. A HTOL test method for a dual-mode HDC chip, characterized in that: The test method is applied to a HTOL test system for a dual-mode HDC chip according to any one of claims 1 to 7, and the test method comprises the following steps: Collecting the voltage of the chip under test and then determining whether the voltage of the chip under test meets a first preset condition; If the voltage of the chip under test meets the first preset condition, the current of the chip under test is collected to determine whether the current of the chip under test meets the second preset condition; If the current of the chip under test meets the second preset condition, performing a communication test on the chip under test to obtain a communication state of the chip under test; If the communication state of the chip under test is normal, performing a register test on the chip under test to obtain a register state of the chip under test; If the register state of the chip under test is normal, the number of successful tests of the chip under test is determined to be increased by one; The next chip under test is selected, and the process returns to the step of collecting the voltage of the chip under test and then determining whether the voltage of the chip under test meets the first preset condition, until the test of all the chips under test is completed.

9. The HTOL test method of a dual-mode HDC chip according to claim 8, characterized in that: The test method further comprises the following steps: If the voltage of the chip under test does not meet the first preset condition, the current of the chip under test does not meet the second preset condition, the communication state of the chip under test is abnormal, or the register state of the chip under test is abnormal, then the number of failed tests of the chip under test is determined to be increased by one; If the number of consecutive test failures of the chip under test reaches a preset threshold, the chip under test will no longer be tested and a corresponding alarm message will be output.

10. The HTOL test method of a dual-mode HDC chip according to any one of claims 8 to 9, characterized in that: The test method further comprises the following steps: Display various test indicators of each test of the chip under test.

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