Wafer test system based on high and low frequency multiplexing probe and test method thereof

Abstract

The invention discloses a wafer test system based on a high and low frequency multiplexing probe and a test method thereof, and relates to the technical field of semiconductors, the wafer test system based on the high and low frequency multiplexing probe comprises a probe card, a test machine and a high-speed switching matrix; the probe card is provided with a signal transmission layer and a single row of probes. The high-frequency test and the low-frequency test are integrated, and interference-free switching between the high-frequency test and the low-frequency test of the bare core is realized by matching a row of probes arranged on the probe card with the high-speed switching matrix. The probe card is only provided with one row of probes, so that the cost of the probes is reduced, only one-time alignment operation is needed in the testing process, the testing technological process is simplified, and the testing efficiency is improved. And meanwhile, the connection of the probe and the bare core is also completed at one time, so that the requirements on the precision and complexity of a mechanical arm are remarkably reduced, the operation difficulty and cost are further reduced, the damage to a bonding pad of the bare core is also effectively reduced by one-time contact, and the packaging yield is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a wafer testing system and a testing method thereof based on high- and low-frequency multiplexed probes. Background Art

[0002] The process conversion of DRAM (Dynamic Random Access Memory) technology is getting faster and faster, from 30nm, 25nm, 20nm, 1αnm and even smaller processes. There will be certain problems in each process conversion, resulting in the production yield of wafers decreasing with the improvement of process technology. If these products are directly packaged without testing, the bare cores (die for short) of defective products will also be packaged into chip particles. If the yield of the wafer is so low that the profit cannot make up for the packaging cost, losses will occur.

[0003] Therefore, it is a must to test each die before packaging. Die testing is divided into two parts from the functional aspect: DC (direct current characteristic) testing and AC (alternating current characteristic) testing. Among them, DC testing is generally low frequency, and AC testing is high frequency. To implement these two parts of the Die functional testing, it is not possible to achieve it through one set of module circuits, and two sets of module circuits must be used.

[0004] The traditional approach is to use a DC test module circuit to connect one probe card, and an AC test module circuit to connect another probe card. A robotic arm is used to fix the two probe cards at the same time, and the two probe cards are connected to the tested bare core by rotation or translation for corresponding testing. This approach has two very obvious disadvantages. First, the accuracy requirements of the robotic arm are extremely high. The motion error must be between 1 and 5um. Second, two probe cards are required, and the cost of the probe cards is very high.

[0005] Another approach is to design two rows of probes on a probe card, and the robotic arm moves the probe card board to switch between DC testing and AC testing. This approach brings four defects. First, the accuracy requirements of the robotic arm are extremely high. The motion error must be between 1 and 5um. Second, the double-row probe design of the probe card is complex, and the cost increases exponentially; third, the die needs to be aligned twice, which increases the complexity of the process; fourth, the bare core needs to be contacted and crimped twice, which damages the bonding pad of the die and affects the subsequent packaging yield. Summary of the invention

[0006] The main purpose of the present application is to provide a wafer testing system and a testing method thereof based on high- and low-frequency multiplexed probes, aiming to solve the problem that traditional wafer testing devices cannot reduce damage to bare cores while improving accuracy.

[0007] To achieve the above objectives, the present application proposes a wafer testing system based on high- and low-frequency multiplexed probes, comprising: A probe card, wherein a signal transmission layer and a single-row probe are provided on the probe card; one end of the single-row probe is fixed on the probe card and connected to the signal transmission layer, and the other end of the single-row probe is used to realize electrical connection between the bare core to be tested and the signal transmission layer; A test machine having a high-frequency output terminal and a low-frequency output terminal, the test machine being used to generate a high-frequency test signal and output it through the high-frequency output terminal, and to generate a low-frequency test signal and output it through the low-frequency output terminal; A high-speed switching matrix, wherein a first input end of the high-speed switching matrix is ​​connected to the low-frequency output end, a second input end of the high-speed switching matrix is ​​connected to the high-frequency output end, and an output end of the high-speed switching matrix is ​​connected to a single-row probe through the signal transmission layer; the high-speed switching matrix is ​​used to control the high-frequency output end to be electrically connected to the single-row probe according to the received switching instruction so as to output the high-frequency test signal to the bare core to be tested, or control the low-frequency output end to be electrically connected to the single-row probe so as to output the low-frequency test signal to the bare core to be tested; The test machine is also used to receive the test results fed back by the core to be tested in response to the high-frequency test signal and the low-frequency test signal, and upload them to the host computer.

[0008] In one embodiment, the high-speed switching matrix includes: A plurality of high-speed electronic relays, wherein a first input end of each of the high-speed electronic relays is connected to a high-frequency output end of the test machine, a second input end of each of the high-speed electronic relays is connected to a low-frequency output end of the test machine, and an output end of each of the high-speed electronic relays is connected to a single-row probe through the signal transmission layer; The relay control circuit has an input end connected to an external signal and the test machine, and an output end connected to a control end of each high-speed electronic relay.

[0009] In one embodiment, the high-speed switching matrix further includes: An external signal input circuit, the input end of which is electrically connected to the external signal, and the output end of which is electrically connected to the input end of the relay control circuit; The test machine signal input circuit has an input end connected to the control signal output end of the test machine, and an output end electrically connected to the input end of the relay control circuit.

[0010] In one embodiment, it further includes: A mechanical arm, comprising a clamping portion, wherein the clamping portion is used to fix the probe card, and the mechanical arm drives the probe card to move so that the single row of probes contacts the bare core to be tested; Probe station, used to carry wafers.

[0011] In one embodiment, the wafer testing system has a high frequency testing mode and a low frequency testing mode; In the high-frequency test mode, the high-speed switching matrix controls the high-frequency output terminal to be electrically connected to the single-row probe according to the received switching instruction, so that the high-frequency test signal generated by the tester is output to the bare core to be tested; In the low-frequency test mode, the high-speed switching matrix controls the low-frequency output terminal to be electrically connected to the single-row probe according to the received switching instruction, so that the low-frequency test signal generated by the tester is output to the bare core to be tested.

[0012] In one embodiment, the testing machine comprises: A main control circuit connected to the control end of the high-speed switching matrix; A high-frequency test circuit is connected to the main control circuit, and is used to generate a high-frequency test signal and output it to the bare core to be tested for high-frequency testing, and obtain a high-frequency test result fed back by the bare core to be tested in response to the high-frequency test signal and output it to the main control circuit; A low-frequency test circuit is connected to the main control circuit, and is used to generate a low-frequency test signal and output it to the bare core to be tested for low-frequency testing, and obtain a low-frequency test result fed back by the bare core to be tested in response to the low-frequency test signal and output it to the main control circuit; Wherein, the main control circuit is also used to control the high-frequency test circuit to work in the high-frequency test mode to obtain a high-frequency test result; The main control circuit is also used to control the low-frequency test circuit to work in the low-frequency test mode to obtain a low-frequency test result.

[0013] In one embodiment, the testing machine further comprises: A communication circuit connected to the communication interface of the main control circuit and used for communication between the test machine and the host computer; The main control circuit is used to receive and output control signals to the high-speed switching matrix according to the instructions of the host computer, so as to control the high-speed switching matrix to connect the high-frequency output terminal / low-frequency output terminal with the single-row probe, and to obtain test results and upload them to the host computer.

[0014] In addition, to achieve the above purpose, the present application also proposes a wafer testing method, which is applied to the wafer testing system based on high- and low-frequency multiplexed probes as described above, comprising: placing the wafer in a wafer test system; Controlling the movement of the mechanical arm to drive the single row of probes on the probe card to contact the bare core to be tested; The wafer testing system enters a low-frequency testing mode according to the instruction of the host computer, and controls the high-speed switching matrix to connect the low-frequency output terminal with the single-row probe; The wafer testing system enters a high-frequency testing mode according to the instruction of the host computer, and controls the high-speed switching matrix to connect the high-frequency output terminal with the single-row probe.

[0015] In one embodiment of the wafer testing method, the wafer testing system enters a low-frequency testing mode according to an instruction of a host computer, and the specific steps of controlling the high-speed switching matrix to connect the low-frequency output terminal with the single-row probe further include: The test machine generates a low-frequency test signal according to the instruction of the host computer to perform a low-frequency test on the bare core to be tested, so that the bare core to be tested responds to the low-frequency test signal and generates a corresponding low-frequency test result; The test machine obtains the low-frequency test result fed back by the bare core to be tested and uploads it to the host computer to test the quality of the bare core to be tested under the low-frequency signal; And / or, the wafer testing system enters the high-frequency testing mode according to the instruction of the host computer, and the specific steps of controlling the high-speed switching matrix to connect the high-frequency output terminal with the single-row probe also include: The tester generates a high-frequency test signal to perform a high-frequency test on the bare core to be tested, so that the bare core to be tested responds to the high-frequency test signal and generates a corresponding high-frequency test result; The test machine obtains the high-frequency test result fed back by the bare core to be tested and uploads it to the host computer to test the quality of the bare core to be tested under the high-frequency signal.

[0016] In one embodiment of the wafer testing method, the wafer testing system enters a high-frequency testing mode according to an instruction of a host computer, and the specific steps of controlling the high-speed switching matrix to connect the high-frequency output terminal with the single-row probe further include: Upon completion of the low-frequency test mode, the wafer test system enters the high-frequency test mode according to the instruction of the host computer.

[0017] One or more technical solutions proposed in this application have at least the following technical effects: The present application proposes a wafer testing system and a testing method based on high- and low-frequency multiplexed probes, which integrate the two major functions of high-frequency testing and low-frequency testing, and realize interference-free switching between high-frequency and low-frequency testing of bare cores through a row of probes equipped on the probe card in conjunction with a high-speed switching matrix. Since the probe card is only equipped with one row of probes, the cost of the probes is reduced, the difficulty and complexity of production are reduced, and only one alignment operation is required during the test process, which simplifies the test process and improves test efficiency. At the same time, the connection between the probe and the bare core only needs to be completed once, which significantly reduces the accuracy and complexity requirements of the robotic arm, further reducing the difficulty and cost of operation. One-time contact also effectively reduces damage to the bonding pads of the bare core and improves the packaging yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 This is a structural diagram of a wafer testing system based on high- and low-frequency multiplexed probes for this application; Figure 2 This is a circuit framework structure diagram of a wafer testing system based on high- and low-frequency multiplexed probes in this application; Figure 3 The present invention is a flowchart of a wafer testing method.

[0021] Description of the accompanying drawings: probe card 01, single-row probe 11, tester 02, low-frequency test circuit 21, high-frequency test circuit 22, main control circuit 23, high-speed switching matrix 03.

[0022] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0023] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0024] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0025] To achieve the above purpose, Figure 1 As shown, the present application proposes a wafer testing system based on high- and low-frequency multiplexed probes, comprising: A probe card 01, wherein a signal transmission layer and a single-row probe 11 are provided on the probe card 01; one end of the single-row probe 11 is fixed on the probe card 01 and connected to the signal transmission layer, and the other end of the single-row probe 11 is used to realize electrical connection between the bare core to be tested and the signal transmission layer; The test machine 02 has a high-frequency output terminal and a low-frequency output terminal, and is used to generate a high-frequency test signal and output it through the high-frequency output terminal, and to generate a low-frequency test signal and output it through the low-frequency output terminal; A high-speed switching matrix 03, wherein a first input end of the high-speed switching matrix 03 is connected to the low-frequency output end, a second input end of the high-speed switching matrix 03 is connected to the high-frequency output end, and an output end of the high-speed switching matrix 03 is connected to a single-row probe 11 through the signal transmission layer; the high-speed switching matrix 03 is used to control the high-frequency output end to be electrically connected to the single-row probe 11 according to the received switching instruction, so as to output the high-frequency test signal to the bare core to be tested, or control the low-frequency output end to be electrically connected to the single-row probe 11, so as to output the low-frequency test signal to the bare core to be tested; The test machine 02 is further used to receive the test results fed back by the core to be tested in response to the high-frequency test signal and the low-frequency test signal, and upload the results to the host computer.

[0026] Specifically, in the semiconductor field, a wafer is a silicon chip used to make silicon semiconductor integrated circuits. Because of its round shape, it is called a wafer; various circuit element structures can be processed on the silicon wafer to become IC products with specific electrical functions. On the wafer, a large number of integrated circuit structures will be formed after a series of semiconductor processes (such as photolithography, doping, etching, etc.). Each independent unit in these integrated circuit structures is called a die. The bare die is obtained by cutting the wafer into multiple small pieces. Each bare die represents a complete electronic component, usually with complete functions, but it has not been packaged at this stage. After the bare die is cut and tested, it will be packaged into a complete chip. The package not only provides physical protection for the bare die to prevent it from being damaged during use, but also connects the chip to the external circuit through pins, pads, etc. The chip is the final product for users and the market. The chip after packaging has actual electrical functions and can be used as part of the integrated circuit (IC) in various electronic devices.

[0027] The packaging step includes die bonding. In order to achieve a stable and reliable mechanical and electrical connection between the bare die and the carrier (such as substrate, lead frame, package substrate, etc.), the bare die must first be firmly "glued" to the appropriate position. If it is not mounted properly, not only will the subsequent coil wire bonding (Wire Bonding) be offset or even unable to connect, but the heat dissipation and reliability of the device will also be greatly reduced. The connection of the bare die requires a bonding pad, which is the exposed metallized contact point on the surface of the bare die, serving as an electrical connection bridge between the internal circuit of the chip and the external package pins.

[0028] As semiconductor manufacturing enters the nanoscale era, wafer testing technology faces unprecedented physical scale challenges. The miniaturization of bonding pads not only changes the contact mechanism of the test probe, but also reconstructs the signal transmission model of the entire test system. When the pad size is reduced to the micron level, the contact mechanics between the probe and the pad undergoes essential changes - the elastic deformation assumption in the traditional macroscopic contact theory gradually fails, and the surface roughness and material grain boundary effects at the microscale begin to dominate the contact impedance characteristics. The damage mechanism of the test interface is another irreversible technical obstacle. Each time the probe contacts, a nanoscale indentation will be formed on the surface of the pad. These microscopic defects will affect the packaging yield in the subsequent packaging bonding process.

[0029] It is a must to test each Die before packaging. Die testing is divided into two parts from the functional aspect: low-frequency (low-frequency) testing and high-frequency (high-frequency) testing. To implement the functional testing of these two parts of Die, it is not possible to achieve it through a set of module circuits, and two sets of module circuits must be used. The traditional approach is to use a low-frequency test module circuit to connect a probe card 01, and a high-frequency test module circuit to connect another probe card 01. The two probe cards 01 are fixed at the same time by a mechanical arm, and the two probe cards 01 are connected to the tested bare core by rotation or translation for corresponding testing. This approach has two very obvious disadvantages. First, the accuracy requirements of the mechanical arm are extremely high. The motion error must be between 1 and 5um. Second, two probe cards 01 are required, and the cost of probe cards 01 is very high.

[0030] Another approach is to design two rows of probes on a probe card 01, and the robotic arm moves the probe card 01 to switch between low-frequency testing and high-frequency testing. This approach brings four defects. First, the accuracy requirements for the robotic arm are extremely high. The motion error must be between 1 and 5um. Second, the double-row probe design of the probe card 01 is complex, and the cost increases exponentially; third, the die needs to be aligned twice, which increases the complexity of the process; fourth, the bare core needs to be contacted and crimped twice, which damages the bonding pad of the die and affects the subsequent packaging yield.

[0031] The main purpose of the present application is to provide a wafer testing system and a testing method based on high-low frequency multiplexed probes, aiming to solve the problem that traditional wafer testing devices cannot reduce damage to bare cores while improving accuracy. The wafer testing system based on high-low frequency multiplexed probes includes a probe card 01, a testing machine 02 and a high-speed switching matrix 03.

[0032] The test machine 02 has a high-frequency output terminal and a low-frequency output terminal. The test machine 02 is used to generate a high-frequency test signal and output it through the high-frequency output terminal, and to generate a low-frequency test signal and output it through the low-frequency output terminal. In the present application, the test is integrated with two systems: a high-frequency test and a low-frequency test. The low-frequency test is basically a low-frequency test below 10Mbps. The purpose of the low-frequency test is to check the DC electrical characteristics of the bare core, such as detecting whether the signal pin of the chip has an open circuit or a short circuit problem, verifying whether the power pin of the chip has a short circuit problem, or measuring the DC current and voltage parameters of the chip to ensure that they meet the design specifications. These tests help identify electrical faults of the chip under static or low-frequency conditions, such as pin connection problems, power short circuits, and DC parameter deviations from design specifications.

[0033] High-frequency testing is basically a 100Mbps high-frequency test, which mainly focuses on the AC signal quality and timing parameters of the chip. For example, Function testing (read and write testing) writes and reads programs on the bare core to be tested, and compares whether the read and write programs are consistent. Timing testing (timing testing) writes and reads programs on the bare core to be tested, and measures the parameters of the bare core to be tested under different operating conditions. AC testing helps to discover potential problems of the chip at high frequency or actual operating speed, such as delay failures, signal distortion, etc.

[0034] A high-speed switching matrix 03, wherein a first input terminal of the high-speed switching matrix 03 is connected to the low-frequency output terminal, a second input terminal of the high-speed switching matrix 03 is connected to the high-frequency output terminal, and an output terminal of the high-speed switching matrix 03 is connected to a single-row probe 11 through the signal transmission layer; the high-speed switching matrix 03 is used to control the high-frequency output terminal to be electrically connected to the single-row probe 11 according to the received switching instruction so as to output the high-frequency test signal to the bare core to be tested, or to control the low-frequency output terminal to be electrically connected to the single-row probe 11 so as to output the low-frequency test signal to the bare core to be tested.

[0035] Since low-frequency testing and high-frequency testing have significant differences in signal characteristics, test requirements, and potential interference sources. In the same test device, the low-frequency part will affect the high-frequency test of the high frequency, often resulting in failure of the high-frequency test. The present invention sets up a high-speed switching matrix 03, which separates the low-frequency test and the high-frequency test by conducting the connection between the probe card 01 and the high- and low-frequency output terminals or the connection between the low-frequency output terminals, so that the two do not interfere with each other. More specifically, the high-speed switching matrix 03 of the present application adopts a high-speed electronic relay array, which is an electronic control device composed of multiple high-speed electronic relays. It controls the on-off of the circuit through electromagnetic induction, has the characteristics of automatic switching, fast speed, and low cost, and is suitable for switching between high- and low-frequency tests of the present application.

[0036] The probe card 01 is provided with a signal transmission layer and a single-row probe 11; one end of the single-row probe 11 is fixed on the probe card 01 and connected to the signal transmission layer, and the other end of the single-row probe 11 is used to realize the electrical connection between the bare core to be tested and the signal transmission layer. The defect of the above-mentioned traditional wafer testing device is that no matter using a single card with two needles or a double card with two needles, a double-row probe is required, which means that the bare core to be tested needs to be contacted twice. This repetitive mechanical contact not only increases the manufacturing cost and assembly complexity of the probe card 01 itself, but also causes cumulative physical damage to the surface of the bare core.

[0037] Therefore, the probe card 01 of the present application adopts a single-row probe 11, that is, a single card with a single needle. A single probe can simultaneously carry out high-frequency and low-frequency signal transmission tasks, and cooperate with the high-speed switching matrix 03, so that the probe card 01 can complete all test tasks in a single alignment, without the need to switch between different test modes through a physically separated probe array. In terms of test process optimization, the single-contact mechanism completely eliminates the need for secondary alignment operations in traditional solutions. The robotic arm only needs to perform one high-precision positioning action to achieve reliable contact between the probe array and the bare core pad, which not only shortens the test cycle of a single chip, but also greatly reduces the performance requirements for the mechanical motion system. The sub-micron level repeatability positioning accuracy required by traditional double-row probes is relaxed to the micron level, which simplifies the mechanical structure of the test equipment, significantly reduces the complexity of the motion control algorithm, and reduces the equipment maintenance cost simultaneously. The physical protection effect of a single contact on the bare core bonding pad is particularly prominent. During two independent crimping processes of traditional double-row probes, the pad surface will experience a cycle of contact stress loading-unloading-reloading. This alternating stress can easily lead to the expansion of microcracks in the metal layer or peeling of the dielectric layer interface. The single-row probe 11 of this solution reduces the damage to the bonding pad of the bare core by more than 50% by optimizing the contact pressure distribution. Among them, the test machine 02 is also used to receive the test results fed back by the core to be tested in response to the high-frequency test signal and the low-frequency test signal, and upload them to the host computer.

[0038] This application integrates two major functions, high-frequency testing and low-frequency testing, and realizes interference-free switching between high-frequency and low-frequency testing of the bare core through a row of probes equipped on the probe card 01, in conjunction with the high-speed switching matrix 03. Since the probe card 01 is only equipped with one row of probes, the cost of the probes is reduced, the difficulty and complexity of production are reduced, and only one alignment operation is required during the test process, which simplifies the test process and improves the test efficiency. At the same time, the connection between the probe and the bare core only needs to be completed once, which significantly reduces the accuracy and complexity requirements of the robot arm, further reducing the difficulty and cost of operation. One-time contact also effectively reduces damage to the bonding pad of the bare core and improves the packaging yield.

[0039] In one embodiment, the high-speed switching matrix 03 includes: A plurality of high-speed electronic relays, wherein the first input end of each of the high-speed electronic relays is connected to the high-frequency output end of the test machine 02, the second input end of each of the high-speed electronic relays is connected to the low-frequency output end of the test machine 02, and the output end of each of the high-speed electronic relays is connected to the single-row probe 11 through the signal transmission layer; The relay control circuit has an input end connected to an external signal and the tester 02, and an output end connected to a control end of each of the high-speed electronic relays.

[0040] The high-speed switching matrix 03 is composed of multiple high-speed electronic relays and a master control relay control circuit, wherein each high-speed electronic relay includes components such as a coil, a contact, and a spring. When the coil is energized, a magnetic field is generated, causing the contacts to close or open, thereby controlling the connection or disconnection of the circuit. By precisely controlling the coil current of each relay unit, precise control of the entire high-speed switching matrix 03 can be achieved. Each high-speed electronic relay is simultaneously connected to the high-frequency output terminal and the low-frequency output terminal of the test machine 02, which means that during the test process, the signal frequency can be quickly switched according to the requirements of the bare core to be tested. This flexibility is essential for testing multiple types of electronic devices, as different devices may have different requirements for signal frequencies.

[0041] At the same time, the present application adopts high-speed electronic relays with fast switching speed, which can complete the on-off switching of the circuit in milliseconds to meet the needs of high-speed electronic equipment. Since the relay array is composed of multiple relay units, it has high reliability. Even if a relay unit fails, it will not affect the normal operation of the entire array. At the same time, the high-speed electronic relay array can expand the control scale by increasing the number of relay units to meet the needs of different application scenarios.

[0042] The relay control circuit is connected to the external signal and the test machine 02, and can be controlled by external instructions or instructions of the test machine 02 to achieve more complex switching logic control. External instructions are manual instructions, which allow operators to manually trigger the start of the high-speed switching matrix 03 through an external manually operated device. In certain emergency situations, when the automatic control system cannot work normally due to a fault or abnormality, the operator can quickly intervene through this external device and manually control the high-speed switching matrix 03 to ensure the continuity and safety of the test.

[0043] In this embodiment, the first input end of each high-speed electronic relay is connected to the high-frequency output end of the test machine 02, the second input end of each high-speed electronic relay is connected to the low-frequency output end of the test machine 02, and the output end of each high-speed electronic relay is connected to the single-row probe 11 through the signal transmission layer, and can quickly switch the working state after receiving the switching instruction, speed up the test speed, and improve the test efficiency. The high-speed switching matrix 03 of this embodiment not only has a high degree of automation, but also retains the necessary manual control capability to cope with various complex and changeable application scenarios.

[0044] In one embodiment, the high-speed switching matrix 03 further includes: An external signal input circuit, the input end of which is electrically connected to the external signal, and the output end of which is electrically connected to the input end of the relay control circuit; a test machine 02 signal input circuit, the input end of which is connected to the control signal output end of the test machine 02, and the output end of which is electrically connected to the input end of the relay control circuit.

[0045] Specifically, the signal input circuit of the test machine 02 receives and processes the control signal from the test machine 02. The input end of the circuit is connected to the control signal output end of the test machine 02, and its output end is also connected to the input end of the relay control circuit, so that the test machine 02 can directly control the high-speed switching matrix 03. The test machine 02 can adjust the working state of the switching matrix in real time according to the test results to meet the needs of different test stages.

[0046] At the same time, the external signal input circuit receives and processes various signals from outside the wafer test system. The input end of the circuit is electrically connected to the external signal source to ensure accurate signal reception; and its output end is connected to the input end of the relay control circuit to transmit the received external signal to the relay control circuit in real time, thereby realizing remote control of the high-speed switching matrix 03. External instructions are manual instructions. By connecting an external manually operated device, the operator is allowed to manually trigger the start of the high-speed switching matrix 03. In certain emergency situations, when the automatic control system cannot work normally due to a fault or abnormality, the operator can quickly intervene through this external device and manually control the high-speed switching matrix 03 to ensure the continuity and safety of the test. According to actual test requirements, the tester can bypass the instructions of the test machine 02 and flexibly control the working state of the high-speed switching matrix 03 through the external signal source.

[0047] In one embodiment, it further includes: The robot arm includes a clamping part, which is used to fix the probe card 01. The robot arm drives the probe card 01 to move so that the single-row probes 11 are in contact with the bare core to be tested; the probe station is used to carry the wafer. During the test, the robot arm can accurately drive the probe card 01 to move in multiple dimensions to ensure that the single-row probes 11 can accurately and correctly achieve physical contact with the bare core to be tested, thereby establishing the necessary electrical connection. The robot arm not only improves the degree of automation of the test, but also effectively reduces the errors that may be introduced due to manual operation.

[0048] At the same time, as another important component of the wafer test system, the probe station's main function is to carry the wafer. The design of the probe station needs to fully consider stability and accuracy to ensure that the wafer can always remain in a fixed and accurate position during the test. In this way, when the robot arm drives the probe card 01 to move, the single-row probe 11 can smoothly contact each bare core to be tested on the wafer, thereby completing the test task.

[0049] In one embodiment, the wafer testing system has a high frequency testing mode and a low frequency testing mode; In the high-frequency test mode, the high-speed switching matrix 03 controls the high-frequency output terminal to be electrically connected to the single-row probe 11 according to the received switching instructions, so that the high-frequency test signal generated by the tester 02 is output to the bare chip to be tested. When the wafer test system enters the high-frequency test mode, the high-speed switching matrix 03 will quickly and accurately establish the electrical connection between the high-frequency output terminal and the single-row probe 11 according to the preset or real-time received switching instructions. In this process, the high-speed electronic relays inside the high-speed switching matrix play a key role. They can complete the on-off switching of the circuit within milliseconds, ensuring that the high-frequency test signal can be transmitted to the bare chip to be tested without delay and loss.

[0050] High-frequency test signals are often used to evaluate the performance of bare chips in high-speed digital circuits or radio frequency (RF) applications. Due to the high-frequency characteristics of these signals, the impedance matching, signal attenuation, and noise interference of the transmission path are extremely high. Therefore, the design and manufacture of high-speed switching matrices must achieve extremely high precision and stability to ensure the accuracy and reliability of the test results.

[0051] In the low-frequency test mode, the high-speed switching matrix 03 controls the low-frequency output terminal to be electrically connected to the single-row probe 11 according to the received switching instruction, so that the low-frequency test signal generated by the tester 02 is output to the bare core to be tested. Unlike the high-frequency test mode, the low-frequency test mode is mainly used to evaluate the electrical characteristics of the bare chip at a lower frequency, such as DC resistance, capacitance, inductance, etc. In the low-frequency test mode, the high-speed switching matrix will also control the electrical connection between the low-frequency output terminal and the single-row probe 11 according to the switching instruction.

[0052] The high-speed switching matrix 03 can quickly respond to switching instructions, reduce waiting time during the test process, and thus improve overall test efficiency. By controlling the connection between different output terminals and the single-row probes 11, the high-speed switching matrix 03 can support a variety of test modes and test signal types to meet different test requirements. It also ensures accurate transmission of test signals to avoid test errors caused by connection problems.

[0053] In one embodiment, if Figure 2 As shown, the test machine 02 includes: The main control circuit 23 is connected to the control end of the high-speed switching matrix 03; wherein, the main control circuit 23 is also used to control the high-frequency test circuit 22 to work in the high-frequency test mode to obtain high-frequency test results; the main control circuit 23 is also used to control the low-frequency test circuit 21 to work in the low-frequency test mode to obtain low-frequency test results.

[0054] The high-frequency test circuit 22 is connected to the main control circuit 23, and is used to generate a high-frequency test signal and output it to the bare core to be tested for high-frequency testing, and obtain the high-frequency test result fed back by the bare core to be tested in response to the high-frequency test signal and output it to the main control circuit 23. The high-frequency test circuit 22 includes a Function test (read-write test) circuit, an EFT (Electrical Fast Transient) test circuit, a Timing test (timing test) circuit, an eye diagram test circuit, and a different rate test circuit; in this embodiment, the Function test circuit, the EFT test circuit, the Timing test circuit, the eye diagram test circuit, and the different rate test circuits are performed on an FPGA (Field-Programmable Gate Array) platform.

[0055] Function test circuit, used to verify whether the basic functions of the bare core are normal, including data writing, reading, storage and deletion. By designing test interfaces through FPGA, such as SPI, I2C or parallel interface, communicating with the bare core and comparing the consistency of the read and write programs, it can be determined whether the bare core has functional failures or data errors. This test is the read and write function test described above. The EFT test circuit simulates fast transient electromagnetic interference through the fast transient pulse signal generated by FPGA, and can detect whether the bare core will have problems such as data loss, functional abnormality or damage. The Timing test circuit is used to evaluate the timing performance of the bare core. The bare core is driven by the clock signal generated by the FPGA, and the parameters under different operating conditions are measured to understand the response speed, stability and compatibility of the bare core with other circuits.

[0056] Eye diagram test circuit is an important means to evaluate the quality of the bare core output signal. The eye diagram can intuitively display the waveform, jitter, noise and other characteristics of the signal. By analyzing the parameters such as the opening, closing and cross point of the eye diagram, it can be judged whether the output signal of the bare core is stable and clear, and whether there are potential signal quality problems. The different rate test circuit changes the interface rate of communication with the bare core through FPGA, measures the performance data at different rates, and can understand the rate adaptability, bandwidth and data transmission efficiency of the bare core. These test circuits together constitute an important part of the semiconductor memory device test system. They provide strong support for the performance evaluation, quality control and fault diagnosis of the bare core through their respective test functions and test data. In an embodiment, these test circuits are integrated in a test device including a high-frequency test circuit 22 to achieve efficient and accurate testing.

[0057] The low-frequency test circuit 21 is connected to the main control circuit 23, and is used to generate a low-frequency test signal and output it to the bare core to be tested for low-frequency testing, and obtain the low-frequency test result fed back by the bare core to be tested in response to the low-frequency test signal and output it to the main control circuit 23. The low-frequency test circuit 21 includes a voltage test circuit, an impedance test circuit, a positive current test circuit, a negative current test circuit, an open-short circuit test circuit, a power consumption test circuit and a leakage current test circuit; the voltage test circuit is used to provide different voltages to the bare core to be tested and detect the output voltage of the bare core to be tested at the same time to obtain voltage test data; by adjusting the input voltage, it is possible to observe how the output voltage of the bare core changes, and its voltage adaptability and stability can be evaluated.

[0058] The impedance test circuit calculates the impedance value by applying a specific signal to the bare core to be tested and measuring its response. The impedance test data helps to understand the circuit characteristics and frequency response of the bare core, and provides a basis for circuit design and optimization. At the same time, impedance abnormality may also mean that there is a fault in the circuit, such as component damage, poor contact, etc. The forward current test circuit can evaluate the current driving capability and stability of the bare core by measuring the current response of the bare core under forward current, including current response speed, current stability and current distribution. The negative current test circuit evaluates the performance of the bare core under reverse current conditions, including reverse current tolerance, reverse breakdown voltage, etc. Negative current testing helps to discover potential problems of the bare core under the action of reverse current, such as reverse leakage, so as to ensure its stability and reliability in complex working environments.

[0059] The open-short circuit test circuit is an important means to detect whether there is an open circuit or short circuit fault in the bare core pin. By measuring the resistance or voltage drop between the pins, the connection status between the pins can be determined. It helps to find and repair potential circuit faults in a timely manner. The power consumption test circuit helps to understand the energy consumption of the bare core under different working conditions and provide a basis for circuit design and optimization. At the same time, abnormal power consumption may also mean that there are faults or performance problems in the circuit. The leakage current test circuit is an important means to evaluate whether there is abnormal current leakage in the bare core when it is turned off or in a low-level state. By measuring the size of the leakage current, the insulation performance and stability of the bare core can be determined. These test circuits together constitute an important part of the semiconductor test system, and they provide strong support for the performance evaluation, quality control and fault diagnosis of the bare core through their respective test functions and test data. In an embodiment, these test circuits are integrated in a test device including a low-frequency test circuit 21 to achieve automated testing and efficient testing.

[0060] In one embodiment, the testing machine 02 further includes: The communication circuit is connected to the communication interface of the main control circuit 23 and is used for communication between the test machine 02 and the host computer; the main control circuit 23 is used to receive and output a control signal to the high-speed switching matrix 03 according to the instruction of the host computer, so as to control the high-speed switching matrix 03 to connect the high-frequency output end / low-frequency output end with the single-row probe 11, and obtain the test results and upload them to the host computer. The communication circuit electrically connects the test machine 02 and the host computer; the communication circuit is used for communication between the test machine 02 and the host computer. The test machine 02 communicates with the host computer through the communication circuit, and the test machine 02 receives the instruction of the host computer through the communication circuit and controls the working state of the test device, and transmits the test results to the host computer through the communication circuit.

[0061] In addition, to achieve the above purpose, the present application also proposes a wafer testing method, which is applied to the wafer testing system based on high-low frequency multiplexing probes as described above, such as Figure 3 As shown, including: S100: placing the wafer in the wafer testing system; S200: Controlling the mechanical arm to move so as to drive the single row of probes 11 on the probe card 01 to contact with the bare core to be tested; S300: The wafer testing system enters the low-frequency testing mode according to the instruction of the host computer, and controls the high-speed switching matrix 03 to connect the low-frequency output terminal with the single-row probe 11; the testing machine 02 generates a low-frequency testing signal according to the instruction of the host computer to perform a low-frequency test on the bare core to be tested, so that the bare core to be tested responds to the low-frequency testing signal and generates a corresponding low-frequency testing result; the testing machine 02 obtains the low-frequency testing result fed back by the bare core to be tested and uploads it to the host computer to test the quality of the bare core to be tested under the low-frequency signal.

[0062] S400: The wafer test system enters the high-frequency test mode according to the instruction of the host computer, and controls the high-speed switching matrix 03 to connect the high-frequency output terminal with the single-row probe 11. The test machine 02 generates a high-frequency test signal to perform a high-frequency test on the bare core to be tested, so that the bare core to be tested responds to the high-frequency test signal and generates a corresponding high-frequency test result; the test machine 02 obtains the high-frequency test result fed back by the bare core to be tested and uploads it to the host computer to test the quality of the bare core to be tested under the high-frequency signal.

[0063] After completing the low-frequency test process based on the bare core to be tested, the bare core with faults has been selected. Since the low-frequency test mainly focuses on the static electrical characteristics of the chip, these characteristics are the basis for the normal operation of the chip. If the chip has a fault during the low-frequency test stage, the subsequent high-frequency test may not accurately reflect the actual performance of the chip, and may even cause damage to the test equipment. Therefore, performing a low-frequency test first can eliminate those basic electrical faults that may cause the chip to not work properly. Therefore, it is necessary to perform a high-frequency test after confirming that the chip has passed the low-frequency test to further verify the performance of the chip at high frequency or actual operating speed.

[0064] This application integrates two major functions, high-frequency testing and low-frequency testing, and realizes interference-free switching between high-frequency and low-frequency testing of the bare core through a row of probes equipped on the probe card 01, in conjunction with the high-speed switching matrix 03. Since the probe card 01 is only equipped with one row of probes, the cost of the probes is reduced, the difficulty and complexity of production are reduced, and only one alignment operation is required during the test process, which simplifies the test process and improves the test efficiency. At the same time, the connection between the probe and the bare core only needs to be completed once, which significantly reduces the accuracy and complexity requirements of the robot arm, further reducing the difficulty and cost of operation. One-time contact also effectively reduces damage to the bonding pad of the bare core and improves the packaging yield.

[0065] In one embodiment of the wafer testing method, the wafer testing system enters the low-frequency testing mode according to the instruction of the host computer, and the specific steps of controlling the high-speed switching matrix 03 to connect the low-frequency output terminal and the single-row probe 11 also include: The test machine 02 generates a low-frequency test signal according to the instruction of the host computer to perform a low-frequency test on the bare core to be tested, so that the bare core to be tested responds to the low-frequency test signal and generates a corresponding low-frequency test result; The tester 02 obtains the low-frequency test result fed back by the bare core to be tested and uploads it to the host computer to test the quality of the bare core to be tested under the low-frequency signal; And / or, the wafer testing system enters the high-frequency testing mode according to the instruction of the host computer, and the specific steps of controlling the high-speed switching matrix 03 to connect the high-frequency output terminal with the single-row probe 11 also include: The tester 02 generates a high-frequency test signal to perform a high-frequency test on the bare core to be tested, so that the bare core to be tested responds to the high-frequency test signal and generates a corresponding high-frequency test result; The test machine 02 obtains the high-frequency test result fed back by the bare core to be tested and uploads it to the host computer to test the quality of the bare core to be tested under the high-frequency signal.

[0066] In one embodiment of the wafer testing method, the wafer testing system enters the high-frequency testing mode according to the instruction of the host computer, and the specific steps of controlling the high-speed switching matrix 03 to connect the high-frequency output terminal with the single-row probe 11 also include: After completing the low-frequency test mode, the wafer test system enters the high-frequency test mode according to the instructions of the host computer. Since the low-frequency test mainly focuses on the static electrical characteristics of the chip, these characteristics are the basis for the normal operation of the chip. If the chip fails during the low-frequency test stage, the subsequent high-frequency test may not accurately reflect the actual performance of the chip, and may even cause damage to the test equipment.

[0067] Therefore, performing low-frequency testing first can rule out basic electrical faults that may cause the chip to not work properly. After confirming that the chip has passed the low-frequency test, performing high-frequency testing can further verify the chip's performance at high frequencies or actual operating speeds. High-frequency testing can reveal potential problems with the chip under dynamic conditions, such as delay failures and signal quality issues. These memory cells may work properly under certain conditions, but may not work properly under other conditions. Their states may be affected by the state transitions of surrounding memory cells, or may change due to slight fluctuations in their own performance. Or the states of some memory cells may be disturbed by the state transitions of adjacent memory cells. For example, when adjacent memory cells switch from a charged state to a discharged state, electromagnetic interference or charge leakage may occur, affecting the states of these memory cells. Therefore, performing low-frequency testing first and then high-frequency testing helps to fully and accurately evaluate the performance and quality of the bare die.

[0068] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A wafer testing system based on high and low frequency multiplexed probes, characterized in that: include: A probe card, wherein a signal transmission layer and a single row of probes are provided on the probe card; One end of the single-row probe is fixed on the probe card and connected to the signal transmission layer, and the other end of the single-row probe is used to realize the electrical connection between the bare core to be tested and the signal transmission layer; A test machine having a high-frequency output terminal and a low-frequency output terminal, the test machine being used to generate a high-frequency test signal and output it through the high-frequency output terminal, and to generate a low-frequency test signal and output it through the low-frequency output terminal; A high-speed switching matrix, wherein a first input end of the high-speed switching matrix is ​​connected to the low-frequency output end, a second input end of the high-speed switching matrix is ​​connected to the high-frequency output end, and an output end of the high-speed switching matrix is ​​connected to a single-row probe through the signal transmission layer; the high-speed switching matrix is ​​used to control the high-frequency output end to be electrically connected to the single-row probe according to the received switching instruction so as to output the high-frequency test signal to the bare core to be tested, or control the low-frequency output end to be electrically connected to the single-row probe so as to output the low-frequency test signal to the bare core to be tested; The test machine is also used to receive the test results fed back by the core to be tested in response to the high-frequency test signal and the low-frequency test signal, and upload them to the host computer.

2. The wafer testing system based on high and low frequency multiplexed probes as claimed in claim 1, characterized in that: The high-speed switching matrix comprises: A plurality of high-speed electronic relays, wherein a first input end of each of the high-speed electronic relays is connected to a high-frequency output end of the test machine, a second input end of each of the high-speed electronic relays is connected to a low-frequency output end of the test machine, and an output end of each of the high-speed electronic relays is connected to a single-row probe through the signal transmission layer; The relay control circuit has an input end connected to an external signal and the test machine, and an output end connected to a control end of each high-speed electronic relay.

3. The wafer testing system based on high and low frequency multiplexed probes as claimed in claim 2, characterized in that: The high-speed switching matrix also includes: An external signal input circuit, the input end of which is electrically connected to the external signal, and the output end of which is electrically connected to the input end of the relay control circuit; The test machine signal input circuit has an input end connected to the control signal output end of the test machine, and an output end electrically connected to the input end of the relay control circuit.

4. The wafer testing system based on high- and low-frequency multiplexed probes according to any one of claims 1 to 3, characterized in that: Also includes: A mechanical arm, comprising a clamping portion, wherein the clamping portion is used to fix the probe card, and the mechanical arm drives the probe card to move so that the single row of probes contacts the bare core to be tested; Probe station, used to carry wafers.

5. The wafer testing system based on high and low frequency multiplexed probes as claimed in claim 1, characterized in that: The wafer testing system has a high frequency testing mode and a low frequency testing mode; In the high-frequency test mode, the high-speed switching matrix controls the high-frequency output terminal to be electrically connected to the single-row probe according to the received switching instruction, so that the high-frequency test signal generated by the tester is output to the bare core to be tested; In the low-frequency test mode, the high-speed switching matrix controls the low-frequency output terminal to be electrically connected to the single-row probe according to the received switching instruction, so that the low-frequency test signal generated by the tester is output to the bare core to be tested.

6. The wafer testing system based on high and low frequency multiplexed probes as claimed in claim 5, characterized in that: The testing machine comprises: A main control circuit connected to the control end of the high-speed switching matrix; A high-frequency test circuit is connected to the main control circuit, and is used to generate a high-frequency test signal and output it to the bare core to be tested for high-frequency testing, and obtain a high-frequency test result fed back by the bare core to be tested in response to the high-frequency test signal and output it to the main control circuit; A low-frequency test circuit is connected to the main control circuit, and is used to generate a low-frequency test signal and output it to the bare core to be tested for low-frequency testing, and obtain a low-frequency test result fed back by the bare core to be tested in response to the low-frequency test signal and output it to the main control circuit; Wherein, the main control circuit is also used to control the high-frequency test circuit to work in the high-frequency test mode to obtain a high-frequency test result; The main control circuit is also used to control the low-frequency test circuit to work in the low-frequency test mode to obtain a low-frequency test result.

7. The wafer testing system based on high and low frequency multiplexed probes as claimed in claim 6, characterized in that: The testing machine also includes: A communication circuit connected to the communication interface of the main control circuit and used for communication between the test machine and the host computer; The main control circuit is used to receive and output control signals to the high-speed switching matrix according to the instructions of the host computer, so as to control the high-speed switching matrix to connect the high-frequency output terminal / low-frequency output terminal with the single-row probe, and to obtain test results and upload them to the host computer.

8. A wafer testing method, applied to the wafer testing system based on high- and low-frequency multiplexed probes as described in any one of claims 1 to 7, characterized in that: include: placing the wafer in a wafer test system; Controlling the movement of the mechanical arm to drive the single row of probes on the probe card to contact the bare core to be tested; The wafer testing system enters a low-frequency testing mode according to the instruction of the host computer, and controls the high-speed switching matrix to connect the low-frequency output terminal with the single-row probe; The wafer testing system enters a high-frequency testing mode according to the instruction of the host computer, and controls the high-speed switching matrix to connect the high-frequency output terminal with the single-row probe.

9. The wafer testing method according to claim 8, characterized in that: The wafer testing system enters the low-frequency testing mode according to the instruction of the host computer, and the specific steps of controlling the high-speed switching matrix to connect the low-frequency output terminal with the single-row probe also include: The test machine generates a low-frequency test signal according to the instruction of the host computer to perform a low-frequency test on the bare core to be tested, so that the bare core to be tested responds to the low-frequency test signal and generates a corresponding low-frequency test result; The test machine obtains the low-frequency test result fed back by the bare core to be tested and uploads it to the host computer to test the quality of the bare core to be tested under the low-frequency signal; And / or, the wafer testing system enters the high-frequency testing mode according to the instruction of the host computer, and the specific steps of controlling the high-speed switching matrix to connect the high-frequency output terminal with the single-row probe also include: The tester generates a high-frequency test signal to perform a high-frequency test on the bare core to be tested, so that the bare core to be tested responds to the high-frequency test signal and generates a corresponding high-frequency test result; The test machine obtains the high-frequency test result fed back by the bare core to be tested and uploads it to the host computer to test the quality of the bare core to be tested under the high-frequency signal.

10. The wafer testing method according to claim 8, characterized in that: The wafer test system enters the high-frequency test mode according to the instruction of the host computer, and the specific steps of controlling the high-speed switching matrix to connect the high-frequency output terminal and the single-row probe also include: Upon completion of the low-frequency test mode, the wafer test system enters the high-frequency test mode according to the instruction of the host computer.

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