Wafer-Level Intelligent Optical Computing Chip System and Architecture

Abstract

The present disclosure relates to the field of optical computing technologies, and particularly to a wafer-level intelligent optical computing chip system and architecture. The system includes: a high-energy-efficiency information encoding and compression module for encoding and compressing an input matrix through multiple information channels to obtain a first encoded vector; a reconfigurable information encoding and compression module for calculating weights with multiple information reconfigurations of the input matrix to obtain a second encoded vector; a general feature calculation module for performing general feature calculation on the first encoded vector and the second encoded vector to obtain a feature vector; a high-energy-efficiency feature decoding and characterization module for performing first decoding and characterization on the feature vector to obtain a first decoded vector; a reconfigurable feature decoding and characterization module for performing second decoding and characterization on the feature vector to obtain a second decoded vector; and an output module for fusing the first decoded vector and the second decoded vector to obtain a target calculation result. The present disclosure supports optical deployment of intelligent computing networks with higher parameter quantities.

Description

Technical Field

[0001] The present disclosure relates to the field of optical computing technologies, and particularly to a wafer-level intelligent optical computing chip system and architecture. Background Art

[0002] With the rapid development of the fields of artificial intelligence and scientific computing, the complexity and scale of computing requirements are also increasing continuously. However, for existing electronic computing, its performance is gradually approaching the saturation state, and it is difficult to effectively meet the increasingly stringent requirements for computing power and power consumption of large-scale complex algorithms. Light has natural advantages such as high throughput and low latency during the propagation process. Optical computing technology using photons instead of electrons as the computing carrier is regarded as the key to breaking the existing computing bottleneck. Summary of the Invention

[0003] The present disclosure aims to solve at least one of the technical problems in the related art to some extent.

[0004] To this end, the first object of the present disclosure is to propose a wafer-level intelligent optical computing chip system.

[0005] The second object of the present disclosure is to propose a calculation method for the wafer-level intelligent optical computing chip system.

[0006] To achieve the above object, an embodiment of the first aspect of the present disclosure proposes a wafer-level intelligent optical computing chip system, including:

[0007] A high-energy-efficiency information encoding and compression module, configured to perform multi-channel information channel encoding and compression on an input matrix through a diffraction encoding device to obtain a first encoded vector;

[0008] A reconfigurable information encoding and compression module, configured to perform multi-channel information reconfigurable calculation weights on the input matrix through a phase modulation device or an amplitude modulation device to obtain a second encoded vector;

[0009] A general feature calculation module, configured to perform general feature calculation on the first encoded vector and the second encoded vector to obtain a feature vector;

[0010] A high-energy-efficiency feature decoding and characterization module, configured to perform first decoding and characterization on the feature vector to obtain a first decoded vector, wherein the structure of the high-energy-efficiency feature decoding and characterization module is dual to the structure of the high-energy-efficiency information encoding and compression module;

[0011] A reconfigurable feature decoding and characterization module, configured to perform second decoding and characterization on the feature vector to obtain a second decoded vector, wherein the structure of the reconfigurable feature decoding and characterization module is dual to the structure of the reconfigurable information encoding and compression module;

[0012] An output module, configured to fuse the first decoded vector and the second decoded vector to obtain a target calculation result.

[0013] Optionally, the high - energy - efficiency information encoding and compression module and the reconfigurable information encoding and compression module are deployed on a wafer.

[0014] Optionally, the general - feature calculation module performs general - feature calculation on the first encoded vector and the second encoded vector through a fully reconfigurable arbitrary matrix calculation unit with an MZI or cross - bar structure to obtain a feature vector.

[0015] Optionally, the system further includes an auxiliary module, configured to assist the wafer - level intelligent optical computing chip system in completing large - scale complex intelligent computing tasks with high parameter quantities.

[0016] Optionally, the auxiliary module includes a high - speed interface array module, a high - speed modulation module, a loading module, and a data routing and monitoring module. Among them,

[0017] The auxiliary module includes a high - speed interface array module, configured for data coupling and reading;

[0018] The high - speed modulation module, configured for high - speed modulation of calculation information;

[0019] The loading module, configured for loading of electrical control signals;

[0020] The data routing and monitoring module, configured for data routing and monitoring.

[0021] Optionally, the system includes an array of configurable high - energy - efficiency information encoding and compression modules. Each diffractive encoding device in the array has mutually orthogonal weight distributions, and the mutual features are independent.

[0022] Optionally, the output module performs weighted fusion on the first decoded vector and the second decoded vector to obtain a target calculation result.

[0023] To achieve the above object, an embodiment of the second aspect of the present disclosure provides a calculation method applying the wafer - level intelligent optical computing chip system described in the first aspect, including:

[0024] Obtain an input matrix to be calculated, and perform multi - channel information channel encoding and compression on the input matrix to obtain a first encoded vector;

[0025] Perform multi - channel information - reconfigurable calculation weights on the input matrix to obtain a second encoded vector;

[0026] Perform general - feature calculation on the first encoded vector and the second encoded vector to obtain a feature vector;

[0027] Perform a first decoding representation on the feature vector to obtain a first decoding vector;

[0028] Perform a second decoding representation on the feature vector to obtain a second decoding vector;

[0029] Fuse the first decoding vector and the second decoding vector to obtain a target calculation result.

[0030] Another object of the present invention is to provide an electronic device, including:

[0031] At least one processor; and

[0032] A memory communicatively connected to the at least one processor; wherein,

[0033] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method described in the foregoing two aspects.

[0034] Another object of the present invention is to provide a computer storage medium, wherein the computer storage medium stores computer-executable instructions; after the computer-executable instructions are executed by a processor, the computer executes the method described in the foregoing two aspects.

[0035] In summary, the wafer-level intelligent optical computing chip system and architecture provided by the present disclosure, through the division of labor and cooperation of the high-energy efficiency information encoding and compression module, the reconfigurable information encoding and compression module, the general feature calculation module, the high-energy efficiency feature decoding and representation module, and the reconfigurable feature decoding and representation module, can support the optical deployment of intelligent computing networks with higher parameter quantities, improve the computing scale, and thus realize large models with parameter quantities above the billion level in the form of optical computing, supporting the efficient computing of the new generation of large model artificial intelligence.

[0036] Some of the additional aspects and advantages of the present disclosure will be given in the following description, some will become obvious from the following description, or will be understood through the practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and / or additional aspects and advantages of the present disclosure will become obvious and easy to understand from the following description of the embodiments in conjunction with the drawings, wherein:

[0038] Figure 1 is a schematic structural diagram of a wafer-level intelligent optical computing chip system provided by an embodiment of the present disclosure;

[0039] Figure 2 is a schematic structural diagram of a wafer-level intelligent optical computing chip architecture provided by an embodiment of the present disclosure;

[0040] Figure 3 A flowchart showing a calculation method of a wafer-level intelligent optical computing chip system provided by an embodiment of the present disclosure. Detailed implementation manners

[0041] Embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, but should not be construed as a limitation of the present disclosure.

[0042] Currently, for most analog computing architectures, signals may attenuate during transmission and processing, and at the same time, noise will also affect the signal quality. As a result, errors or instability in the calculation results may occur. For optical computing models, due to factors such as material defects, wavefront errors, and uneven transmission in the optical system, various errors will inevitably be introduced in optical computing. These errors may affect the accuracy of the calculation results, resulting in a deviation between the experimental results and the simulation data. If the number of parameters of the optical neural network is expanded by simple layer stacking, the errors will gradually accumulate during propagation, ultimately having a huge wrong impact on the output.

[0043] In the prior art, an array composed of 56 cascaded Mach-Zehnder Interferometers (MZIs) can be used to complete the classification of four vowel acoustic signals, or a deep diffraction neural network based on the cascade of optical diffraction masks can be used to achieve visual tasks such as handwritten digit recognition and image saliency detection; the ability of multi-channel parallel processing for diffraction optical computing is given by the beam splitting and aggregation of the optical path.

[0044] However, due to the errors in the analog computing and optical calibration processes in the above prior art, the scalability of the common paradigm of optical computing based on interference and diffraction is limited and cannot be extended to large-scale applications, thus limiting the complexity of intelligent optical computing tasks.

[0045] The present disclosure will be described in detail below with reference to specific embodiments.

[0046] Figure 1 A schematic structural diagram of a wafer-level intelligent optical computing chip system provided by an embodiment of the present disclosure. As Figure 1 shown, the wafer-level intelligent optical computing chip system includes:

[0047] A high-energy efficiency information encoding and compression module 101, configured to encode and compress an input matrix through a diffraction encoding device to obtain a first encoded vector;

[0048] The reconfigurable information encoding and compression module 102 is used to perform multiplexed information reconfigurable computational weights on the input matrix through a phase modulation device or an amplitude modulation device to obtain a second encoded vector;

[0049] The general feature calculation module 103 is used to perform general feature calculation on the first encoded vector and the second encoded vector to obtain a feature vector;

[0050] The high-energy efficiency feature decoding and characterization module 104 is used to perform first decoding and characterization on the feature vector to obtain a first decoded vector, where the structure of the high-energy efficiency feature decoding and characterization module is dual to the structure of the high-energy efficiency information encoding and compression module;

[0051] The reconfigurable feature decoding and characterization module 105 is used to perform second decoding and characterization on the feature vector to obtain a second decoded vector, where the structure of the reconfigurable feature decoding and characterization module is dual to the structure of the reconfigurable information encoding and compression module;

[0052] The output module 106 is used to fuse the first decoded vector and the second decoded vector to obtain a target calculation result.

[0053] In an embodiment of the present disclosure, the above wafer-level intelligent optical computing chip system is applicable to large matrix calculations. Based on this, the above wafer-level intelligent optical computing chip system can be applicable to multiple scenarios, such as the classification of intelligent computing tasks.

[0054] Among them, in an embodiment of the present disclosure, the above high-energy efficiency information encoding and compression module can use an on-chip diffraction computing device with pre-trained parameters to perform multiplexed information channel encoding and compression on the input matrix to achieve channel redundancy elimination. In an embodiment of the present disclosure, the above high-energy efficiency information encoding and compression module is passive modulation and weight non-reconfigurable, with high area efficiency and low computational energy consumption. And, in an embodiment of the present disclosure, the above system may include an array of high-energy efficiency information encoding and compression modules that can be set. Each diffraction encoding device in the array has mutually orthogonal weight distributions, and the mutual features are independent. Specifically, on the wafer-level chip system, the array composed of the above modules is mainly used for preliminary modulation and semantic extraction of information, and different numbers and scales of arrays can be activated according to the task difficulty.

[0055] Moreover, in an embodiment of the present disclosure, the above-mentioned reconfigurable information encoding and compression module may use a phase modulation device or an amplitude modulation device to provide precisely reconfigurable computational weights for multiplexed information of the input matrix, and fuse the subsequent multiplexed information. Among them, in an embodiment of the present disclosure, the above-mentioned reconfigurable information encoding and compression module may be actively modulated and weight-trainable, with a high degree of computational freedom, and can be used for weight migration between different computational tasks in general computing. In an embodiment of the present disclosure, the above-mentioned reconfigurable information encoding and compression module may be used as a supplement to the aforementioned energy-efficient information encoding and compression module and be deployed on a wafer in cooperation with it.

[0056] Furthermore, in an embodiment of the present disclosure, the above-mentioned general feature calculation module may perform cascaded multiplexing in depth or breadth through a fully reconfigurable arbitrary matrix calculation unit with an MZI or cross-bar structure, perform general feature calculation on the first encoded vector and the second encoded vector, and obtain a feature vector to achieve general feature calculation of any scale. Among them, the above-mentioned general feature calculation module performs further high-degree-of-freedom calculation processing on the above-mentioned encoded first encoded vector and second encoded vector, and its weights can be flexibly switched according to different tasks. Moreover, in an embodiment of the present disclosure, multiple general feature calculation modules may be deployed on a wafer-level chip system and can be selectively activated and expanded according to the calculation scale.

[0057] Furthermore, in an embodiment of the present disclosure, the above-mentioned energy-efficient feature decoding and characterization module may use a structure dual to the energy-efficient information encoding and compression module and pre-trained decoding weights to decode and characterize the feature vector of the general feature calculation module and map it to a second decoded vector output by the middle layer of the high-dimensional network. Among them, the above-mentioned energy-efficient feature decoding and characterization module may be deployed on a wafer-level system in the form of multiple cores, and a computational array with orthogonal decoding weights expands the output dimension.

[0058] Furthermore, in an embodiment of the present disclosure, the above-mentioned reconfigurable feature decoding and characterization module may use a structure dual to the reconfigurable information encoding and compression module and pre-trained weights as a supplement to the energy-efficient feature decoding and characterization module to achieve task versatility in feature decoding and characterization.

[0059] Among them, in an embodiment of the present disclosure, the above-mentioned output module performs weighted fusion on the first decoded vector and the second decoded vector to obtain a target calculation result.

[0060] Also, in an embodiment of the present disclosure, the above system may further include an auxiliary module for assisting the above wafer-level intelligent optical computing chip system to complete large-scale complex intelligent computing tasks with a large number of high parameters. Among them, the above auxiliary module includes a high-speed interface array module, a high-speed modulation module, a loading module, and a data routing and monitoring module. Among them,

[0061] The high-speed interface array module is used for data coupling and reading;

[0062] The high-speed modulation module is used for high-speed modulation of computing information;

[0063] The loading module is used for loading of electrical control signals;

[0064] The data routing and monitoring module is used for data routing and monitoring.

[0065] Among them, in an embodiment of the present disclosure, the above auxiliary module can cooperate with the above modules to form a wafer-level device array to achieve large-scale complex intelligent computing tasks with a large number of high parameters.

[0066] In summary, the wafer-level intelligent optical computing chip system provided in this embodiment, through the division of labor and cooperation of the high-energy efficiency information encoding and compression module, the reconfigurable information encoding and compression module, the general feature calculation module, the high-energy efficiency feature decoding and characterization module, and the reconfigurable feature decoding and characterization module, can support the optical deployment of intelligent computing networks with a higher number of parameters, improve the computing scale, and thus realize large models with more than hundreds of millions of parameter levels in the form of optical computing, support the efficient computing of a new generation of large model artificial intelligence, and has broad application prospects. It can be applied to fields such as unmanned systems, autonomous driving, and ultrafast science.

[0067] Figure 2 This is the wafer-level intelligent optical computing chip architecture of the present invention. As Figure 2 shown, this architecture is composed of cascaded multi-layer optical computing chips. Each part in the chip is reverse-designed driven by the intelligent task target, so the optimal computing performance can be guaranteed.

[0068] To implement the above embodiment, Figure 3 The present disclosure also proposes a computing method applying the wafer-level intelligent optical computing chip system. As Figure 3 shown, this method may include the following steps:

[0069] Step 301: Obtain the input matrix to be calculated, and perform multi-channel information channel encoding and compression on the input matrix to obtain the first encoded vector;

[0070] Step 302: Perform multi-channel information reconfigurable computing weights on the input matrix to obtain the second encoded vector;

[0071] Step 303: Perform general feature calculation on the first encoding vector and the second encoding vector to obtain a feature vector;

[0072] Step 304: Perform first decoding characterization on the feature vector to obtain a first decoding vector;

[0073] Step 305: Perform second decoding characterization on the feature vector to obtain a second decoding vector;

[0074] Step 306: Fuse the first decoding vector and the second decoding vector to obtain a target calculation result.

[0075] The collection, storage, use, processing, transmission, provision, and disclosure of the user's personal information involved in this disclosure all comply with the provisions of relevant laws and regulations and do not violate public order and good customs.

[0076] It should be noted that personal information from users should be collected for legal and reasonable purposes and should not be shared or sold outside of these legitimate uses. In addition, such collection / sharing should be carried out after obtaining the informed consent of the user, including but not limited to notifying the user to read the user agreement / user notice and signing an agreement / authorization including authorizing relevant user information before the user uses this function. In addition, any necessary steps should be taken to safeguard and protect access to such personal information data and ensure that others with access to personal information data comply with their privacy policies and procedures.

[0077] This disclosure anticipates providing embodiments that allow users to selectively block the use or access of personal information data. That is, this disclosure anticipates providing hardware and / or software to prevent or block access to such personal information data. Once personal information data is no longer needed, the risk can be minimized by restricting data collection and deleting the data. In addition, when applicable, personal identifiers are removed from such personal information to protect the privacy of the user.

[0078] In the technical solution of this disclosure, the acquisition, transmission, storage, use, processing, etc. of data all comply with the relevant provisions of national laws and regulations.

[0079] It should be noted that in the embodiments of this disclosure, certain industry-existing solutions such as software, components, models, etc. may be mentioned. They should be considered exemplary, and their purpose is only to illustrate the feasibility in the implementation of the technical solution of this application, but it does not mean that the applicant has already or necessarily used this solution.

[0080] In the description of the foregoing embodiments, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0081] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0082] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logic function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations, where the functions may be executed in a substantially simultaneous manner or in a reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present disclosure pertain.

[0083] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a definite sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch instructions from the instruction execution system, apparatus, or device and execute the instructions), or in conjunction with these instruction execution systems, apparatuses, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection portion having one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable medium on which a program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpretation, or otherwise processing as appropriate, and then storing it in a computer memory.

[0084] It should be understood that various parts of the present disclosure can be implemented by hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.

[0085] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the methods of the above-described embodiments can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium, and when the program is executed, it includes one or a combination of the steps of the method embodiments.

[0086] In addition, in various embodiments of the present disclosure, each functional unit may be integrated into a processing module, may exist physically alone for each unit, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0087] The above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A wafer-level intelligent optical computing chip system, characterized in that: include: A high-energy-efficiency information coding and compression module, used to perform multi-channel information channel coding and compression on the input matrix through a diffraction coding device to obtain a first coding vector; A reconfigurable information coding compression module is used to perform multi-path information reconfigurable calculation weights on the input matrix through a phase modulation device or an amplitude modulation device to obtain a second coding vector; A general feature calculation module, used for performing general feature calculation on the first coding vector and the second coding vector to obtain a feature vector; A high energy efficiency feature decoding and characterization module, used for performing a first decoding and characterization on the feature vector to obtain a first decoding vector, wherein the structure of the high energy efficiency feature decoding and characterization module is relatively dual to the structure of the high energy efficiency information coding and compression module; A reconfigurable feature decoding representation module is used to perform a second decoding representation on the feature vector to obtain a second decoding vector, wherein the structure of the reconfigurable feature decoding representation module is relatively dual to the structure of the reconfigurable information coding compression module; An output module is used to fuse the first decoding vector with the second decoding vector to obtain a target calculation result.

2. The system according to claim 1, characterized in that The energy-efficient information coding and compression module and the reconfigurable information coding and compression module are deployed on a wafer.

3. The system according to claim 1, characterized in that The general feature calculation module performs general feature calculation on the first coding vector and the second coding vector through a fully reconfigurable arbitrary matrix calculation unit of an MZI or cross-bar structure to obtain a feature vector.

4. The system according to claim 1, characterized in that The system also includes an auxiliary module for assisting the wafer-level intelligent optical computing chip system to complete large-scale, high-parameter complex intelligent computing tasks.

5. The system according to claim 4, characterized in that The auxiliary module includes a high-speed interface array module, a high-speed modulation module, a loading module and a data routing and monitoring module, wherein: The high-speed interface array module is used for data coupling and reading; The high-speed modulation module is used for high-speed modulation of calculation information; The loading module is used for loading the electric control signal; The data routing and monitoring module is used for data routing and monitoring.

6. The system according to claim 1, characterized in that The system comprises an array of configurable high energy efficiency information coding compression modules, wherein each diffraction coding device in the array has mutually orthogonal weight distributions and their characteristics are independent of each other.

7. The system according to claim 1, characterized in that The output module performs weighted fusion on the first decoding vector and the second decoding vector to obtain a target calculation result.

8. A computing method using the wafer-level intelligent optical computing chip system as claimed in claim 1, characterized in that: include: Obtaining an input matrix to be calculated, and performing multi-channel information channel coding compression on the input matrix to obtain a first coding vector; The input matrix is ​​subjected to multi-path information reconfigurable calculation weights to obtain a second encoding vector; Performing common feature calculation on the first encoding vector and the second encoding vector to obtain a feature vector; Performing a first decoding representation on the feature vector to obtain a first decoding vector; Performing a second decoding representation on the feature vector to obtain a second decoding vector; The first decoding vector and the second decoding vector are merged to obtain a target calculation result.

9. An electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of claim 8.

10. A computer storage medium, wherein: The computer storage medium stores computer executable instructions; after the computer executable instructions are executed by the processor, the method according to claim 8 can be implemented.

Images