Intelligent light calculation large model training chip system and calculation method

Abstract

The invention relates to the technical field of optical computing, in particular to an intelligent optical computing large model training chip system and a computing method. The system comprises a plurality of optical chips, and each optical chip comprises a plurality of digital-to-analog converters used for converting digital electric signals of a plurality of input parameters and a plurality of variable parameters which need to be calculated into analog electric signals; the plurality of on-chip attenuators are connected with the plurality of digital-to-analog converters and are used for converting the analog electric signals of the plurality of input parameters and the plurality of variable parameters which need to be calculated into analog optical signals and multiplying the plurality of input parameters and the plurality of variable parameters to obtain a plurality of multiplication results; and the summation module is used for adding the multiple multiplication results to obtain a target output result. According to the invention, through the plurality of optical chips, the high-speed parallel processing characteristic of photons is fully utilized, the calculation task is processed through photonization, and the efficiency and throughput of model training are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of optical computing technology, and in particular to an intelligent optical computing large model training chip system and a computing method. Background Art

[0002] With the development of deep learning and large models, the complexity and scale of computing requirements for the model training process of large models are also increasing. However, the existing electronic computing architecture faces high power consumption and computing delays when processing large-scale parallel computing tasks, and it is difficult to effectively cope with the increasingly stringent demands of large models for computing power and power consumption. Among them, optical computing uses photons for information transmission and processing, and has the advantages of ultra-high speed and low energy consumption. Based on this, optical computing technology that uses photons instead of electrons as computing carriers is regarded as the key to breaking the existing computing bottleneck. Summary of the invention

[0003] The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

[0004] To this end, the first purpose of the present invention is to propose an intelligent optical computing large model training chip system, which uses multiple optical chips to fully utilize the high-speed parallel processing characteristics of photons to realize photonic processing computing tasks, thereby improving the efficiency and throughput of model training.

[0005] The second objective of the present disclosure is to propose a calculation method for an intelligent optical computing large model training chip system.

[0006] To achieve the above-mentioned purpose, the first aspect of the present disclosure proposes an intelligent optical computing large model training chip system, the system comprising a plurality of optical chips, each of which comprises: A plurality of digital-to-analog converters, used for converting digital electrical signals of a plurality of input parameters and a plurality of variable parameters to be calculated into analog electrical signals; A plurality of on-chip attenuators, connected to the plurality of digital-to-analog converters, for converting analog electrical signals of the plurality of input parameters and the plurality of variable parameters to be calculated into analog optical signals, and multiplying the plurality of input parameters and the plurality of variable parameters to obtain a plurality of multiplication results; A summing module is used to add the multiple multiplication results to obtain a target output result.

[0007] Optionally, the summing module includes a plurality of on-chip phase shifters and a sub-wavelength diffraction calculation module, wherein: The summing module ensures the uniformity of the input phase through the multiple on-chip phase shifters, and effectively regulates and controls the light on the chip through the sub-wavelength diffraction calculation module.

[0008] Optionally, the parameters in the sub-wavelength diffraction calculation module are pre-trained, and the sub-wavelength diffraction calculation module is used to implement an addition operation of multiple inputs and one output.

[0009] Optionally, each on-chip attenuator in some of the multiple on-chip attenuators is used to convert the analog electrical signal of the input parameter to be calculated into an analog optical signal, and each on-chip attenuator in the remaining part of the on-chip attenuators is used to convert the analog electrical signal of the corresponding variable parameter into an analog optical signal, wherein each input parameter has a corresponding variable parameter.

[0010] Optionally, the optical chip guides light into and out of the optical chip through a plurality of eight-channel optical fiber arrays with a period of 127 µm and a tilt angle of 8°.

[0011] Optionally, the multiple optical chips are integrated onto the entire PCB board.

[0012] Optionally, the optical chip and the thermistor are mounted on a copper block, wherein the thermistor is used to measure the temperature of the chip, and a thermoelectric temperature controller TEC is attached to the copper block.

[0013] Optionally, the thermistor and the TEC establish a proportional-integral-differential PID feedback loop, and the feedback loop is used to maintain the temperature of the optical chip within a preset range.

[0014] To achieve the above-mentioned purpose, the second aspect of the present disclosure proposes a calculation method for a large-model training chip system for intelligent optical computing, including: Converting digital electrical signals of multiple input parameters and multiple variable parameters to be calculated into analog electrical signals through multiple digital-to-analog converters; Using a plurality of on-chip attenuators connected to the plurality of digital-to-analog converters, converting the analog electrical signals of the plurality of input parameters and the plurality of variable parameters to be calculated into analog optical signals, and multiplying the plurality of input parameters and the plurality of variable parameters to obtain a plurality of multiplication results; The multiple multiplication results are added together to obtain a target output result.

[0015] Another object of the present invention is to provide an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the methods described in the above two aspects.

[0016] Another object of the present invention is to provide a computer storage medium, wherein the computer storage medium stores computer executable instructions; after the computer executable instructions are executed by a processor, the computer executes the methods described in the above two aspects.

[0017] In summary, the intelligent optical computing large model training chip system and computing method provided by the present invention fully utilize the high-speed parallel processing characteristics of photons through multiple optical chips, realize photonic processing computing tasks, and improve the efficiency and throughput of model training.

[0018] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which: Figure 1 A schematic diagram of the structure of an intelligent optical computing large model training chip system provided by an embodiment of the present disclosure; Figure 2 A schematic diagram of the structure of a summation module provided in an embodiment of the present disclosure; Figure 3 A flowchart of a calculation method for an intelligent optical computing large model training chip system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0021] The present disclosure is described in detail below with reference to specific embodiments.

[0022] Figure 1 This is a schematic diagram of the structure of an intelligent optical computing large model training chip system provided by the embodiment of the present disclosure. Figure 1 As shown, the system includes: A plurality of digital-to-analog converters, used for converting digital electrical signals of a plurality of input parameters and a plurality of variable parameters to be calculated into analog electrical signals; A plurality of on-chip attenuators are connected to a plurality of digital-to-analog converters, and are used to convert analog electrical signals of a plurality of input parameters and a plurality of variable parameters to be calculated into analog optical signals, and to multiply the plurality of input parameters and the plurality of variable parameters to obtain a plurality of multiplication results; The summation module is used to add multiple multiplication results to obtain a target output result.

[0023] In one embodiment of the present disclosure, the above-mentioned large model can be applied to a variety of scenarios, such as intelligent question-answering scenarios.

[0024] Among them, in one embodiment of the present disclosure, the trainable unit in the above-mentioned large model is a multi-layer perceptron layer, and the parameters in the remaining network layers in the large model can directly participate in the calculation without the need for training. Based on this, in an embodiment of the present disclosure, the above-mentioned system may include multiple optical chips to replace the above-mentioned multi-layer perceptron layer with multiple optical chips.

[0025] For example, in one embodiment of the present disclosure, it is assumed that a multi-layer perceptron layer with an input of N×N is transformed into a combination of N optical module layers, so that it can be completely equivalent to an ordinary multi-layer perceptron. Based on this, the complete training of the multi-layer perceptron layer can be completed by training the N combined optical module layers. Thus, the computing structure of an optical module layer can be implemented through an optical chip, so that efficient large-model optical training can be achieved by performing model training on the chip.

[0026] In one embodiment of the present disclosure, each on-chip attenuator in some of the multiple on-chip attenuators is used to convert the analog electrical signal of the input parameter to be calculated into an analog optical signal, and each on-chip attenuator in the remaining part of the on-chip attenuators is used to convert the analog electrical signal of the corresponding variable parameter into an analog optical signal, wherein each input parameter has a corresponding variable parameter.

[0027] Specifically, in one embodiment of the present disclosure, the number of input parameters and variable parameters loaded in the on-chip attenuator is related to the scale of calculation in the optical module layer. Specifically, in one embodiment of the present disclosure, if the optical module layer is N×N, that is, , 2N on-chip attenuators are needed, where N on-chip attenuators are used to load the input parameters to be calculated. , N on-chip attenuators are used to load the variable parameters corresponding to the input parameters , the on-chip attenuator for each input parameter is cascaded with the on-chip attenuator for each variable parameter to complete the multiplication operation The input parameters or variable parameters in each attenuator are provided by a plurality of digital-to-analog converters.

[0028] In one embodiment of the present disclosure, after the output of the multiplication operation is obtained through the above-mentioned multiple on-chip attenuators, the multiple multiplication results can be added together through a summing module to obtain a target output result.

[0029] Specifically, in one embodiment of the present disclosure, in order to achieve Matrix operations on the input matrix, where , the i-th row and i-th column are all 1, and the rest of the elements are 0. Among them, Figure 2 FIG. 1 is a schematic diagram of a structure of a summation module proposed in an embodiment of the present disclosure. Figure 2 As shown, the above-mentioned summing module may include multiple on-chip phase shifters and sub-wavelength diffraction calculation modules, wherein the summing module ensures the uniformity of the input phase through multiple on-chip phase shifters, and effectively regulates and controls the light on the chip through the sub-wavelength diffraction calculation module.

[0030] Among them, the number of the above-mentioned on-chip phase shifters is related to the dimension of the output parameter of the on-chip attenuator. For example, if the dimension of the output parameter of the above-mentioned on-chip attenuator is N, the summation module includes N on-chip phase shifters, wherein the N on-chip phase shifters can ensure the uniformity of the input phase and eliminate the phase error of the off-chip light propagation. And, the above-mentioned on-chip subwavelength diffraction structure is an optical structure based on nanoscale characteristic dimensions, which can effectively regulate and manipulate light on the chip. Its parameters are loaded on air slots of different lengths on the flat waveguide. When the width and spacing are constant, the phase change of light passing through the subwavelength diffraction structure is only related to its length.

[0031] Further, in one embodiment of the present disclosure, the parameters in the above-mentioned sub-wavelength diffraction calculation module are pre-trained, and the sub-wavelength diffraction calculation module is used to realize the addition operation of multiple inputs and one output. For example, if the parameter dimension of the on-chip attenuator is N, the sub-wavelength diffraction calculation module can realize the addition operation of N inputs and 1 output. In addition, one of the N outputs will be evenly divided into N-1 light channels on the waveguide as the remaining output ports. As a result, the optical chip can realize an efficient NN optical summation module.

[0032] And, in one embodiment of the present disclosure, an activation propagation operation can be implemented through the above-mentioned structured light chip, and N optical chips can realize the complete N×N multi-layer perceptron training process. Among them, the above-mentioned multiple optical chip modules can be integrated into a whole PCB board to form a large model optical training basic unit. Through efficient digital-to-analog-to-digital conversion, the basic unit can be efficiently reused to achieve high-speed and energy-efficient optical training of large models.

[0033] Further, in one embodiment of the present disclosure, multiple eight-channel optical fiber arrays (e.g., two) with a period of 127 µm and a tilt angle of 8° can be used in the above optical chip to guide light into and out of the photonic chip to achieve an efficient and stable chip working system. After aligning the optical fiber array and the grating array using a nanometer-level electric translation stage under a microscope, the vertically coupled optical fiber array is fixed on the PIC with a curable epoxy resin, and the coupling insertion loss of the optical fiber to the chip after packaging is about -8 dB per channel.

[0034] In one embodiment of the present disclosure, the optical chip may further include two layers of dedicated PCB boards for feeding electrical signals on the optical chip. Also, the chip pads on the VOA (variable optical attenuator) array with a spacing of 100 µm are connected to the PCB board by gold wire welding, and are independently led out to the electrical socket through signal lines with a spacing of 800 µm. A customized multi-channel DC signal source is connected to the board, and the injection current of the VOA is controlled by setting a voltage of 0-5V, which effectively adjusts the imaginary part of the effective refractive index of the waveguide mode.

[0035] And, in one embodiment of the present disclosure, the optical chip and the thermistor are mounted on a copper block, wherein the thermistor is used to measure the temperature of the chip, and a TEC (thermoelectric temperature controller, Peltier cooler) is attached to the copper block to cool the packaging system. A proportional-integral-differential (PID) feedback loop is established between the thermistor and the TEC, which can maintain the temperature on the chip within a preset range. In one embodiment of the present disclosure, the preset range can be within ±0.004 Kelvin, corresponding to a long-term resistance stability of the thermistor of ±2 ohms, thereby ensuring the reliability and consistency of the system.

[0036] In the intelligent optical computing large model training chip system of the disclosed embodiment, the above-mentioned optical chip can support high-speed and high-energy-efficiency optical training of large models, greatly improving the efficiency and throughput of model training. It has broad application prospects and provides a new, efficient and green solution for the training of artificial intelligence large models.

[0037] In order to implement the above embodiment, Figure 3 The present disclosure also proposes a calculation method for an intelligent optical computing large model training chip system, which may include the following steps: Step 301, converting digital electrical signals of multiple input parameters and multiple variable parameters to be calculated into analog electrical signals through multiple digital-to-analog converters; Step 302, using a plurality of on-chip attenuators connected to a plurality of digital-to-analog converters, converting analog electrical signals of a plurality of input parameters and a plurality of variable parameters to be calculated into analog optical signals, and multiplying the plurality of input parameters and the plurality of variable parameters to obtain a plurality of multiplication results; Step 303, adding multiple multiplication results to obtain a target output result.

[0038] In the disclosed embodiment, the above-mentioned multiple on-chip attenuators connected to multiple digital-to-analog converters are used to convert analog electrical signals of multiple input parameters and multiple variable parameters that need to be calculated into analog optical signals, and multiply the multiple input parameters and multiple variable parameters to obtain multiple multiplication results, including: using each on-chip attenuator in some of the multiple on-chip attenuators to convert the analog electrical signal of the input parameter that needs to be calculated into an analog optical signal, and each on-chip attenuator in the remaining part of the on-chip attenuators to convert the analog electrical signal of the corresponding variable parameter into an analog optical signal to multiply to obtain multiple multiplication results, wherein each input parameter has a corresponding variable parameter.

[0039] The collection, storage, use, processing, transmission, provision and disclosure of user personal information involved in this disclosure shall comply with the relevant laws and regulations and shall not violate public order and good morals.

[0040] It should be noted that personal information from users should be collected for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. In addition, such collection / sharing should be carried out after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign the agreement / authorization including authorization of relevant user information before the user uses the function. In addition, any necessary steps should be taken to protect and safeguard access to such personal information data and ensure that others who have access to personal information data comply with its privacy policy and procedures.

[0041] The present disclosure anticipates providing implementation schemes for users to selectively block the use or access of personal information data. That is, the present disclosure anticipates providing hardware and / or software to prevent or block access to such personal information data. Once the personal information data is no longer needed, risks can be minimized by limiting data collection and deleting the data. In addition, when applicable, such personal information is de-identified to protect the privacy of the user.

[0042] The acquisition, transmission, storage, use, and processing of data in the technical solution disclosed in this disclosure are in compliance with the relevant provisions of national laws and regulations.

[0043] It should be noted that in the embodiments of the present disclosure, certain software, components, models and other existing solutions in the industry may be mentioned, which should be regarded as exemplary. Their purpose is only to illustrate the feasibility of implementing the technical solution of the present application, but it does not mean that the applicant has or will necessarily use the solution.

[0044] In the description of the aforementioned embodiments, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they contradict each other.

[0045] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0046] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present disclosure belong.

[0047] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing in a suitable manner if necessary, and then stored in a computer memory.

[0048] It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0049] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0050] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0051] The storage medium mentioned above may be a read-only memory, a disk or an optical disk, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present disclosure. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure.

Claims

1. An intelligent optical computing large model training chip system, characterized in that: The system includes a plurality of optical chips, each of which includes: A plurality of digital-to-analog converters, used for converting digital electrical signals of a plurality of input parameters and a plurality of variable parameters to be calculated into analog electrical signals; A plurality of on-chip attenuators, connected to the plurality of digital-to-analog converters, for converting analog electrical signals of the plurality of input parameters and the plurality of variable parameters to be calculated into analog optical signals, and multiplying the plurality of input parameters and the plurality of variable parameters to obtain a plurality of multiplication results; A summing module is used to add the multiple multiplication results to obtain a target output result.

2. The system according to claim 1, characterized in that The summing module includes a plurality of on-chip phase shifters and a sub-wavelength diffraction calculation module, wherein: The summing module ensures the uniformity of the input phase through the multiple on-chip phase shifters, and effectively regulates and controls the light on the chip through the sub-wavelength diffraction calculation module.

3. The system according to claim 2, characterized in that The parameters in the sub-wavelength diffraction calculation module are pre-trained, and the sub-wavelength diffraction calculation module is used to realize the addition operation of multiple inputs and one output.

4. The system according to claim 1, characterized in that Each on-chip attenuator in some of the multiple on-chip attenuators is used to convert the analog electrical signal of the input parameter to be calculated into an analog optical signal, and each on-chip attenuator in the remaining part of the on-chip attenuators is used to convert the analog electrical signal of the corresponding variable parameter into an analog optical signal, wherein each input parameter has a corresponding variable parameter.

5. The system according to claim 1, characterized in that Light is guided into and out of the optical chip through multiple eight-channel optical fiber arrays with a period of 127 µm and a tilt angle of 8°.

6. The system according to claim 1, characterized in that The multiple optical chips are integrated onto the entire PCB board.

7. The system according to claim 1, characterized in that The optical chip and the thermistor are mounted on a copper block, wherein the thermistor is used to measure the temperature of the chip, and a thermoelectric temperature controller TEC is attached to the copper block.

8. The system according to claim 7, characterized in that The thermistor and the TEC establish a proportional-integral-differential PID feedback loop, and the feedback loop is used to maintain the temperature of the optical chip within a preset range.

9. A computing method for the intelligent optical computing large model training chip system according to any one of claims 1 to 8, characterized in that: include: Converting digital electrical signals of multiple input parameters and multiple variable parameters to be calculated into analog electrical signals through multiple digital-to-analog converters; Using a plurality of on-chip attenuators connected to the plurality of digital-to-analog converters, converting the analog electrical signals of the plurality of input parameters and the plurality of variable parameters to be calculated into analog optical signals, and multiplying the plurality of input parameters and the plurality of variable parameters to obtain a plurality of multiplication results; The multiple multiplication results are added together to obtain a target output result.

10. The method according to claim 9, characterized in that The method comprises: using a plurality of on-chip attenuators connected to the plurality of digital-to-analog converters to convert the analog electrical signals of the plurality of input parameters and the plurality of variable parameters to be calculated into analog optical signals, and multiplying the plurality of input parameters and the plurality of variable parameters to obtain a plurality of multiplication results, including: Each on-chip attenuator in some of the multiple on-chip attenuators converts the analog electrical signal of the input parameter to be calculated into an analog optical signal, and each on-chip attenuator in the remaining part of the on-chip attenuators converts the analog electrical signal of the corresponding variable parameter into an analog optical signal, and multiplies them to obtain multiple multiplication results, wherein each input parameter has a corresponding variable parameter.

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