A chip working parameter multi-section storage method, device, equipment and medium

Abstract

The application discloses a chip working parameter multi-section storage method, device, equipment and medium, and belongs to the electronic information technical field.The method comprises the following steps: when a target working parameter storage event is identified, reading a current value from a storage address indication area to determine a storage area of a current working parameter; determining a starting address for storing the target working parameter according to the storage area of the current working parameter; determining a target storage area of the target working parameter according to the starting address and a preset number of bytes, and writing the target working parameter into the target storage area; and updating the current value in the storage address indication area.The multi-section storage and the construction of the address mapping mechanism can enable the working parameters of the chip to support adjustment and meet the actual use requirements of the chip.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of electronic information technology, and particularly relates to a multi-segment storage method, device and equipment of working parameters of a chip and a medium. BACKGROUND

[0002] With the vigorous development of the science and technology level, the gradual expansion of the consumer electronics and wearable device market, electronic devices will be used in various environments, so the use scenarios of the chip are gradually increasing.

[0003] In many integrated circuits, especially systems requiring high precision and reliability, the working parameters of the chip, such as voltage, clock frequency, etc., need to be adjusted, that is, the TRIM value of the chip is adjusted. However, the traditional OTP (One-Time Programmable) chip can usually write data only once, which makes them unable to flexibly support dynamic adjustment or update of the TRIM value.

[0004] Therefore, how to realize flexible adjustment of the working parameters of the chip and ensure the availability of the chip is a technical problem to be solved by those skilled in the art. SUMMARY

[0005] The embodiments of the application provide a multi-segment storage method, device and equipment of working parameters of a chip and a medium, which aims to support adjustment of the working parameters of the chip through construction of a multi-segment storage and address mapping mechanism, and meet the actual use requirements of the chip.

[0006] In a first aspect, the embodiments of the application provide a multi-segment storage method of working parameters of a chip, the chip is provided with a storage address indication area and at least two storage areas, each storage area is composed of a preset number of bytes; the method comprises:

[0007] When a target working parameter storage event is identified, reading a current value from the storage address indication area to determine a storage area of a current working parameter;

[0008] According to the storage area of the current working parameter, determining a starting address for storing the target working parameter;

[0009] According to the starting address and the preset number of bytes, determining a target storage area of the target working parameter, and writing the target working parameter into the target storage area;

[0010] Updating the current value in the storage address indication area.

[0011] Further, the method further comprises:

[0012] Obtaining an actual byte length of the working parameters of the chip;

[0013] According to the actual byte length, a preset number of bytes used for dividing the at least two storage areas is determined.

[0014] Further, a current value in the storage address indication area is read to determine the storage area of the current working parameter, including:

[0015] The number written as a target value is read from low bits to high bits in the storage address indication area to obtain the current value;

[0016] According to a pre-constructed mapping relationship, a storage area corresponding to the current value is analyzed to obtain the storage area of the current working parameter.

[0017] Further, the initial value of each bit of the storage address indication area is 0, and the target value is 1.

[0018] Further, the current value in the storage address indication area is updated, including:

[0019] The higher bit of the highest bit overwritten as the target value in the storage address indication area is overwritten as the target value from the initial value.

[0020] Further, the method further includes:

[0021] In the storage address indication area, the value on each bit is set to the initial value;

[0022] When the initial value on each bit is overwritten as the target value, a mapping relationship between the read value of the storage address indication area and the storage area is established.

[0023] Further, the method further includes:

[0024] When it is identified that the current value in the storage address indication area is updated to the maximum read value in the storage address indication area, the storage address indication area is expanded to obtain an expanded indication area;

[0025] A mapping relationship between the expanded indication area and a plurality of storage areas expanded from the expanded indication area is established.

[0026] In a second aspect, an embodiment of the present application provides a multi-segment storage device for working parameters of a chip, the chip being provided with a storage address indication area and at least two storage areas, each storage area being composed of a preset number of bytes; the device includes:

[0027] A current value reading module is configured to read a current value from the storage address indication area when a target working parameter storage event is identified, to determine a storage area of a current working parameter.

[0028] a storage start address determination module configured to determine a storage start address of the target working parameter according to a storage area of the current working parameter;

[0029] a target storage area determination module configured to determine a target storage area of the target working parameter according to the storage start address and the preset number of bytes, and write the target working parameter into the target storage area;

[0030] a current value update module configured to update a current value in the storage address indication area.

[0031] In a third aspect, an electronic device is provided, which includes a processor, a memory, and a program or instruction stored in the memory and executable in the processor, and the program or instruction, when executed by the processor, implements the steps of the method according to the first aspect.

[0032] In a fourth aspect, a readable storage medium is provided, which stores a program or instruction, and the program or instruction, when executed by a processor, implements the steps of the method according to the first aspect.

[0033] In a fifth aspect, a chip is provided, which includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to execute a program or instruction to implement the method according to the first aspect.

[0034] In the embodiments of the present application, when a target working parameter storage event is identified, a current value is read from the storage address indication area to determine a storage area of a current working parameter; a storage start address of the target working parameter is determined according to the storage area of the current working parameter; a target storage area of the target working parameter is determined according to the storage start address and the preset number of bytes, and the target working parameter is written into the target storage area; and the current value in the storage address indication area is updated. The construction of the multi-segment storage and address mapping mechanism can make the working parameters of the chip support adjustment and meet the actual use requirements of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a flowchart of a working parameter multi-segment storage method of a chip provided by the embodiments of the present application;

[0036] Figure 2 is a schematic diagram of TRIM value storage provided by the embodiments of the present application;

[0037] Figure 3 is a structural schematic diagram of a working parameter multi-segment storage device of a chip provided by the embodiments of the present application;

[0038] Figure 4 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the purposes, technical solutions and advantages of the present application clearer, the specific embodiments of the present application are described in further detail below in combination with the drawings. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only parts related to the present application are shown in the drawings, but not all contents. Before discussing the example embodiments in more detail, it should be mentioned that some example embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the operations (or steps) as sequential processes, many of the operations can be implemented in parallel, concurrently or simultaneously. In addition, the order of the operations can be rearranged. The processes can be terminated when the operations are completed, but can also have additional steps not included in the drawings. The processes can correspond to methods, functions, procedures, subroutines, subprograms, etc.

[0040] The technical solutions in the embodiments of the present application will be described clearly in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present application.

[0041] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of a kind, and are not limited to the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / ", generally represents that the front and rear associated objects are in an "or" relationship.

[0042] The working parameter multi-section storage method, device, equipment and medium of the chip provided by the embodiments of the present application will be described in detail below in combination with the drawings, through specific embodiments and application scenarios.

[0043] Figure 1 is a flowchart of a working parameter multi-section storage method of a chip provided by an embodiment of the present application.

[0044] The chip is provided with a storage address indication area and at least two storage areas, and each storage area is composed of a preset number of bytes. Figure 1 As shown, the method specifically comprises the following steps:

[0045] S101, when a target working parameter storage event is identified, reading a current value from the storage address indication area to determine a storage area of a current working parameter;

[0046] The internal part of the chip can be divided into a storage address indication area and a plurality of storage areas, and each storage area can be used to store a working parameter. For example, when a working parameter iteration is required, the updated working parameter can be stored in the next storage area of the current storage area, and the updated working parameter is used to update the working parameter of the chip.

[0047] In this scheme, the target working parameter storage event can be identified when a target parameter storage request is identified. For example, when a staff member queries the current working parameter storage area of the chip through a tool and applies for storage of a new target working parameter, it can be determined that there is a target working parameter storage event.

[0048] The current value in the storage address indication area is associated with the storage area of the current working parameter. According to the association relationship and the size of the current value, the storage area of the current working parameter can be determined, and the next area of the area is used as the storage area of the target working parameter.

[0049] The association rule used to determine the storage area of the current working parameter can be preset. For example, when the chip is manufactured or first used, the storage location of the TRIM value is indicated by the first storage address. The 0x1000 address is used as the storage address indication area, and the initial value is 0. When first used, the address is written as 1. The programmer writes the TRIM value into the area starting from the 0x1020 address with a size of 4 bytes according to the byte information. That is, the data 1 in the 0x1000 address corresponds to the TRIM value in the 0x1020 address. That is, when the current value is 1, the area starting from the 0x1020 address with a size of 4 bytes is determined as the storage area of the current working parameter. The 4 bytes are the preset number of bytes.

[0050] S102, according to the storage area of the current working parameter, determining a starting address for storing the target working parameter;

[0051] After determining the storage area of the current working parameter, the starting address of the next storage area can be determined according to the starting position and the preset number of bytes.

[0052] Specifically, each time a new TRIM value is stored, the system checks the indication area of the storage unit to determine where to store the new data. It first checks from the low bit to see if it is 1, and then proceeds to the high bit, until a 0 is detected, and then the bit is modified to 1. For example, reading the 0x1000 address, if only bit0 in the data is 1, and bits 1 and above are 0, it indicates that the current TRIM value is stored at the 0x1020 address, and the target working parameter needs to be stored backward to 0x1024, and the data bit1 in the 0x1000 address needs to be changed from 0 to 1.

[0053] S103, determining a target storage area of the target working parameter according to the starting address and the preset number of bytes, and writing the target working parameter into the target storage area;

[0054] After obtaining the starting address of the target working parameter, the entire target storage area for storing the target working parameter can be determined according to the starting address and the preset number of bytes.

[0055] After determining the target storage area, the target working parameter can be written into the target storage area.

[0056] In this embodiment, optionally, the current value is read from the storage address indication area to determine the storage area of the current working parameter, including:

[0057] The number of bits written as the target value is read from the low bit to the high bit in the storage address indication area to obtain the current value.

[0058] According to the pre-constructed mapping relationship, the storage area corresponding to the current value is analyzed to obtain the storage area of the current working parameter.

[0059] Among them, the writing of the value of the storage address indication area can be in the order from low to high, for example, after a working parameter is stored into the first storage area, the lowest bit of the storage address indication area, i.e. bit0, is rewritten from the default value to the target value, when another working parameter is stored into the second storage area, bit1 of the storage address indication area is rewritten from the default value to the target value, when again a working parameter is stored into the third storage area, bit2 of the storage address indication area is rewritten from the default value to the target value, and so on.

[0060] Because the value on different bits changes after the initial value is written to the target value, the read value of the storage address indication area changes. The association between the read value and the storage area can be constructed in advance, so that the corresponding storage area is determined based on the current value, that is, the storage area of the current working parameter is obtained. For example, if the data in the 0x1000 address is only bit0 is 1, and bits above bit1 are 0, it indicates that the current TRIM value is stored in the 0x1020 address, and the newly added TRIM value needs to be stored to 0x1024, and the data bit1 in the 0x1000 address needs to be changed from 0 to 1, that is, 0x03 needs to be written to the 0x1000 address. Similarly, if the data in the 0x1000 address is 0x03, bit2 needs to be changed from 0 to 1, that is, 0x07 needs to be written to the 0x1000 address, which indicates that the TRIM value is stored in the 0x1028 address, that is, the current TRIM value to be written is written to the 0x1028 storage area.

[0061] Through such a setting, the storage area corresponding to the current value can be accurately parsed, and the storage area is used as the basis for determining the target storage area of the target working parameter, thereby improving the flexible adjustment capability of the target working parameter of the chip.

[0062] In this embodiment, optionally, the initial value of each bit of the storage address indication area is 0, and the target value is 1.

[0063] In this scheme, for the storage address indication area, the initial value of each bit can be 0, and the target value after rewriting can be 1. In this way, the number of bits where the number 1 is located can be used to determine the read value, and the association between the read value and the storage area is established based on this.

[0064] Through such a setting, the association between the read value in the storage address indication area and the storage area can be better obtained, the ordered storage of the target parameter is ensured, and the situation that the target parameter storage area has an intersection caused by parsing errors is avoided.

[0065] In this embodiment, optionally, the current value in the storage address indication area is updated, including:

[0066] The higher bit of the highest bit rewritten to the target value in the storage address indication area is rewritten from the initial value to the target value.

[0067] In the present scheme, after the target working parameter is stored in the target storage area, the storage address indication area can be adjusted correspondingly, so that the read value of the storage address indication area can correspond to the target storage position of the target working parameter being used. Specifically, the higher bit of the highest bit of the target value in the storage address indication area can be rewritten from the initial value to the target value.

[0068] Through the above arrangement, the read value of the storage address indication area can accurately correspond to the current target storage area through a simple rewriting operation.

[0069] S104, updating the current value in the storage address indication area.

[0070] It can be understood that after the target working parameter, such as a new TRIM value, is written to the target storage area, the current value in the storage address indication area needs to be updated. As described in the above example, after the target working parameter is stored in 0x1024, the data bit1 in 0x1000 address needs to be changed from 0 to 1.

[0071] It should be noted that updating the current value in the storage address indication area before writing the target working parameter to the target storage area is also feasible. The updating of the current value and the writing of the target working parameter can be regarded as one process, and the execution order of the two does not have actual difference. As long as the storage and updating can be completed, the position where the target working parameter is stored can be determined according to the value in the storage address indication area.

[0072] In the present embodiment, optionally, the method further comprises:

[0073] obtaining the actual byte length of the working parameter of the chip;

[0074] determining the preset number of bytes for dividing at least two storage areas according to the actual byte length.

[0075] In the present scheme, the actual byte length of different working parameters is different, and the byte length of each storage area, i.e. the preset number of bytes, can be determined according to the storage requirement of the working parameter.

[0076] In the scheme, taking the TRIM value as an example, each storage area of the chip is divided into several small segments, and each small segment stores a TRIM value. The scheme can determine the preset number of bytes according to the size of the specific TRIM value. Assuming that each TRIM value occupies 4 bytes, each storage area is composed of 4 bytes, and each storage area is used to store a complete TRIM value. If a TRIM value needs to store more information, each TRIM value can be expanded to multiple storage areas to store more bytes.

[0077] Through such a setting, the flexibility of setting the storage area can be improved, and the size of each storage area can be set according to actual needs, avoiding waste of storage space and avoiding the case that each storage area cannot store complete working parameters.

[0078] In one embodiment, optionally, the method further comprises:

[0079] In the storage address indication area, the value of each bit is set to an initial value;

[0080] When the initial value of each bit is overwritten with a target value, the mapping relationship between the read value of the storage address indication area and the storage area is established.

[0081] In the scheme, the content of the storage unit of the storage address indication byte identifies the starting address of the actual storage TRIM value storage unit through the address mapping relationship. When storing the TRIM value, the programmer determines the next available storage position by reading the information of the indication bit.

[0082] When the TRIM value needs to be updated, the system jumps to the next free storage area according to the information of the indication bit and updates the corresponding TRIM value.

[0083] For the establishment of the mapping mechanism, the following processes can be divided:

[0084] Initial programming, that is, when the chip is shipped or first used, the storage position of the TRIM value is indicated by the first storage address. Assuming that the maximum update number of the stored TRIM value does not exceed 32 times, only 4 bytes of address need to be stored, for example: 0x1000. The initial value of the 0x1000 address is 0, and the address is written to 1 when first used. The programmer writes the TRIM value to the specified storage area according to the byte information. Assuming that each TRIM value occupies 4 bytes, for example: starting from the 0x1020 address, that is, the data 1 in the 0x1000 address corresponds to the TRIM value in the 0x1020 address.

[0085] The storage updates, each time a new TRIM value is stored, the system checks the indication area of the storage unit to determine where to store the new data. First, check if it is 1 from the low bit, and then to the high bit, until a 0 is detected, and then modify the bit to 1. For example, read the 0x1000 address, if the data is only bit0 is 1, and bit1 above is 0, it means that the current TRIM value is stored in the 0x1020 address, and the new TRIM value needs to be stored to 0x1024, and the data bit1 in the 0x1000 address needs to be changed from 0 to 1, that is, 0x03 needs to be written to the 0x1000 address. Similarly, if the data in the 0x1000 address is 0x03, bit2 needs to be changed from 0 to 1, that is, 0x07 needs to be written to the 0x1000 address, which indicates that the TRIM value is stored in the 0x1028 address. The storage position of the TRIM value is dynamically adjusted by the increment of 1 in the indication area of the storage unit.

[0086] The present scheme can determine the storage area of the currently used working parameter by reading the value in the storage address indication area through the establishment of the mapping mechanism, and can realize precise control of reading, updating and other operations of the working parameter.

[0087] In one embodiment, optionally, the method further comprises:

[0088] When the current value in the storage address indication area is updated to the maximum reading in the storage address indication area, the storage address indication area is expanded to obtain an expanded indication area;

[0089] The mapping relationship between the expanded indication area and the plurality of storage areas obtained by expansion is established.

[0090] In the present scheme, when the current value is updated to the maximum reading in the storage address indication area, the storage address indication area needs to be expanded.

[0091] In combination with the above example, when the maximum update times of the stored TRIM value exceed 32 times, the address storage area can use more continuous address storage areas for storage, and at the same time, the actual storage TRIM value area address will also be incremented in turn, for example, when the maximum update times of the stored TRIM value do not exceed 128 times, and the starting address is 0x1000, 0x1000-0x100F, 16 bytes, can be used for storage.

[0092] It can be understood that while the storage address indication area is expanded, the storage area can also continue to expand in turn to obtain more storage areas to be able to store more TRIM values.

[0093] This solution, through this setting, can expand the storage address indicator area when the number of updates to the operating parameters reaches or exceeds the maximum number that the storage address indicator area can record, thereby obtaining the function of recording more update times and ensuring the normal updating of the chip's operating parameters.

[0094] The technical solution provided in this embodiment, upon detecting a target operating parameter storage event, reads the current value from the storage address indication area to determine the storage area of ​​the current operating parameter; determines the starting address for storing the target operating parameter based on the storage area of ​​the current operating parameter; determines the target storage area of ​​the target operating parameter based on the starting address and the preset number of bytes, and writes the target operating parameter into the target storage area; and updates the current value in the storage address indication area. This technical solution, with its multi-segment storage and address mapping mechanism, enables the chip's operating parameters to be adjusted, meeting the actual usage requirements of the chip.

[0095] Figure 2 This is a schematic diagram of TRIM value storage provided in an embodiment of this application. For example... Figure 2 As shown: Storage Structure Design: The OTP chip's storage structure adopts a segmented storage method, dividing the storage area into an address storage indicator area and a TRIM value storage area. The address storage indicator area is used to record the status of the current storage location, and the address of the subsequent storage unit is used to store the TRIM value. The specific design is as follows:

[0096] The TRIM value storage area of ​​the chip is divided into several segments, each storing one TRIM value. Assume each TRIM value occupies 4 bytes. Each storage unit consists of 4 bytes, storing a complete TRIM value. If a TRIM value needs to store more information, each TRIM value can be expanded into multiple storage units, storing multiple bytes.

[0097] The storage address indicator area is used to record and retrieve the location where a new TRIM value should be stored, and it is located before the TRIM value storage area.

[0098] The storage address indicator area specifically identifies the starting address of the actual storage unit for the TRIM value, based on the address mapping relationship. When storing the TRIM value, the programmer determines the next available storage location by reading the information from this indicator bit.

[0099] When a TRIM value needs to be updated, the system will jump to the next free storage area based on the information in the indicator bit and update the corresponding TRIM value.

[0100] Address mapping mechanisms can be used to support storing and updating multiple TRIM values. The mechanism works as follows:

[0101] Initial programming, the storage location of TRIM value is indicated by the first storage address when the chip is shipped or first used. Assuming that the maximum update times of the stored TRIM value is not more than 32, only 4 bytes of address are needed to store, for example: 0x1000. The initial value of 0x1000 address is 0, and the address is written as 1 when first used. The programmer writes the TRIM value into the specified storage area according to the byte information. Assuming that each TRIM value occupies 4 bytes, for example: starting from 0x1020 address, that is, the data 1 in 0x1000 address corresponds to the TRIM value in 0x1020 address.

[0102] Storage update, each time a new TRIM value is stored, the system will check the indication area of the storage unit to determine where to store the new data. First, check from the low bit to see if it is 1, and then go to the high bit, until 0 is detected, and then modify the bit to 1. For example: read the 0x1000 address, if only bit0 in the data is 1, and bits above bit1 are 0, it indicates that the current TRIM value is stored in 0x1020 address, and the new TRIM value needs to be stored to 0x1024, and the data bit1 in 0x1000 address needs to be changed from 0 to 1, that is, 0x03 needs to be written to 0x1000 address. Similarly, if the data in 0x1000 address is 0x03, bit2 needs to be changed from 0 to 1, that is, 0x07 needs to be written to 0x1000 address, which indicates that the TRIM value is stored in 0x1028 address. The storage location of the TRIM value is dynamically adjusted by the increment of 1 in the indication area of the storage unit.

[0103] Storage times dynamic processing, when the maximum update times of the stored TRIM value exceeds 32, the address storage area can use more continuous address storage area for storage, at the same time, the actual storage TRIM value area address will also be incremented in turn, for example, when the maximum update times of the stored TRIM value is not more than 128, the starting address is 0x1000, 0x1000-0x100F, that is, 16 bytes, can be used for storage.

[0104] The programming process of the TRIM value includes the following steps:

[0105] Read the current storage location;

[0106] First, the programmer reads the first location of the chip (i.e. the storage address indication area) to indicate the starting address of the current storage area.

[0107] Store the TRIM value;

[0108] According to the indication byte information, the programmer writes the TRIM value to the specified storage area. Each TRIM value storage unit is composed of 4 bytes (or expand the number of bytes as needed), and the programmer writes data byte by byte.

[0109] The reading process of the TRIM value is similar to the programming process. The user obtains the TRIM value by reading the data in the storage area. The specific steps are as follows:

[0110] Read the indication byte, read the bytes of the storage area, and determine the TRIM value storage location.

[0111] Read the TRIM value, and according to the storage location, extract the TRIM value from the corresponding storage unit.

[0112] Since the patent scheme adopts an address mapping mechanism, it has high flexibility and can store multiple TRIM values as needed. The storage area of the chip can be expanded according to actual needs:

[0113] Dynamic expansion: The expansion of the storage area is dynamic each time it is programmed, and there is no need to fix the storage capacity at the time of chip design.

[0114] TRIM value update: The TRIM value can be updated at different times and under different conditions. The updated value will be stored in a new address without overwriting the previous TRIM value. This allows the system to make multiple adjustments according to environmental changes or different working parameters.

[0115] The invention can also be flexibly configured according to different application requirements, such as storing different TRIM values, storing different parameter values, and adjusting the storage location.

[0116] The storage method of the invention breaks through the limitation of the traditional OTP chip that can only write the TRIM value once at the factory, and realizes multiple writing, providing a more optimal solution for the practicality of OTP chips.

[0117] Suppose there is an initial configuration as follows:

[0118] Address 0x1000: Address indication storage bit;

[0119] Address 0x1004: Address indication storage bit (if the number of TRIM values to be stored exceeds 32, this address is used);

[0120] Address 0x1020: TRIM value storage start address (the start address and offset can be customized as needed);

[0121] When the TRIM value needs to be updated, the program first checks whether the address 0x1000 is empty, i.e. does not point to other places. If yes, the new TRIM data is written starting from the start address of the storage unit, and 0x1000 is set to 0b00000000-00000000-00000000-00000001, which points to the corresponding storage area according to the address offset relationship; otherwise, the number of address indicating areas 1 is determined to determine the address offset, and the latest TRIM value is read.

[0122] The technical scheme introduces a flexible address mapping mechanism, so that even on the non-rewritable OTP medium, multiple versions of TRIM data can be effectively managed and updated, and the practicability of the OTP chip is increased.

[0123] Figure 3 is a structural schematic diagram of a multi-segment storage device for working parameters of a chip provided by the embodiment of the present application; as shown in the figure, the chip is provided with a storage address indicating area and at least two storage areas, each storage area is composed of a preset number of bytes; the device comprises: Figure 3

[0124] a current value reading module 301 for reading the current value from the storage address indicating area when a target working parameter storage event is identified, to determine the storage area of the current working parameter;

[0125] a storage start address determining module 302 for determining the start address for storing the target working parameter according to the storage area of the current working parameter;

[0126] a target storage area determining module 303 for determining the target storage area of the target working parameter according to the start address and the preset number of bytes, and writing the target working parameter into the target storage area;

[0127] a current value updating module 304 for updating the current value in the storage address indicating area.

[0128] The technical scheme provided by the embodiment, when a target working parameter storage event is identified, the current value is read from the storage address indicating area to determine the storage area of the current working parameter; the start address for storing the target working parameter is determined according to the storage area of the current working parameter; the target storage area of the target working parameter is determined according to the start address and the preset number of bytes, and the target working parameter is written into the target storage area; the current value in the storage address indicating area is updated. The construction of the multi-segment storage and the address mapping mechanism can make the working parameters of the chip support adjustment, and meet the actual use requirements of the chip. ​

[0129] The chip working parameter multi-section storage device in the embodiments of the present application can be a device, or a component, an integrated circuit, or a chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. Exemplarily, the mobile electronic device can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), etc., and the non-mobile electronic device can be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine, etc., and the embodiments of the present application are not limited in this regard.

[0130] The chip working parameter multi-section storage device in the embodiments of the present application can be a device with an operating system. The operating system can be an Android operating system, an iOS operating system, or other possible operating systems, and the embodiments of the present application are not limited in this regard.

[0131] The chip working parameter multi-section storage device provided in the embodiments of the present application can implement the processes implemented by the method embodiments, and thus repeated descriptions are not given herein.

[0132] Figure 4 FIG. 1 is a structural schematic diagram of an electronic device provided in the embodiments of the present application. As shown in FIG. 1, the electronic device 100 provided in the embodiments of the present application includes a chip 101. Figure 4 The embodiments of the present application also provide an electronic device 400, which includes a processor 401, a memory 402, and a program or instruction stored in the memory 402 and executable in the processor 401. The program or instruction is executed by the processor 401 to implement the processes of the chip working parameter multi-section storage device embodiments and achieve the same technical effects, and thus repeated descriptions are not given herein.

[0133] It should be noted that the electronic device in the embodiments of the present application includes the mobile electronic device and the non-mobile electronic device.

[0134] The embodiments of the present application also provide a readable storage medium, which stores a program or instruction executable by a processor to implement the processes of the chip working parameter multi-section storage device embodiments and achieve the same technical effects, and thus repeated descriptions are not given herein.

[0135] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0136] The chip provided in the embodiments of the present application also includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is configured to run programs or instructions, implement various processes of the working parameter multi-section storage device embodiments of the chip, and achieve the same technical effects. To avoid repetition, details are not described herein.

[0137] It should be understood that the chip mentioned in the embodiments of the present application can also be referred to as a system-level chip, a system chip, a chip system, or a system-on-chip, etc.

[0138] It should be noted that in this document, the term "comprising" or "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to the order of performing the functions as shown or discussed, but can also include performing the functions in a substantially simultaneous manner or in reverse order, for example, the described method can be performed in an order different from that described, and various steps can also be added, omitted or combined. In addition, the features described with reference to some examples can be combined in other examples.

[0139] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a plurality of instructions for making a terminal (which can be a mobile phone, computer, server, or network equipment, etc.) execute the method described in each embodiment of the present application.

[0140] The embodiments of the present application are described above with reference to the drawings, but the present application is not limited to the specific embodiments described above, and the specific embodiments described above are merely illustrative, but not restrictive, and those of ordinary skill in the art can make many forms without departing from the purpose of the present application and the scope protected by the claims under the inspiration of the present application, which all belong to the protection of the present application.

[0141] The above are only the preferred embodiments of the present application and the technical principles used. The present application is not limited to the specific embodiments described herein, and various obvious changes, re-adjustments and replacements made by those skilled in the art will not deviate from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and more other equivalent embodiments can be included without departing from the concept of the present application, and the scope of the present application is determined by the scope of the claims.

Claims

1. A method for multi-segment storage of operating parameters of a chip, characterized in that, The chip is provided with a storage address indication area and at least two storage areas, each of which is composed of a preset number of bytes; the method comprises: When a target working parameter storage event is identified, a current value is read from the storage address indication area to determine the storage area of the current working parameter, and the reading of the current value from the storage address indication area to determine the storage area of the current working parameter comprises: reading the number written as a target value from low bits to high bits in the storage address indication area to obtain a current value, and analyzing the storage area corresponding to the current value according to a pre-constructed mapping relationship to obtain the storage area of the current working parameter; According to the storage area of the current working parameter, the starting address for storing the target working parameter is determined; According to the starting address and the preset number of bytes, the target storage area of the target working parameter is determined, and the target working parameter is written into the target storage area; The current value in the storage address indication area is updated.

2. The method for multi-segment storage of chip operating parameters according to claim 1, characterized in that, The method further comprises: Obtaining the actual byte length of the working parameter of the chip; According to the actual byte length, the preset number of bytes for dividing at least two storage areas is determined.

3. The method of claim 1, wherein the plurality of segments are stored in a memory of the chip. The initial value of each bit of the storage address indication area is 0, and the target value is 1.

4. The method of claim 1, wherein the plurality of segments are stored in a memory of the chip. Updating the current value in the storage address indication area comprises: The higher bit of the highest bit rewritten as a target value in the storage address indication area is rewritten as a target value.

5. The method of claim 1, wherein the plurality of segments are stored in a memory of the chip. The method further comprises: In the storage address indication area, the value on each bit is set to an initial value; When the initial value on each bit is rewritten as a target value, the mapping relationship between the read value of the storage address indication area and the storage area is established.

6. The method of claim 1, wherein the plurality of segments are stored in a memory of the chip. The method further comprises: When the current value in the storage address indication area is updated to the maximum reading in the storage address indication area, the storage address indication area is expanded to obtain an expanded indication area; The mapping relationship between the expanded indication area and the plurality of storage areas expanded is established.

7. A multi-segment storage device for operating parameters of a chip, characterized in that The chip is provided with a storage address indication area and at least two storage areas, each of which is composed of a preset number of bytes; the device comprises: A current value reading module is configured to read a current value from the storage address indication area to determine the storage area of the current working parameter when a target working parameter storage event is identified, and the current value reading module is specifically configured to read the number written as a target value from low bits to high bits in the storage address indication area to obtain a current value, and analyze the storage area corresponding to the current value according to a pre-constructed mapping relationship to obtain the storage area of the current working parameter; A storage starting address determination module is configured to determine the starting address for storing the target working parameter according to the storage area of the current working parameter; A target storage area determination module is configured to determine the target storage area of the target working parameter according to the starting address and the preset number of bytes, and write the target working parameter into the target storage area; A current value updating module is configured to update the current value in the storage address indication area.

8. An electronic device, comprising: The chip comprises a processor, a memory, and a program or instruction stored in the memory and executable on the processor, and the program or instruction is used to implement the steps of the multi-section storage method of the working parameters of the chip according to any one of claims 1-6.

9. A readable storage medium, characterized by, The program or instruction is stored in the readable storage medium, and the program or instruction is used to implement the steps of the multi-section storage method of the working parameters of the chip according to any one of claims 1-6.

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