A control method and device for an approximate adder circuit based on a memristor

Abstract

The invention discloses a control method of an approximate adder circuit based on a memristor and an approximate adder device, belonging to the technical field of microelectronic devices; wherein the approximate adder circuit only includes 2n+1 memristors and one resistor, the invention divides the approximate addition process of two n-bit numbers into initialization and n rounds of approximate addition sub-processes, and makes each round of approximate addition sub-process perform a 1-bit approximate addition operation; in each round of approximate addition sub-process, the corresponding first, second and third memristors are selected, and only three operations of setting the first and second memristors and applying pressure to each memristor and resistor are required to realize the 1-bit approximate addition operation, so that the actual operation steps required for the entire approximate addition are only 2n+1 steps; compared with the existing n-bit approximate adder, the approximate addition operation can be realized with higher calculation accuracy under the condition of using fewer devices and operation steps.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic devices, and more specifically, relates to a control method of an approximate adder circuit based on a memristor and an approximate adder device. Background Art

[0002] With the rapid development of artificial intelligence and big data technologies, high-performance computing has put forward higher energy efficiency and performance requirements for hardware systems. Due to the separation of storage and computing units in the traditional von Neumann architecture, frequent data movement causes the system to face problems such as "storage wall" and "power consumption wall", which seriously limits the improvement of computing efficiency. In-memory computing technology greatly reduces the delay and energy consumption caused by data transmission by directly performing computing operations in the storage unit, and has become an important research direction to break through the bottleneck of traditional computing architecture. As a new type of non-volatile memory, memristor has great application potential due to its high density, low power consumption and compatibility with CMOS process. Memristor can not only be used to store data, but also realize logical computing functions through its resistive switching characteristics.

[0003] Approximate adders are widely used in image processing, artificial intelligence, signal processing and other fields as a design that can optimize performance while tolerating certain computational errors. The core idea is to reduce power consumption, shorten computational delays and reduce chip area by simplifying the circuit structure at the expense of some accuracy. In particular, image processing tasks such as edge detection, image compression and filtering operations require relatively low computational accuracy, so approximate adders can achieve efficient data processing with low resource consumption.

[0004] The design of the approximate adder based on memristors provides a new hardware solution by combining the advantages of in-memory computing and the flexibility of approximate computing. However, the existing memristor-based approximate adder is implemented based on the Essential Implied Logic (IMPLY) logic. Although the approximate Boolean logic expression is relatively simple, it sacrifices high calculation accuracy. Therefore, the calculation accuracy of the proposed approximate algorithm needs to be further improved. At the same time, it is limited by the inefficient logic synthesis capability of IMPLY logic, and the number of devices and operation steps required are relatively large. Summary of the invention

[0005] In view of the above defects or improvement needs of the prior art, the present invention provides a control method and an approximate adder device of an approximate adder circuit based on a memristor, which are used to solve the technical problem that the prior art cannot realize approximate addition operations with higher calculation accuracy under the condition of using fewer devices and operation steps.

[0006] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a control method of an approximate adder circuit based on a memristor, for realizing an n-bit number an ......a 2 a 1 With b n ......b 2 b 1 Approximate addition; wherein the approximate adder circuit comprises: a resistor and 2n+1 identical memristors; the negative electrode of each memristor is connected to the same source line SL; one end of the source line SL is suspended, and the other end is connected to one end of the resistor; n≥1;

[0007] The above control method includes:

[0008] Select n memristors from 2n+1 memristors and write logic value a into each of them 1 ~ a n ; Select a memristor from the remaining memristors and write the input carry c 1 ; The remaining memristors without set values ​​are all set to high impedance state;

[0009] Execute n rounds of approximate addition sub-processes in sequence;

[0010] In the i-th round of approximate addition subprocess, the following operations are performed:

[0011] In the first time period, the logic value a will be written i The memristor is used as the first memristor, and a voltage -V is applied to its positive terminal; the stored carry c i The memristor with a value set is used as the second memristor, and its positive electrode is left floating; a memristor is selected from the unset memristors as the third memristor, and a voltage V is applied to its positive electrode. P ; Apply a voltage with an amplitude of 0 to the other end of the resistor; At this time, a carry is obtained in the third memristor ;

[0012] In a second time period after the first time period, a voltage VV is applied to the positive electrode of the first memristor. P ; Apply voltage V to the positive electrode of the second memristor P ; Float the positive electrode of the third memristor; Apply a voltage of -V to the other end of the resistor; At this time, the summation result is obtained in the second memristor ;

[0013] Where i=1,2,...,n; when the logical value b i When the logic value is 0, V is 0; when the logic value is b i When it is 1, V is V P ; V P Meet V set / 2 <V P <V set , and V P <2|Vreset |;V set V is the threshold value of the memristor changing from high resistance state to low resistance state; reset is the threshold value of the memristor changing from a low resistance state to a high resistance state;

[0014] s n ......s 2 s 1 and c n+1 This is the desired n-bit number a n ......a 2 a 1 With b n ......b 2 b 1 The approximate addition result of .

[0015] In a second aspect, the present invention provides an approximate adder device for implementing an n-bit number a n ......a 2 a 1 With b n ......b 2 b 1 Approximate addition, comprising: an approximate adder circuit and a control module;

[0016] The approximate adder circuit includes: a resistor and 2n+1 identical memristors; the negative electrodes of each memristor are connected to the same source line SL; one end of the source line SL is suspended, and the other end is connected to one end of the resistor; n≥1;

[0017] The control module is used to execute the control method provided by the first aspect of the present invention.

[0018] Further preferably, the resistance value of the resistor is between the high resistance state resistance value and the low resistance state resistance value of the memristor.

[0019] Further preferably, the resistance value of the resistor ; Among them, R H is the high-resistance resistance of the memristor, R L is the low-resistance state resistance value of the memristor.

[0020] Further preferably, the above memristors include a high resistance state and a low resistance state, the high resistance state corresponds to a logic value "0", and the low resistance state corresponds to a logic value "1".

[0021] In a third aspect, the present invention provides a control system, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor executes the control method provided in the first aspect of the present invention when executing the computer program.

[0022] In a fourth aspect, the present invention further provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method provided in the first aspect of the present invention.

[0023] In a fifth aspect, the invention further provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the control method provided in the first aspect of the invention.

[0024] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

[0025] 1. The first aspect of the present invention provides a control method for an approximate adder circuit based on a memristor, for realizing two n-bit numbers a n ......a 2 a 1 With b n ......b 2 b 1 The approximate addition of the summation result s n ......s 2 s 1 and carry out c n+1 The controlled approximate adder circuit includes only 2n+1 memristors and one resistor, and the n-bit approximate addition process is divided into initialization and n rounds of approximate addition sub-processes, and each round of approximate addition sub-process performs a 1-bit approximate addition operation; wherein, in each round of approximate addition sub-process, the first memristor, the second memristor and the third memristor are selected, and the logic value a i Defined as the resistance state of the first memristor, the logic value c i Defined as the resistance state of the second memristor, logic value b i The voltage input terminal of the first memristor and the source line SL is defined in the form of voltage, and the resistance states of the second memristor and the third memristor are used as outputs. Only three operations are required, namely, setting the states of the first memristor and the second memristor and applying voltage to the memristor and the resistor, to realize the 1-bit approximate addition operation, so that the actual operation steps required for the entire approximate adder circuit are only 2n+1 steps; and for the 1-bit approximate addition operation, calculation errors occur only in two input cases, and the approximate error is small; compared with the existing n-bit approximate adder, the present invention can realize the approximate addition operation with higher calculation accuracy under the condition of using fewer devices and operation steps.

[0026] 2. The second aspect of the present invention provides an approximate adder device, comprising: an approximate adder circuit and a control module; wherein the approximate adder circuit only comprises 2n+1 memristors and one resistor, and the control module controls the approximate adder circuit through the control method provided by the first aspect of the present invention to realize two n-bit numbers a n ......a 2 a 1 and b n ......b 2 b 1 The approximate addition can significantly improve the calculation accuracy of the approximate addition operation while reducing the number of devices and operation steps. At the same time, the present invention also realizes a circuit layout with low complexity and small area with a simple structure, which has significant advantages in high-density integrated applications.

[0027] 3. The approximate adder device provided by the present invention makes full use of the non-volatile characteristics of the memristor. After the approximate addition operation is completed, the result is directly stored in the memristor, eliminating additional data transmission and storage steps, significantly optimizing energy consumption performance and shortening operation delay.

[0028] 4. Furthermore, in the approximate adder device provided by the present invention, the resistance value of the resistor is , in order to better distinguish the low resistance state, high resistance state and resistance value of the memristor, further improving the reliability of the calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the structure of a 1-bit approximate adder device provided in Embodiment 1 of the present invention.

[0030] Figure 2 A schematic diagram of the structure of an n-bit approximate adder device provided in Embodiment 2 of the present invention.

[0031] Figure 3 This is a schematic diagram of the structure of a 4-bit serial approximate adder device provided in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0033] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a control method of an approximate adder circuit based on a memristor, for realizing an n-bit number an ......a 2 a 1 With b n ......b 2 b 1 Approximate addition; wherein the approximate adder circuit comprises: a resistor and 2n+1 identical memristors; the negative electrode of each memristor is connected to the same source line SL; one end of the source line SL is suspended, and the other end is connected to one end of the resistor; n≥1;

[0034] The above control method includes:

[0035] Select n memristors from 2n+1 memristors and write logic value a into each of them 1 ~ a n ; Select a memristor from the remaining memristors and write the input carry c 1 ; The remaining memristors without set values ​​are all set to high impedance state;

[0036] Execute n rounds of approximate addition sub-processes in sequence;

[0037] In the i-th round of approximate addition subprocess, the following operations are performed:

[0038] In the first time period, the logic value a will be written i The memristor is used as the first memristor, and a voltage -V is applied to its positive terminal; the stored carry c i The memristor with a value set is used as the second memristor, and its positive electrode is left floating; a memristor is selected from the unset memristors as the third memristor, and a voltage V is applied to its positive electrode. P ; Apply a voltage with an amplitude of 0 to the other end of the resistor; At this time, a carry is obtained in the third memristor ;

[0039] In a second time period after the first time period, a voltage VV is applied to the positive electrode of the first memristor. P ; Apply voltage V to the positive electrode of the second memristor P ; Float the positive electrode of the third memristor; Apply a voltage of -V to the other end of the resistor; At this time, the summation result is obtained in the second memristor ;

[0040] Where i=1,2,...,n; when the logical value b i When the logic value is 0, V is 0; when the logic value is b i When it is 1, V is V P ; V P Meet V set / 2 <V P <V set , and V P <2|Vreset |;V set V is the threshold value of the memristor changing from high resistance state to low resistance state; reset is the threshold value of the memristor changing from a low resistance state to a high resistance state;

[0041] s n ......s 2 s 1 and c n+1 This is the desired n-bit number a n ......a 2 a 1 With b n ......b 2 b 1 The approximate addition result of .

[0042] In a second aspect, the present invention provides an approximate adder device for implementing an n-bit number a n ......a 2 a 1 With b n ......b 2 b 1 Approximate addition, comprising: an approximate adder circuit and a control module;

[0043] The approximate adder circuit includes: a resistor and 2n+1 identical memristors; the negative electrodes of each memristor are connected to the same source line SL; one end of the source line SL is suspended, and the other end is connected to one end of the resistor; n≥1;

[0044] The control module is used to execute the control method provided by the first aspect of the present invention.

[0045] In an optional implementation manner, the resistance value of the resistor is between the high resistance state resistance value and the low resistance state resistance value of the memristor. ; Among them, R H is the high-resistance resistance of the memristor, R L is the low-resistance resistance value of the memristor.

[0046] In an optional implementation manner, the above-mentioned memristors all include a high resistance state and a low resistance state, the high resistance state corresponds to a logic value "0", and the low resistance state corresponds to a logic value "1".

[0047] The related technical solution is the same as the control method provided in the first aspect of the present invention, and will not be described in detail here.

[0048] In a third aspect, the present invention provides a control system, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor executes the control method provided in the first aspect of the present invention when executing the computer program.

[0049] The related technical solution is the same as the control method provided in the first aspect of the present invention, and will not be described in detail here.

[0050] In a fourth aspect, the present invention further provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method provided in the first aspect of the present invention.

[0051] The related technical solution is the same as the control method provided in the first aspect of the present invention, and will not be described in detail here.

[0052] In a fifth aspect, the invention further provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the control method provided in the first aspect of the invention.

[0053] The related technical solution is the same as the control method provided in the first aspect of the present invention, and will not be described in detail here.

[0054] In order to further illustrate the control method of the memristor-based approximate adder circuit and the corresponding approximate adder device provided by the present invention, the following is a detailed description in conjunction with specific embodiments:

[0055] Example 1

[0056] In this embodiment, n is set to 1, and a 1-bit approximate adder device is provided for calculating the value of the input logic value c. i 、a i , b i Perform approximate addition (to achieve logical value a i , Logic b i and input carry c i approximate addition of Figure 1 As shown, it includes: an approximate adder circuit and a control module; wherein the approximate adder circuit includes: a memristor M 1 、Memristor 2 、Memristor 3 and resistor (a fixed value resistor is used in this embodiment); memristor M 3 The initial state is high impedance state; the control module includes: controller 1 and controller 2.

[0057] The controller 1 is connected to the memristor M 1 、Memristor 2 and memristor M 3 The positive electrode of the memristor M 1 、Memristor 2 and memristor M 3The negative electrodes are all connected to the same source line SL; one end of the source line SL is suspended, and the other end is connected to the controller 2; the resistor is connected to the source line SL, one end of which is connected to the control end of the source line SL, and the other end is connected to the negative electrode of the memristor closest to the control end of the source line.

[0058] The controller 1 includes a control terminal BL 1 , control end BL 2 and control terminal BL 3 . Control terminal BL 1 With memristor M 1 The positive electrode is connected to the control terminal BL 2 With memristor M 2 The positive electrode is connected to the control terminal BL 3 With memristor M 3 When the controller 1 performs similar addition operation, it controls the positive electrode of the control terminal BL. 1 , control end BL 2 and control terminal BL 3 For memristor M 1 、Memristor 2 and memristor M 3 Apply a time-varying voltage V BL1 , voltage V BL2 and voltage V BL3 When the controller 2 performs similar addition operation, it applies a voltage V that varies with time to the source line SL. SL It should be noted that the above memristor M 1 、Memristor 2 and memristor M 3 They are exactly the same, both including high-impedance state and low-impedance state, the high-impedance state corresponds to the logic value "0", and the low-impedance state corresponds to the logic value "1".

[0059] The controller 1 is used to set the memristor M before performing the approximate addition operation. 1 Set to logical value a i The corresponding resistance state, memristor M 2 Set to logical value c i The corresponding resistance state, memristor M 3 is set to high impedance state; when performing similar addition operations, the memristor M 1 、Memristor 2 and memristor M 3 Apply a time-varying voltage V BL1 , voltage V BL2 and voltage V BL3 .

[0060] The controller 2 is used to keep the grounding before performing the approximate addition operation; when performing the approximate addition operation, a voltage V that varies with time is applied to the source line SL.SL .

[0061] Among them, the value of each control terminal input voltage is determined by the logic b i Specifically, the approximate addition calculation process includes a first time period and a second time period after the first time period; the voltage that changes with time is reflected in different values ​​in the first time period and the second time period. In the first time period, the voltage V BL1 The value is -V, the control terminal BL 2 Floating, voltage V BL3 The value is V P , voltage V SL The value is 0. In the second time period, the voltage V BL1 The value is VV P , voltage V BL2 The value is V P , control terminal BL 3 Floating, voltage V SL The value is -V; when the logical value b i When the logic value is 0, V is 0; when the logic value is b i When it is 1, V is V P ;

[0062] Since the electrical signals used in the approximate addition process are all voltage pulse signals, in order to prevent the memristor in the high-resistance state from changing to the low-resistance state when no operation is performed, at the same time, when 2V is added to both ends of the memristor P When the voltage drops, the memristor is guaranteed to change its resistance state, and the voltage V P The amplitude should be between V set / 2 and V set In addition, in order to prevent the memristor in the low-resistance state from changing to the high-resistance state when no operation is performed, V P <2|V reset |. Based on this, V P Need to meet V set / 2 <V P <V set , and V P <2|V reset |. V set V is the threshold value of the memristor changing from high resistance state to low resistance state; reset is the threshold value at which the memristor changes from a low-resistance state to a high-resistance state.

[0063] Furthermore, in order to clearly distinguish the low resistance state, high resistance state and resistance value of the memristor, a memristor with a switching ratio greater than or equal to a preset switching threshold is used. In this embodiment, the preset switching threshold value is 100. The resistance value of the resistor is between the high resistance state and the low resistance state of the memristor. Since the high resistance state and the low resistance state of the memristor are at different orders of magnitude, in order to further clearly distinguish the low resistance state, high resistance state and resistance value of the memristor, preferably, the resistance value of the resistor is , where R H is the high-resistance resistance of the memristor, R L is the resistance value of the low resistance state of the memristor. The fixed value resistor mainly plays the role of current limiting in this logic circuit; further, considering that the high resistance state and low resistance state of the memristor have a certain fluctuation range, the resistance value R can be selected to be slightly larger than The result provides better guarantee for the reliability of the circuit.

[0064] Specifically, the control method of the approximate adder circuit in the above-mentioned 1-bit approximate adder device is used to realize the logic value a i , Logic b i and input carry c i The approximate addition of the summation result s i and carry output c i+1 , including the following steps:

[0065] S1, the memristor M 1 Set to logical value a i The corresponding resistance state, memristor M 2 Set to logical value c i The corresponding resistance state, memristor M 3 Set to its initial state high impedance state;

[0066] S2. During the first time period of approximate addition, the memristor M 1 Applied voltage V BL1_1 = -V, control terminal BL 2 Floating, for memristor M 3 Applied voltage V BL3_1 = V P , apply voltage V to the source line SL_1 = 0; at this time, a carry is obtained in the third memristor ;

[0067] S3, in the second time period, the memristor M 1 Applied voltage V BL1_2 = VV P , for the memristor M 2 Applied voltage V BL2_2 = V P, control terminal BL 3 Floating, applying voltage V to the source line SL_2 = -V; at this time, the summation result is obtained in the second memristor ;

[0068] Among them, when the logical value b i When the logic value is 0, V is 0; when the logic value is b i When it is 1, V is V P ; V P Meet V set / 2 <V P <V set , and V P <2|V reset |;V set V is the threshold value of the memristor changing from high resistance state to low resistance state; reset is the threshold value at which the memristor changes from a low resistance state to a high resistance state.

[0069] It should be noted that the control method in the 1-bit approximate adder device provided in this embodiment only includes three actual operation steps. Table 1 shows the voltage configuration in each actual operation step under different logic inputs. Specifically, since the initial state of the memristor is a high impedance state when it is initially used, there is no need to control the memristor M. 3 Therefore, S1 only includes setting the memristor M 1 Set to logical value a i The corresponding resistance state and the memristor M 2 Set to logical value c i The corresponding resistance state operation corresponds to step 1 in Table 1; S2 and S3 implement a 1-bit approximate addition function by applying corresponding voltages, corresponding to steps 2 and 3 in Table 1.

[0070]

[0071] In order to make the technical solution and advantages of this embodiment more clear, this embodiment provides eight input conditions of a 1-bit approximate adder and the resistance changes measured in an actual circuit. In this embodiment, the resistance R is 10 kΩ, and the switching ratio of the memristor is greater than or equal to 100, so that the resistance values ​​of the low resistance state, high resistance state and fixed resistance R of the memristor can be clearly distinguished.

[0072] It should be noted that the two outputs of the precise full adder are expressed as and ; The present invention improves the calculation speed of approximate addition by simplifying the carry generation process while maintaining a certain accuracy. The proposed approximate addition scheme can be expressed as and .

[0073] Table 2 shows the operation truth table of a 1-bit approximate adder. It can be seen from the table that compared with the precise adder, the present invention only has calculation errors in two input conditions. The specific operation and memristor state are as follows:

[0074] Memristor M 3 The initialization state is high impedance;

[0075] When inputting a i = 0, b i = 0, c i = 0, V = 0, the memristor M 1 Set to high impedance state, the memristor M 2 Set to high impedance state, during step 2, the memristor M 1 The voltage across the two ends is V M1 is approximately 0, the memristor M 2 The voltage across the two ends is V M2 is approximately 0, the memristor M 3 The voltage across the two ends is V M3 About V P ; Memristor M 2 Keeping the high impedance state unchanged, the memristor M 3 Keep the high impedance state unchanged; during step 3, the memristor M 1 The voltage across the two ends is V M1 About -V P , memristor M 2 The voltage across the two ends is V M2 About V P , memristor M 3 The voltage across the two ends is V M3 About 0; memristor M 2 Keeping the high impedance state unchanged, the memristor M 3 Keep the high impedance state unchanged, that is, the 1-bit addition result is s i = 0, c i+1 = 0;

[0076] When inputting a i = 0, b i = 0, c i = 1, V = 0, the memristor M 1 Set to high impedance state, the memristor M 2 Set to low resistance state, during step 2, the memristor M 1 The voltage across the two ends is V M1 is approximately 0, the memristor M 2 The voltage across the two ends is V M2 is approximately 0, the memristor M 3 The voltage across the two ends is V M3 About V P; Memristor M 2 Keeping the low resistance state unchanged, the memristor M 3 Keep the high impedance state unchanged; during step 3, the memristor M 1 The voltage across the two ends is V M1 About -2V P , memristor M 2 The voltage across the two ends is V M2 About V P , memristor M 3 The voltage across the two ends is V M3 About 0; memristor M 2 Keeping the low resistance state unchanged, the memristor M 3 Keep the high impedance state unchanged, that is, the 1-bit addition result is s i = 1, c i+1 = 0;

[0077] When inputting a i = 0, b i = 1, c i = 0, V = V P , memristor M 1 Set to high impedance state, the memristor M 2 Set to high impedance state, during step 2, the memristor M 1 The voltage across the two ends is V M1 About -V P , memristor M 2 The voltage across the two ends is V M2 is approximately 0, the memristor M 3 The voltage across the two ends is V M3 About V P ; Memristor M 2 Keeping the high impedance state unchanged, the memristor M 3 Keep the high impedance state unchanged; during step 3, the memristor M 1 The voltage across the two ends is V M1 About V P , memristor M 2 The voltage across the two ends is V M2 About 2V P , memristor M 3 The voltage across the two ends is V M3 About 0; memristor M 2 Converted to low resistance state, the memristor M 3 Keep the high impedance state unchanged, that is, the 1-bit addition result is s i = 1, c i+1 = 0;

[0078] When inputting a i = 0, b i = 1, c i = 1, V = VP , memristor M 1 Set to high impedance state, the memristor M 2 Set to low resistance state, during step 2, the memristor M 1 The voltage across the two ends is V M1 About -V P , memristor M 2 The voltage across the two ends is V M2 is approximately 0, the memristor M 3 The voltage across the two ends is V M3 About V P ; Memristor M 2 Keeping the low resistance state unchanged, the memristor M 3 Keep the high impedance state unchanged; during step 3, the memristor M 1 The voltage across the two ends is V M1 About V P , memristor M 2 The voltage across the two ends is V M2 About 2V P , memristor M 3 The voltage across the two ends is V M3 About 0; memristor M 2 Keeping the low resistance state unchanged, the memristor M 3 Keep the high impedance state unchanged, that is, the 1-bit addition result is s i = 1, c i+1 = 0;

[0079] When inputting a i = 1, b i = 0, c i = 0, V = 0, the memristor M 1 Set to low resistance state, the memristor M 2 Set to high impedance state, during step 2, the memristor M 1 The voltage across the two ends is V M1 is approximately 0, the memristor M 2 The voltage across the two ends is V M2 is approximately 0, the memristor M 3 The voltage across the two ends is V M3 About V P ; Memristor M 2 Keeping the high impedance state unchanged, the memristor M 3 Keep the high impedance state unchanged; during step 3, the memristor M 1 The voltage across the two ends is V M1 About -V P , memristor M 2 The voltage across the two ends is V M2 About 2V P , memristor M 3 The voltage across the two ends is V M3 About 0; memristor M2 Converted to low resistance state, the memristor M 3 Keep the high impedance state unchanged, that is, the 1-bit addition result is s i = 1, c i+1 = 0;

[0080] When inputting a i = 1, b i = 0, c i = 1, V = 0, the memristor M 1 Set to low resistance state, the memristor M 2 Set to high impedance state, during step 2, the memristor M 1 The voltage across the two ends is V M1 is approximately 0, the memristor M 2 The voltage across the two ends is V M2 is approximately 0, the memristor M 3 The voltage across the two ends is V M3 About V P ; Memristor M 2 Keeping the low resistance state unchanged, the memristor M 3 Keep the high impedance state unchanged; during step 3, the memristor M 1 The voltage across the two ends is V M1 About -V P , memristor M 2 The voltage across the two ends is V M2 About 2V P , memristor M 3 The voltage across the two ends is V M3 About 0; memristor M 2 Keeping the low resistance state unchanged, the memristor M 3 Keep the high impedance state unchanged, that is, the 1-bit addition result is s i = 1, c i+1 = 0;

[0081] When inputting a i = 1, b i = 1, c i = 1, V = 0, the memristor M 1 Set to low resistance state, the memristor M 2 Set to high impedance state, during step 2, the memristor M 1 The voltage across the two ends is V M1 About -V P , memristor M 2 The voltage across the two ends is V M2 is approximately 0, the memristor M 3 The voltage across the two ends is V M3 About 2V P ; Memristor M 2 Keeping the high impedance state unchanged, the memristor M 3During step 3, the memristor M 1 The voltage across the two ends is V M1 About V P , memristor M 2 The voltage across the two ends is V M2 About V P , memristor M 3 The voltage across the two ends is V M3 About 0; memristor M 2 Keeping the high impedance state unchanged, the memristor M 3 Keep the low impedance state unchanged, that is, the 1-bit addition result is s i = 0, c i+1 = 1;

[0082] When inputting a i = 1, b i = 1, c i = 1, V = V P , memristor M 1 Set to low resistance state, the memristor M 2 Set to low resistance state, during step 2, the memristor M 1 The voltage across the two ends is V M1 About -V P , memristor M 2 The voltage across the two ends is V M2 is approximately 0, the memristor M 3 The voltage across the two ends is V M3 About 2V P ; Memristor M 2 Keeping the low resistance state unchanged, the memristor M 3 During step 3, the memristor M 1 The voltage across the two ends is V M1 About V P , memristor M 2 The voltage across the two ends is V M2 About V P , memristor M 3 The voltage across the two ends is V M3 About 0; memristor M 2 Keeping the low resistance state unchanged, the memristor M 3 Keep the low impedance state unchanged, that is, the 1-bit addition result is s i = 1, c i+1 = 1;

[0083] Based on the above operations, the 1-bit approximate adder operation method provided in this embodiment can effectively control the logic output according to the 1-bit approximate adder operation truth table shown in Table 2; wherein, , .

[0084]

[0085] In summary, this embodiment operates an approximate adder composed of a memristor and a fixed resistor. By setting the memristor and configuring different operating voltages at the control end, a 1-bit approximate adder circuit operation can be realized in three steps. The present invention has the characteristics of a small number of devices, simple operation steps, and a compact structure, and provides reliable support for the realization of complex logical operations. Specifically, this embodiment discloses a 1-bit approximate adder device based on a memristor, including three identical memristors and a fixed resistor. By setting the memristor and configuring three control ends (BL 1 BL 2 BL 3 ) and source line (SL), three steps can realize the approximate adder logic function. 1 、Memristor 2 and memristor M 3 The positive electrode is connected to different bit lines (BL 1 BL 2 BL 3 ) are connected, the memristor M 1 、Memristor 2 and memristor M 3 The negative electrode of is connected to the same source line SL; one end of the fixed resistor is connected to the control end of the source line SL, and the other end is connected to the negative electrode of the memristor closest to the control end of the source line. i Defined as a memristor M 1 The other input logic value is b i Defined in the form of voltage at the control terminal BL 1 and SL, input logic value c i Defined as a memristor M 2 The resistance state of the memristor M 2 and memristor M 3 The resistance state is used as the output. This improves the computing efficiency and effectively saves the circuit area, which helps to support the implementation of more complex logic functions.

[0086] Example 2

[0087] In this embodiment, n is an integer greater than 1, and an n-bit approximate adder device is provided to implement two n-bit numbers a n ......a 2 a 1 and b n ......b 2 b 1 The approximate addition of the summation result s n......s 2 s 1 and carry out c n+1 ,like Figure 2 As shown, it includes: an approximate adder circuit and a control module; wherein the approximate adder circuit includes: 2n+1 identical memristors and a resistor (a fixed value resistor is used in this embodiment); the control module includes: controller 1 and controller 2.

[0088] Similarly, in this embodiment, the memristor includes a high resistance state and a low resistance state; the high resistance state corresponds to a logic value "0", and the low resistance state corresponds to a logic value "1". The resistance value of the resistor is between the high resistance state and the low resistance state of the memristor, preferably , where R H is the high-resistance resistance of the memristor, R L is the low-resistance resistance value of the memristor.

[0089] Specifically, the controller 1 is connected to the positive electrode of each memristor respectively; the negative electrode of each memristor is connected to the same source line SL; one end of the source line SL is suspended, and the other end is connected to the controller 2; the resistor is connected to the source line SL, one end of which is connected to the control end of the source line SL, and the other end is connected to the negative electrode of the memristor closest to the control end of the source line;

[0090] The controller 1 is used to divide the n-bit approximate addition process into initialization and n rounds of approximate addition sub-processes; each round of approximate addition sub-process performs a 1-bit approximate addition operation; specifically, the following operations are performed:

[0091] Initialization: Select n memristors from 2n+1 memristors and write logic value a to each of them. 1 ~ a n ; Select a memristor from the remaining memristors and write the input carry c 1 ; The remaining unset memristors are all set to high impedance state. For ease of operation, this embodiment adds the number a 1 ~ a n Write the first n memristors and carry the input c 1 Write the n+1th memristor and initialize the remaining n memristors to high impedance; input carry c 1 It can be 0 or 1. In this embodiment, c 1 = 0;

[0092] The first round of approximate addition subprocess: store a in the first n memristors 1 The memristor is used as the first memristor, and the n+1th memory c 1The memristor with a value n+2 is selected as the second memristor, and the memristor with no value n+2 is selected as the third memristor to perform 1-bit approximate addition; specifically, the method includes: applying a voltage V to the positive electrode of the first memristor in a first time period. BL1_1 = -V, making the positive electrode of the second memristor float; applying voltage V to the positive electrode of the third memristor BL3_1 = V P ; Apply a voltage V with an amplitude of 0 to the other end of the resistor SL_1 ; At this time, a carry is obtained in the third memristor ; In a second time period after the first time period, a voltage V is applied to the positive electrode of the first memristor BL1_2 = VV P ; Apply voltage V to the positive electrode of the second memristor BL2_2 = V P ; Make the positive electrode of the third memristor float; Apply voltage V to the other end of the resistor SL_2 = -V; at this time, the summation result is obtained in the second memristor ;

[0093] The i-th round of approximate addition sub-process: store a in the first n memristors i The memristor is used as the first memristor, and the n+ith memory c i The memristor is used as the second memristor to store c i+1 The n+i+1th memristor is used as the third memristor to perform 1-bit approximate addition. The specific operation is the same as the first round of approximate addition sub-process, which will not be described here; i=1,2,...,n;

[0094] After the nth to 1th round of approximate addition sub-process operation, the resistance state of the second memristor is the approximate sum of the two n-bit numbers s. n ......s 2 s 1 ; After the nth round of approximate addition sub-process operation, the resistance state of the third memristor is the carry output c of the approximate addition of two n-bit numbers n+1 ;s n ......s 2 s 1 and c n+1 This is the desired n-bit number a n ......a 2 a 1 With b n ......b 2 b 1 The approximate addition result of .

[0095] As in Example 1, when the logic value b iWhen the logic value is 0, V is 0; when the logic value is b i When it is 1, V is V P ; V P Meet V set / 2 <V P <V set , and V P <2|V reset |;V set V is the threshold value of the memristor changing from high resistance state to low resistance state; reset is the threshold value at which the memristor changes from a low-resistance state to a high-resistance state.

[0096] It should be noted that the n-bit serial approximate adder is obtained by expanding the 1-bit approximate adder described in Example 1, but it is only an expansion of the memristor part. The entire n-bit serial approximate adder includes only one resistor. The specific operating principle is the same as that of Example 1 and is not repeated here. The actual operation steps required for the entire n-bit serial approximate adder are 2n+1 steps. This solution is not only compact in area and easy to expand, but also can maintain low circuit complexity and short delay after expansion.

[0097] In order to make the technical solution of this embodiment clearer, specifically, taking a 4-bit serial approximate addition circuit as an example, the following description is given:

[0098] like Figure 3 The 4-bit serial approximate adder device provided by the present invention requires a resistor, 9 memristors and 9 steps to implement 4-bit serial approximate addition. , , , , ; Among them, BL 1 -BL 9 Connect the memristor M 1 -M 9 Based on the expanded serial approximate adder circuit, the present invention also provides a control method for a 4-bit serial approximate adder circuit for realizing two 4-bit numbers a 4 a 3 a 2 a 1 and b 4 b 3 b 2 b 1 The approximate addition of the summation result s 4 s 3 s 2 s 1 and carry out c 5; Specifically, the above serial approximate addition method includes the following 9 practical operation steps;

[0099] Step 1: Add the addend a 1 、a 2 、a 3 、a 4 Write the first four memristors M separately 1 、M 2 、M 3 、M 5 , c 1 Write the fifth memristor M 5 , initialize the remaining 4 memristors to high impedance state;

[0100] Step 2: Select storage a 1 The memristor M 1 As the first memristor, select storage c 1 The memristor M 5 As the second memristor, the memristor M 6 Used to store the c to be generated 2 , as the third memristor; V is applied to the first memristor BL1_1 = -V, floating the BL control terminal of the second memristor and applying V to the third memristor BL3_1 = V P , voltage V SL_1 The value is 0; after the operation is completed, the resistance of the third memristor is The logical value of

[0101] Step 3: Apply V to the first memristor BL1_2 = VV P , apply V to the second memristor BL2_2 = V P , making the BL control terminal of the third memristor float, the voltage V SL_2 The value is -V; after the operation is completed, the resistance of the second memristor is The logical value of b i When the logic value is 0, V is 0; when the logic value is b i When it is 1, V is V P ;

[0102] Step 4: Select storage a 2 The memristor M 2 As the first memristor, select storage c 2 The memristor M 6 As the second memristor, the memristor M 7 Used to store the c to be generated 3 , as the third memristor; V is applied to the first memristor BL1_1= -V, floating the BL control terminal of the second memristor and applying V to the third memristor BL3_1 = V P , voltage V SL_1 The value is 0; after the operation is completed, the resistance of the third memristor is The logical value of

[0103] Step 5: Apply V to the first memristor BL1_2 = VV P , apply V to the second memristor BL2_2 = V P , the BL control terminal of the third memristor is floating, and the voltage V SL_2 The value is -V; after the operation is completed, the resistance of the second memristor is The logical value of b 2 When the logic value is 0, V is 0; when the logic value is b 2 When it is 1, V is V P ;

[0104] Step 6. Select storage a 3 The memristor M 3 As the first memristor, select storage c 3 The memristor M 7 As the second memristor, the memristor M 8 Used to store the c to be generated 4 , as the third memristor; V is applied to the first memristor BL1_1 = -V, floating the BL control terminal of the second memristor and applying V to the third memristor BL3_1 = V P , voltage V SL_1 The value is 0; after the operation is completed, the resistance of the third memristor is The logical value of

[0105] Step 7: Apply V to the first memristor BL1_2 = VV P , apply V to the second memristor BL2_2 = V P , the BL control terminal of the third memristor is floating, and the voltage V SL_2 The value is -V; after the operation is completed, the resistance of the second memristor is The logical value of b 3 When the logic value is 0, V is 0; when the logic value is b 3 When it is 1, V is V P ;

[0106] Step 8. Select storage a 4 The memristor M 4 As the first memristor, select storage c4 The memristor M 8 As the second memristor, the memristor M 9 Used to store the c to be generated 4 , as the third memristor; V is applied to the first memristor BL1_1 = -V, floating the BL control terminal of the second memristor and applying V to the third memristor BL3_1 = V P , voltage V SL_1 The value is 0; after the operation is completed, the resistance of the third memristor is The logical value of

[0107] Step 9: Apply V to the first memristor BL1_2 = VV P , apply V to the second memristor BL2_2 = V P , the BL control terminal of the third memristor is floating, and the voltage V SL_2 The value is -V; after the operation is completed, the resistance of the second memristor is The logical value of b 4 When the logic value is 0, V is 0; when the logic value is b 4 When it is 1, V is V P ;

[0108] It should be noted that the above four steps 2-3, 4-5, 6-7 and 8-9 are similar approximate addition sub-processes, the difference being that different three memristors are selected to perform approximate addition calculations of different bits;

[0109] It should be further explained that the circuit structure and operation process of other n-bit approximate adders based on the present invention are similar to the logical operation process of the 4-bit serial approximate adder, which will not be described in detail here.

[0110] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A control method for an approximate adder circuit based on a memristor, characterized in that: Used to implement n-bit number a n ......a2a1 and b n ...approximate addition of b2b1; the approximate adder circuit comprises: a resistor and 2n+1 identical memristors; the negative electrodes of each memristor are connected to the same source line SL; one end of the source line SL is suspended, and the other end is connected to one end of the resistor; n≥1; The control method comprises: Select n memristors from 2n+1 memristors and write logic values ​​a1~ a respectively. n ; Select a memristor from the remaining memristors and write the input carry c1; the remaining memristors that have not been set are all set to high impedance state; Execute n rounds of approximate addition subprocesses in sequence; wherein, in the i-th round of approximate addition subprocess, perform the following operations: In the first time period, the logic value a will be written i The memristor is used as the first memristor, and a voltage -V is applied to its positive terminal; the stored carry c i The memristor with a value set is used as the second memristor, and its positive electrode is left floating; a memristor is selected from the unset memristors as the third memristor, and a voltage V is applied to its positive electrode. P ; Apply a voltage with an amplitude of 0 to the other end of the resistor; At this time, a carry is obtained in the third memristor ; In a second time period after the first time period, a voltage VV is applied to the positive electrode of the first memristor. P ; Apply voltage V to the positive electrode of the second memristor P ; Float the positive electrode of the third memristor; Apply a voltage of -V to the other end of the resistor; At this time, the summation result is obtained in the second memristor ; Where i=1,2,...,n; when the logical value b i When the logic value is 0, V is 0; when the logic value is b i When it is 1, V is V P ; V P Meet V set / 2 < V P < V set , and V P < 2|V reset |;V set V is the threshold value of the memristor changing from high resistance state to low resistance state; reset is the threshold value of the memristor changing from a low resistance state to a high resistance state; s n ...s2s1 and c n+1 This is the desired n-bit number a n ......a2a1 and b n ......The approximate addition result of b2b1.

2. An approximate adder device, characterized in that: Used to implement n-bit number a n ......a2a1 and b n ...approximate addition of b2b1, comprising: an approximate adder circuit and a control module; The approximate adder circuit comprises: a resistor and 2n+1 identical memristors; the negative electrodes of the memristors are connected to the same source line SL; one end of the source line SL is suspended, and the other end is connected to one end of the resistor; n≥1; The control module is used to execute the control method described in claim 1.

3. The approximate adder device according to claim 2, characterized in that: The resistance value of the resistor is between the high resistance state resistance value and the low resistance state resistance value of the memristor.

4. The approximate adder device according to claim 3, characterized in that: The resistance value of the resistor ; Among them, R H is the high-resistance resistance of the memristor, R L is the low-resistance state resistance value of the memristor.

5. The approximate adder device according to any one of claims 2 to 4, characterized in that: The memristors include a high resistance state and a low resistance state, the high resistance state corresponds to a logic value "0", and the low resistance state corresponds to a logic value "1".

6. A control system, characterized in that: include: A memory and a processor, wherein the memory stores a computer program, and the processor executes the control method according to claim 1 when executing the computer program.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method of claim 1.

8. A computer program product, characterized in that The invention comprises a computer program / instruction, which implements the control method of claim 1 when executed by a processor.

Images