Control Method and Device for Memristor-Based Non-Volatile Majority Gate Circuit and Addition Circuit

Abstract

The present invention discloses a control method and device for a non-volatile majority gate circuit and an adder circuit based on memristors, belonging to the field of microelectronic logic operation technology; in the majority gate circuit, three memristors respectively correspond to inputting the logic values a, b, and c to be subjected to majority gate logic operation, and the result of the logic operation is determined by a voltage comparator according to the comparison result between the common node voltage and the reference voltage; by changing the voltage of the positive electrode of the memristor, the M(a, b, c) and two types of majority gate logics can be realized; in the process of realizing different types of majority gate logics, there is no need to increase the number of memristors, and two types of majority gate logic operations can be realized with fewer devices and faster calculation speed, and these two types of majority gate logics are complete, and any Boolean function can be realized by combining the two types of majority gate logics; based on this, the present invention can meet the requirements for multifunctional logic in practical applications with high integration and fast calculation speed.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic logic operations, and more specifically, relates to a control method and device for a non-volatile majority gate circuit and an adder circuit based on a memristor. Background Art

[0002] Traditional computers adopt the von Neumann architecture, in which the storage unit and the processing unit are physically separated. Generally, the processing unit reads data from the storage unit, performs corresponding arithmetic and logical operations, and then writes the data back to the storage unit. Frequent read and write operations impose a huge burden on the bus. Especially when the transmission speed is limited, this not only affects the data transmission efficiency but also causes a considerable amount of power consumption. At the same time, there is a speed mismatch between the processing unit and the storage unit, and this difference is increasing year by year. Therefore, how to solve the "bottleneck problem" and "memory wall" problem existing in the von Neumann architecture has become the research focus in the field of computer architecture.

[0003] To break through these bottlenecks, the technology of in-memory computing has emerged. By integrating the computing and storage functions on the same hardware platform, this technology realizes advantages such as high computing parallelism, low latency, and low power consumption, and has gradually become a research hotspot in the academic and industrial circles. As a new type of non-volatile storage device, the memristor has advantages such as low power consumption, small size, and compatibility with CMOS processes, and has become an ideal candidate device for in-memory computing architectures. The memristor can store information by changing its resistance state and can still maintain the resistance state after power-off, so it is naturally suitable for digital logic operations. By simultaneously selecting multiple memristor units for readout operations, the specified logical operations or complex arithmetic functions can be completed without explicitly retrieving the data stored in the memristor, thereby realizing in-memory computing. This method greatly improves the speed and efficiency of information processing.

[0004] The majority-inverter graph (MIG) logic is a new type of data logic representation structure, which consists of majority gate logic (MAJ) and inverter logic (INV). The logical expression of the three-input majority decision gate is: M(a, b, c) = a·b + a·c + b·c, and the expression of the inverter logic is: 。The MAJ and inversion logic form a complete logic set, that is, all Boolean logic functions can be implemented by iterating the MAJ and inversion logic. Logic optimization involves manipulating the logical representation structure to minimize certain target metrics. The logic optimization method is closely related to the data structure on which it operates. The MIG logic primitive itself exhibits high potential for efficient logic synthesis. MIG often requires a smaller logic depth to implement the same complex logic, and thus has better experimental results in terms of propagation delay. The key and difficulty in implementing MIG logic lies in implementing the majority gate logic. Majority gate logic plays a core role in arithmetic circuits such as adders and multipliers, as well as in complex reasoning tasks. Therefore, it is of great significance to study a majority gate logic circuit.

[0005] However, the existing CMOS-based implementations of majority gates not only have a high hardware complexity but also suffer from significant delay and power consumption bottlenecks. Implementing majority gate logic based on memristors provides a new solution to this problem. The existing implementation schemes of majority gate logic based on memristors operate on a, b, and c respectively through three memristor units, implementing the three-input majority gate logic M(a, b, c) = a·b + a·c + b·c. Although it can reduce the hardware complexity, this logic scheme only supports a single logical operation and lacks the implementation of inversion logic; while in the multifunctional logic implemented based on majority gate logic, it often involves not only the traditional majority gate logic M(a, b, c) = a·b + a·c + b·c but also the majority gate logic including inversion logic ; due to the simultaneous involvement of two different types of majority gate logics, if the existing implementation schemes of majority gate logic based on memristors are adopted, the majority gate logic often needs to be decomposed into two independent logical operations: the majority gate logic M(a, b, c) and the inversion logic, and at least four memristor units operate on a, b, c, respectively. The number of required devices is large, the integration level is low, and the calculation speed is also low, making it impossible to meet the requirements for multifunctional logic in practical applications with a high integration level and calculation speed. Summary of the Invention

[0006] In view of the above defects or improvement requirements of the prior art, the present invention provides a control method and device for a non-volatile majority gate circuit and adder circuit based on memristors, aiming to solve the technical problem that the prior art is difficult to meet the requirements for multifunctional logic in practical applications with a high integration level and calculation speed due to only supporting a single logical operation.

[0007] To achieve the above object, in the first aspect, the present invention provides a control method for a non-volatile majority gate circuit based on memristors;

[0008] Most of the majority gates include: a voltage comparator, a resistor, and three identical memristors; the negative electrodes of the three memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input terminal of the voltage comparator is connected to the common node of the three memristors and the resistor; the resistance value of the resistor is the low-resistance state resistance value of the memristor;

[0009] The above control method includes:

[0010] Write the logic values a, b, and c to be subjected to the majority gate logic operation into the three memristors respectively, apply a voltage V to the positive electrode of the memristor where the logic value a is written a , apply a voltage V to the positive electrode of the memristor where the logic value b is written b , apply a voltage V to the positive electrode of the memristor where the logic value c is written c , connect a reference voltage V to the second input terminal of the voltage comparator Ref , and obtain the result of the majority gate logic operation at the output terminal of the voltage comparator;

[0011] Among them, when performing the majority gate logic operation M(a, b, c) = a·b + a·c + b·c on the logic values a, b, and c, V a = V b = V c = V 1 , V Ref = V Ref1 ; 0 < V 1 < V set ; V 1 / 2 < V Ref1 < 2V 1 / 3;

[0012] When performing the majority gate logic operation on the logic values a, b, and c , V a = V b = V 2 , V c = 0, V Ref = V Ref2 ; 0 < V 2 < V set ; V 2 / 3 < V Ref2 < V 2 / 2;

[0013] V set is the threshold value for the memristor to change from the high-resistance state to the low-resistance state; when the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs the first level, and the first level is used as the result "1" of the majority gate logic operation; otherwise, the output terminal outputs the second level, and the second level is used as the result "0" of the majority gate logic operation.

[0014] Further preferably, corresponding logic values are written by setting the high and low resistance states of the memristor; wherein, the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1".

[0015] In a second aspect, the present invention provides a majority gate operation device, including: a majority gate circuit and a controller;

[0016] Wherein, the majority gate circuit includes: a voltage comparator, a resistor, and three identical memristors; the negative electrodes of the three memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input terminal of the voltage comparator is connected to the common node of the three memristors and the resistor; the resistance value of the resistor is the low resistance state resistance value of the memristor;

[0017] The controller is configured to execute the control method provided in the first aspect of the present invention.

[0018] In a third aspect, the present invention provides a control method for an adder circuit, which is used to implement the addition operation of n-bit numbers a n ......a 2 a 1 and b n ......b 2 b 1 ; the adder circuit includes: a voltage comparator, a resistor, and five memristors; the negative electrodes of the five memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input terminal of the voltage comparator is connected to the common node of the five memristors and the resistor; the resistance value of the resistor is the low resistance state resistance value of the memristor; n≥1;

[0019] The above control method includes: executing n rounds of addition sub-processes; wherein, in the i-th round of addition sub-process, the following operations are performed:

[0020] Select three memristors and denote them as the first memristor, the second memristor, and the third memristor respectively; write the logic value a i into the first memristor, write the logic value b i into the second memristor, and write the carry c i of the i-th round of addition into the third memristor;

[0021] Apply voltages V 1 to the positive electrodes of the first memristor, the second memristor, and the third memristor respectively, connect a reference voltage V Ref1 to the second input terminal of the voltage comparator, and obtain the result M(a i , b i , c i ) = a i ·b i + a i ·ci + b i ·c i , as the carry c for the (i + 1)-th round addition i+1 ;

[0022] Apply voltage V to the positive electrodes of the first memristor and the second memristor respectively 2 , apply a voltage with an amplitude of 0 to the positive electrode of the third memristor, and connect a reference voltage V to the second input terminal of the voltage comparator Ref2 , and obtain the result of the majority gate logic operation at the output terminal of the voltage comparator ;

[0023] Denote the remaining two unassigned memristors as the fourth memristor and the fifth memristor respectively, and write M(a i , b i , c i ) into the fourth memristor, and write ;

[0024] Apply voltage V to the positive electrodes of the third memristor and the fifth memristor respectively 2 , apply a voltage with an amplitude of 0 to the positive electrode of the fourth memristor, and connect a reference voltage V to the second input terminal of the voltage comparator Ref2 , and obtain the result of the majority gate logic operation at the output terminal of the voltage comparator , as the summation result s for the i-th round addition i ;

[0025] s n ......s 2 s 1 and c n+1 are the addition results of the desired n-bit numbers a n ......a 2 a 1 and b n ......b 2 b 1 ;

[0026] where i = 1, 2,..., n; 0 < V 1 < V set ; V 1 / 2 < V Ref1 < 2V 1 / 3; 0 < V 2 < V set ; V 2 / 3 < V Ref2 < V 2 / 2; V setis the threshold value for the memristor to change from the high resistance state to the low resistance state; when the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs a first level, and the first level is used as the result "1" of the majority gate logic operation; otherwise, the output terminal outputs a second level, and the second level is used as the result "0" of the majority gate logic operation.

[0027] Further preferably, the corresponding logic values are written by setting the high and low resistance states of the memristor; among them, the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1".

[0028] In a fourth aspect, the present invention provides an addition operation device, including: an addition circuit and a controller;

[0029] The addition circuit includes: a voltage comparator, a resistor, and five memristors; the negative electrodes of the five memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input terminal of the voltage comparator is connected to the common node of the five memristors and the resistor; the resistance value of the resistor is the low resistance state resistance value of the memristor;

[0030] The controller is used to execute the control method provided in the third aspect of the present invention.

[0031] In a fifth aspect, the present invention provides a control system, including: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it executes the control method provided in the first aspect or the third aspect of the present invention.

[0032] In a sixth aspect, the present invention further provides a computer-readable storage medium, the computer-readable storage medium includes a stored computer program, wherein when the computer program is run by a processor, it controls the device where the storage medium is located to execute the control method provided in the first aspect or the third aspect of the present invention.

[0033] In a seventh aspect, the invention further provides a computer program product, including computer program / instructions, and when the computer program / instructions are executed by a processor, they implement the control method provided in the first aspect or the third aspect of the present invention.

[0034] Generally speaking, through the above technical solutions conceived by the present invention, the following beneficial effects can be achieved:

[0035] 1. In the control method of the memristor-based non-volatile majority gate circuit and the corresponding majority gate operation device provided by the present invention, the majority gate circuit includes three memristors, one resistor, and one voltage comparator; the three memristors respectively correspond to input logic values a, b, and c to be subjected to majority gate logic operation, and the result of the majority gate logic operation is determined by the voltage comparator according to the comparison result between the common node voltage and the reference voltage; by changing the voltage at the positive electrode of the memristor, the traditional majority gate logic M(a, b, c) and the new majority gate logic including the inversion logic can be realized. ; Among them, the majority gate logic is realized by avoiding the situation of decomposing it into two independent logic operations of the majority gate logic M(a, b, c) and the inversion logic, and can be realized by applying voltage in one step, so that in the process of realizing different types of majority gate logics, there is no need to increase the number of memristors, and two majority gate logic operations can be realized with fewer devices and faster calculation speed, and these two majority gate logics are complete, and any Boolean function can be realized by combining the two majority gate logics, thus meeting the requirements of multi-functional logic; based on this, the present invention can meet the requirements of multi-functional logic in practical applications with high integration and fast calculation speed.

[0036] 2. The control method of the memristor-based non-volatile majority gate circuit and the corresponding majority gate operation device provided by the present invention keep the input information values written in the three input memristors after the logic calculation is completed, which is non-destructive to the input information, and at the same time has non-volatility, realizing a majority gate logic circuit with the resistance value of the memristor as the input and a non-destructive operation process; the data multiplexing of this circuit is relatively strong, and no additional copying operation is required to save data in practical applications.

[0037] 3. The control method of the adder circuit and the corresponding adder operation device provided by the present invention are realized based on the implementation idea of the majority gate logic operation provided in the first aspect of the present invention. By combining the two majority gate logics of the combination M(a, b, c) and and respectively using the control methods provided in the first aspect of the present invention to control the implementation of M(a, b, c) and , the addition operation can be realized with fewer devices and faster calculation speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a schematic diagram of the majority gate circuit provided by the embodiment of the present invention.

[0039] Figure 2 is a control schematic diagram of the majority gate logic M(a, b, c) provided by the embodiment of the present invention.

[0040] Figure 3Schematic diagram of the design concept of the majority gate logic M(a, b, c) provided by the embodiments of the present invention.

[0041] Figure 4 Majority gate logic provided by the embodiments of the present invention Control schematic diagram.

[0042] Figure 5 Majority gate logic provided by the embodiments of the present invention Schematic diagram of the design concept.

[0043] Figure 6 Schematic diagram of the adder circuit provided by the present invention.

[0044] Figure 7 Schematic diagram of the gate-level representation for implementing addition operation based on majority gate logic provided by the present invention.

[0045] Figure 8 Test results of the 1-bit adder circuit based on two majority gate logics provided by the present invention. Detailed implementation manners

[0046] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0047] To achieve the above objective, in a first aspect, the present invention provides a control method for a non-volatile majority gate circuit based on memristors;

[0048] The majority gate circuit includes: a voltage comparator, a resistor, and three identical memristors; the negative electrodes of the three memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input terminal of the voltage comparator is connected to the common node of the three memristors and the resistor; the resistance value of the resistor is the low-resistance state resistance value of the memristor;

[0049] The above control method includes:

[0050] Writing the logic values a, b, and c to be subjected to majority gate logic operation into the three memristors respectively, applying a voltage V a to the positive electrode of the memristor written with the logic value a, applying a voltage V b to the positive electrode of the memristor written with the logic value b, applying a voltage V c to the positive electrode of the memristor written with the logic value c, connecting a reference voltage V Ref to the second input terminal of the voltage comparator, and obtaining the result of the majority gate logic operation at the output terminal of the voltage comparator;

[0051] Among them, when performing a majority gate logic operation M(a, b, c) = a·b + a·c + b·c on logical values a, b, and c, V a = V b = V c = V 1 , V Ref = V Ref1 ; 0 < V 1 <V set ; V 1 / 2 < V Ref1 <2V 1 / 3;

[0052] When performing a majority gate logic operation on logical values a, b, and c When, V a =V b = V 2 , V c = 0, V Ref = V Ref2 ; 0 < V 2 <V set ; V 2 / 3 < V Ref2 <V 2 / 2;

[0053] V set is the threshold value for the memristor to change from the high resistance state to the low resistance state; when the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs the first level, and the first level is used as the result "1" of the majority gate logic operation; otherwise, the output terminal outputs the second level, and the second level is used as the result "0" of the majority gate logic operation.

[0054] It can be understood that the correspondence between the output level of the voltage comparator and the logical value can be flexibly set. For example, with the first input terminal as the positive terminal, the second input terminal as the negative terminal, the first level as the high level, the second level as the low level, the high level is used as the result "1" of the majority gate logic operation, and the low level is used as the result "0" of the majority gate logic operation. It is also possible to use the first input terminal as the negative terminal, the second input terminal as the positive terminal, the first level as the low level, the second level as the high level, the low level is used as the result "1" of the majority gate logic operation, and the high level is used as the result "0" of the majority gate logic operation.

[0055] In a second aspect, the present invention provides a majority gate operation device, including: a majority gate circuit and a controller;

[0056] Among them, most of the logic gates include: a voltage comparator, a resistor, and three identical memristors; the negative electrodes of the three memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input terminal of the voltage comparator is connected to the common node of the three memristors and the resistor; the resistance value of the resistor is the low resistance state resistance value of the memristor.

[0057] The controller is configured to execute the control method provided in the first aspect of the present invention.

[0058] The related technical solutions are the same as the control method provided in the first aspect of the present invention, and will not be elaborated here.

[0059] To further illustrate the control method of the non-volatile majority logic gate based on memristor and the corresponding majority logic operation device provided by the present invention, a specific embodiment will be described in detail below:

[0060] As Figure 1 shown, this embodiment provides a majority logic gate, including: M 1 , M 2 and M 3 three memristors, a fixed-value resistor, and a voltage comparator; among them, the positive electrodes of the memristors M 1 , M 2 and M 3 are controlled through the control terminals T 1 , T 2 and T 3 ; one end of the fixed-value resistor is controlled through the control terminal T 4 ; the other end of the fixed-value resistor is connected to the negative electrodes of the memristors M 1 , M 2 and M 3 , and the voltage of this common node is represented by V Com ; the control voltages of the remaining four control ports T 1 , T 2 , T 3 and T 4 are V T1 , V T2 , V T3 and V T4 respectively. The positive terminal of the voltage comparator is connected to the common node of the memristor and the series resistor, the negative terminal is connected to the reference voltage V Ref , and the output terminal voltage is V o .

[0061] The memristor includes two resistance states, namely the high resistance state (High Resistance State, HRS) and the low resistance state (Low Resistance State, LRS), and the memristor can be switched between the two resistance states by applying a port voltage with a specific direction and magnitude. Among them, by applying a voltage greater than V setThe forward voltage can set the memristor from the high-resistance state to the low-resistance state; conversely, by applying a negative voltage less than V reset , the memristor can be changed from the low-resistance state to the high-resistance state. V set is the threshold for the memristor to change from the high-resistance state to the low-resistance state; V reset is the threshold for the memristor to change from the low-resistance state to the high-resistance state.

[0062] The high and low configuration resistances of the memristor are R H and R L , R H <<R L ; preferably, in this embodiment, the resistance value of the resistor is equal to the resistance value of the low resistance of the memristor. The high resistance R H of the memristor = 100 KΩ, and the low resistance R L = 1 KΩ. In the case of the resistor R = 1 KΩ.

[0063] The three input variables a, b, and c of the majority gate logic are respectively mapped to the resistance states of the memristors M 1 , M 2 and M 3 . Among them, the high-resistance state of the memristor corresponds to the logic value "0", and the low-resistance state of the memristor corresponds to the logic value "1"; the output of the logic is the voltage value at the output port of the comparator. Among them, when the output V o = V+, it means that the output is a high level, corresponding to the logic result of "1"; when the output V o = V-, it means that the output is a low level, corresponding to the logic result of "0".

[0064] Furthermore, based on the above logic circuit, only by changing the control voltages applied to the control ports T 1 , T 2 , T 3 and T 4 , the two majority gate logics of M(a, b, c) and can be realized. The specific implementation steps are as follows:

[0065] (1) Realization of the majority gate logic M(a, b, c):

[0066] As Figure 2 shown, by applying voltages V 1 , T 2 , T 3 and T 4 to the control ports T 1 , V 1 , V 1 , 0, V Ref = V Ref1 respectively; the result of the logical operation is obtained through the output terminal of the voltage comparator. The principle of the logical implementation is that when the input memristor M 1, M 2 and M 3 When at least two of the memristors are in the low - resistance state, the voltage V of the common node Com is greater than the reference voltage V of the comparator Ref1 , thus outputting a high - level "1"; conversely, when the input memristors M 1 , M 2 and M 3 have at most one memristor in the low - resistance state, the voltage V of the common node Com is less than the reference voltage V of the comparator Ref1 , thus outputting a low - level "0". Specifically, to implement the majority - gate logic M(a, b, c), the port voltage V 1 and the reference voltage V of the voltage comparator Ref need to satisfy the following constraint conditions: 0 < V 1 < V set ; V 1 / 2 < V Ref1 < 2V 1 / 3, and its design concept is as shown in Figure 3 .

[0067] (2) Implementation of the majority - gate logic :

[0068] As shown in Figure 4 , by applying voltages V 1 , T 2 , T 3 and T 4 to the control ports T 2 , V 2 , 0, 0 respectively, V Ref = V Ref2 ; the result of the logical operation is obtained through the output terminal of the voltage comparator. The principle of logical implementation is that when the input memristors M 1 , M 2 are in the low - resistance "1" state, they can raise the voltage V of the common node Com , and when the voltage V of the common node Com is greater than the reference voltage V of the comparator Ref2 , a high - level "1" is output; when the input memristor M 3 is in the low - resistance state, it will lower the voltage V of the common node Com , and when the voltage V of the common node Com is less than the reference voltage V of the comparator Ref2 , a low - level "0" is output. Specifically, to implement the majority - gate logic , the port voltage V 2 and the reference voltage V of the comparator Ref2 need to satisfy the following constraint conditions: 0 < V 2 < Vset ; V 2 / 3 < V Ref2 < V 2 / 2, and its design concept is as Figure 5 shown.

[0069] The present invention provides a method for implementing reconfigurable majority gate logic based on memristors. By simply applying different port voltages, two types of majority gate logics, M(a, b, c) and can be realized, thereby improving the efficiency of arithmetic operations. At the same time, the two proposed majority gate logics are complete, and any Boolean function can be realized by combining the two logics. For example, for the logic a·c, it can be realized by setting b = 0 in the logic M(a, b, c); for the logic a + c, it can be realized by setting b = 0 in the logic M(a, b, c); for the logic , it can be realized by setting b = 0 in the logic ; for the logic , it can be realized by setting b = 1 in the logic ; and for more complex logical expressions, they can be realized by iterating the above logics.

[0070] Considering that the adder is the most basic arithmetic unit in digital circuit design, its performance directly affects the efficiency and power consumption of data processing. Traditional CMOS adders rely on the full adder structure, and their implementation process requires multiple logic gates to be cascaded. Especially in carry calculation, the delay accumulates linearly with the increase in the number of bits. This cascaded logic not only consumes a large amount of hardware resources but also shows obvious performance bottlenecks in the expansion of high-bit adders. The design of memristor-based adders provides a new optimization approach. For example, by implementing Boolean calculations of carry output and sum output through majority gate logic, the number of logic levels and delay can be significantly reduced. However, traditional majority gate and inversion logics are two independent logical operations, and they require more iterative operation steps when implementing the full adder function, and the calculation speed and area efficiency still need to be further improved. Therefore, the present invention focuses on taking the adder as an example to specifically illustrate the application of the implementation methods of the two majority gate logics provided by the present invention in the adder operation implementation process, as follows:

[0071] In the third aspect, the present invention provides a control method for an adder circuit, which is used to implement the addition operation of n-bit numbers a n ......a 2 a 1 and b n ......b 2 b 1 ; such as Figure 6As shown, the adder circuit includes: a voltage comparator, a resistor, and five memristors; the negative electrodes of the five memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input terminal of the voltage comparator is connected to the common node of the five memristors and the resistor; the resistance value of the resistor is the low-resistance state resistance value of the memristor; n≥1;

[0072] The above control method includes: performing n rounds of addition sub-processes; wherein, in the i-th round of addition sub-process, the following operations are performed:

[0073] Select three memristors and denote them as the first memristor, the second memristor, and the third memristor respectively; write the logical value a into the first memristor i , write the logical value b into the second memristor i , and write the carry c of the i-th round of addition into the third memristor i ; wherein, the logic "1" means setting the memristor resistance state to low resistance, and the logic "0" means setting the memristor resistance state to high resistance. When i = 1, the carry c 1 is input by the user and can be either logic "1" or logic "0".

[0074] Apply voltage V to the positive electrodes of the first memristor, the second memristor, and the third memristor respectively 1 , connect the reference voltage V to the second input terminal of the voltage comparator Ref1 , and obtain the result M(a i , b i , c i ) = a i ·b i + a i ·c i + b i ·c i of the majority gate logic operation at the output terminal of the voltage comparator, as the carry c i+1 of the (i + 1)-th round of addition; in this process, the first memristor, the second memristor, the third memristor, the resistor, and the voltage comparator constitute the majority gate circuit in the first aspect of the present invention. Through the control method provided in the first aspect of the present invention, the majority gate logic operation M(a i , b i , c i ) = a i ·b i + a i ·c i + b i ·c i is realized.

[0075] Apply voltage V to the positive electrodes of the first memristor and the second memristor respectively 2, a voltage with an amplitude of 0 is applied to the positive electrode of the third memristor, and a reference voltage V is connected to the second input terminal of the voltage comparator Ref2 , and the result of the majority gate logic operation is obtained at the output terminal of the voltage comparator , which is denoted as s i ; In this process, the first memristor, the second memristor, the third memristor, the resistor, and the voltage comparator constitute the majority gate circuit in the first aspect of the present invention, and the majority gate logic operation is realized through the control method provided in the first aspect of the present invention .

[0076] The remaining two unassigned memristors are respectively denoted as the fourth memristor and the fifth memristor, and M(a i , b i , c i ) is written in the fourth memristor, and ;

[0077] Voltages V are respectively applied to the positive electrodes of the third memristor and the fifth memristor 2 , a voltage with an amplitude of 0 is applied to the positive electrode of the fourth memristor, and a reference voltage V is connected to the second input terminal of the voltage comparator Ref2 , and the result of the majority gate logic operation is obtained at the output terminal of the voltage comparator , which is used as the summation result s in the i-th round of addition i ; In this process, the third memristor, the fifth memristor, the fourth memristor, the resistor, and the voltage comparator constitute the majority gate circuit in the first aspect of the present invention, and the majority gate logic operation is realized through the control method provided in the first aspect of the present invention .

[0078] After n rounds of addition sub-processes, s n ...... s 2 s 1 and c n+1 are the addition results of the n-bit numbers a n ...... a 2 a 1 and b n ...... b 2 b 1 ;

[0079] where i = 1, 2,..., n; 0 < V 1 < V set ; V 1 / 2 < V Ref1 < 2V 1 / 3; 0 < V 2 < V set ; V 2 / 3 < VRef2 <V 2 / 2; V set is the threshold value for the memristor to transition from the high-resistance state to the low-resistance state; when the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs a first level, and the first level is used as the result "1" of the majority gate logic operation; otherwise, the output terminal outputs a second level, and the second level is used as the result "0" of the majority gate logic operation.

[0080] It can be understood that the correspondence between the output level of the voltage comparator and the logical value can be set flexibly. For example, with the first input terminal as the positive terminal, the second input terminal as the negative terminal, the first level as the high level, the second level as the low level, the high level is used as the result "1" of the majority gate logic operation, and the low level is used as the result "0" of the majority gate logic operation. It is also possible to have the first input terminal as the negative terminal, the second input terminal as the positive terminal, the first level as the low level, the second level as the high level, the low level is used as the result "1" of the majority gate logic operation, and the high level is used as the result "0" of the majority gate logic operation.

[0081] The schematic diagram of the gate-level representation for implementing the addition operation based on the majority gate logic is as Figure 7 shown.

[0082] It should be noted that the above majority gate logic operation M(a i , b i , c i ) = a i ·b i + a i ·c i + b i ·c i and the execution order of the majority gate logic operation is not limited.

[0083] Furthermore, taking the 1-bit addition operation circuit (n = 1) based on two majority gate logics as an example for illustration. Specifically, in the case where the high resistance R H of the memristor is 100 KΩ and the low resistance R L is 1 KΩ, the resistance R = 1 KΩ. Verifying the function of the adder, the experimental results as shown in Figure 8 are obtained (where R M represents the resistance value of the memristor). It can be seen from the figure that the one-bit full adder provided by the present invention has a correct function and the calculation accuracy of the present invention is relatively high.

[0084] Fourthly, the present invention provides an addition operation device, including: an addition circuit and a controller;

[0085] The adder circuit includes: a voltage comparator, a resistor, and five memristors; the negative electrodes of the five memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input terminal of the voltage comparator is connected to the common node of the five memristors and the resistor; the resistance value of the resistor is the low-resistance state resistance value of the memristor.

[0086] The controller is used to execute the control method provided in the third aspect of the present invention.

[0087] Preferably, in an alternative embodiment, the resistance value of the resistor is the low-resistance state resistance value of the memristor.

[0088] The related technical solutions are the same as the control method provided in the third aspect of the present invention, and will not be elaborated here.

[0089] In a fifth aspect, the present invention provides a control system, including: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it executes the control method provided in the first aspect or the third aspect of the present invention.

[0090] The related technical solutions are the same as the control method provided in the first aspect or the third aspect of the present invention, and will not be elaborated here.

[0091] In a sixth aspect, the present invention further provides a computer-readable storage medium, the computer-readable storage medium includes a stored computer program, wherein when the computer program is run by a processor, it controls the device where the storage medium is located to execute the control method provided in the first aspect or the third aspect of the present invention.

[0092] The related technical solutions are the same as the control method provided in the first aspect or the third aspect of the present invention, and will not be elaborated here.

[0093] In a seventh aspect, the invention further provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, they implement the control method provided in the first aspect or the third aspect of the present invention.

[0094] In summary, the present invention designs a reconfigurable majority gate logic circuit based on memristors and its adder implementation scheme, aiming to solve the problems of the current single nature of memristor majority gates, high delay in addition arithmetic functions, and large hardware overhead. The two proposed majority gates include both the traditional three-input majority gate logic M(a, b, c) = a·b + a·c + b·c and the new majority gate logic including the inversion logic. . For the majority gate logic set a = "0", b = "1" in it to obtain , that is, the inversion logic is implemented. The two proposed reconfigurable logics can implement the MIG logic, and the MIG logic is complete. Therefore, the proposed reconfigurable logic is complete. By iteratively proposing two majority gate logics, any Boolean function can be implemented. By combining the in-memory computing characteristics of memristors, the present invention can effectively improve the performance of logical operations and arithmetic functions such as adders, significantly reduce the consumption of hardware resources and latency, and provide a new technical path for the efficient implementation of in-memory computing.

[0095] Those skilled in the art can easily understand that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A control method for a non-volatile majority gate circuit based on a memristor, characterized in that: The majority gate circuit comprises: a voltage comparator, a resistor and three identical memristors; the negative electrodes of the three memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to a common node of the three memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The control method comprises: The logic values ​​a, b, and c to be operated on by the majority gate logic operation are written into the three memristors respectively, and a voltage V is applied to the positive electrode of the memristor with the logic value a written. a , a voltage V is applied to the positive electrode of the memristor that writes the logic value b b , apply voltage V to the positive electrode of the memristor that writes the logic value c c , connect the reference voltage V to the second input of the voltage comparator Ref , the result of majority gate logic operation is obtained at the output of the voltage comparator; Among them, when the majority gate logic operation M(a,b,c) = a·b + a·c + b·c is performed on the logic values ​​a, b, c, V a =V b = V c = V1, V Ref = V Ref1 ; 0<V1<V set ; V1 / 2<V Ref1 <2V1 / 3; When performing majority gate logic operations on logic values ​​a, b, and c When V a = V b = V2, V c = 0, V Ref = V Ref2 ; 0<V2<V set ; V2 / 3<V Ref2 <V2 / 2; V set is the threshold value for the memristor to change from a high-resistance state to a low-resistance state; when the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs a first level, and the first level is used as the result of the majority gate logic operation "1"; otherwise, the output terminal outputs a second level, and the second level is used as the result of the majority gate logic operation "0".

2. The control method according to claim 1, characterized in that: The corresponding logic value is written by setting the high and low resistance states of the memristor; wherein the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1".

3. A majority gate computing device, characterized in that: include: Most gate circuits and controllers; The majority gate circuit comprises: a voltage comparator, a resistor and three identical memristors; The negative electrodes of the three memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the three memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The controller is used to execute the control method described in claim 1 or 2.

4. A control method for an adding circuit, characterized in that: Used to implement n-bit number a n ......a2a1 and b n ......addition operation of b2b1; the addition circuit comprises: a voltage comparator, a resistor and five memristors; the negative electrodes of the five memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the five memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; n≥1; The control method comprises: executing n rounds of addition sub-processes; wherein the following operations are performed in the i-th round of addition sub-processes: Select three memristors and record them as the first memristor, the second memristor and the third memristor respectively; write the logic value a into the first memristor i , write the logic value b into the second memristor i , write the carry c of the i-th round of addition into the third memristor i ; A voltage V1 is applied to the positive electrodes of the first memristor, the second memristor, and the third memristor respectively, and a reference voltage V is connected to the second input terminal of the voltage comparator. Ref1 , the result of the majority gate logic operation M(a i ,b i ,c i ) = a i b i + a i ·c i + b i ·c i , as the carry c of the i+1th round of addition i+1 ; A voltage V2 is applied to the positive electrodes of the first memristor and the second memristor respectively, a voltage with an amplitude of 0 is applied to the positive electrode of the third memristor, and a reference voltage V is connected to the second input terminal of the voltage comparator. Ref2 , the result of the majority gate logic operation is obtained at the output of the voltage comparator ; The remaining two unset memristors are marked as the fourth memristor and the fifth memristor, and M(a i ,b i ,c i ), write in the fifth memristor ; A voltage V2 is applied to the positive electrodes of the third memristor and the fifth memristor respectively, a voltage with an amplitude of 0 is applied to the positive electrode of the fourth memristor, and a reference voltage V is connected to the second input terminal of the voltage comparator. Ref2 , the result of the majority gate logic operation is obtained at the output of the voltage comparator , as the summation result s in the i-th round of addition i ; s n ...s2s1 and c n+1 This is the desired n-bit number a n ......a2a1 and b n ......the result of adding b2b1; Where i=1,2,...,n; 0<V1<V set ; V1 / 2<V Ref1 <2V1 / 3;0<V2<V set ; V2 / 3<V Ref2 <V2 / 2;V set is the threshold value for the memristor to change from a high-resistance state to a low-resistance state; when the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs a first level, and the first level is used as the result of the majority gate logic operation "1"; otherwise, the output terminal outputs a second level, and the second level is used as the result of the majority gate logic operation "0".

5. The control method according to claim 4, characterized in that: The corresponding logic value is written by setting the high and low resistance states of the memristor; wherein the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1".

6. An addition operation device, characterized in that: include: Adding circuits and controllers; The adding circuit comprises: a voltage comparator, a resistor and five memristors; The negative electrodes of the five memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the five memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The controller is used to execute the control method described in claim 4 or 5 of the present invention.

7. A control system, characterized in that: include: A memory and a processor, wherein the memory stores a computer program, and the processor executes the control method according to claim 1, 2, 4 or 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method of claim 1, 2, 4 or 5.

9. A computer program product, characterized in that The invention comprises a computer program / instruction, which implements the control method of claim 1, 2, 4 or 5 when executed by a processor.

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