A circuit implementation method for hardware acceleration of trigonometric functions

Abstract

This invention discloses a hardware-accelerated circuit implementation method for trigonometric functions, comprising: a single-precision floating-point input preprocessing circuit for preprocessing the single-precision floating-point input x of the trigonometric function to obtain the corresponding subinterval of x; and a coefficient lookup table circuit for performing a two-level lookup based on the corresponding subinterval of x to obtain the quadratic function coefficients C0, C1, and C2 of the corresponding subinterval from the coefficient storage table. 2； The multiply-accumulate circuit performs radix-4 Booth compression encoding on x and uses a three-level Wallace tree structure for parallel computation to obtain a fixed-point calculation result. The post-processing circuit performs rounding and normalization operations on the fixed-point calculation result to obtain a floating-point output value. This invention relates to the field of computer hardware acceleration technology, solving the technical problem of the difficulty in balancing real-time performance, high accuracy, and low resource consumption in traditional trigonometric function calculation methods.

Description

Technical Field

[0001] This invention belongs to the field of computer hardware acceleration technology, specifically a circuit implementation method for hardware acceleration of trigonometric functions. Background Technology

[0002] Trigonometric functions (such as sine, cosine, arctangent, etc.) are widely used in many fields and are the basic operations of digital computing. However, due to their nonlinear complexity, traditional software computing is difficult to meet the real-time, high-precision and low-power requirements of embedded systems and resource-constrained hardware environments.

[0003] For example, while lookup table methods are simple to implement and fast, the number of lookup entries and the size of the table increase rapidly when dealing with high-precision or large-scale computational problems. This not only increases the storage burden but also makes it difficult to dynamically adjust the computational precision. Furthermore, lookup table methods cannot effectively handle input values ​​outside the preset range, usually requiring additional logic to support such cases. The precision of the CORDIC algorithm is limited by the number of iterations; for high-precision computational needs, more iterations are required, leading to significant latency. Additionally, the fixed-point calculations and shift operations involved in the CORDIC algorithm may introduce rounding errors, which can become limiting factors in high-precision scenarios. In polynomial approximation methods, the computational complexity increases significantly when using higher-order polynomials, potentially leading to increased hardware latency and resource consumption. Moreover, the error distribution of polynomial approximation methods is difficult to control uniformly, resulting in precision degradation in certain specific intervals. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art; to this end, the present invention proposes a circuit implementation method for hardware acceleration of trigonometric functions, which is used to solve the problem that traditional trigonometric function calculation methods are difficult to balance in terms of real-time performance, high accuracy and low resource consumption.

[0005] To achieve the above objectives, a first aspect of the present invention provides a circuit implementation method for hardware acceleration of trigonometric functions, comprising:

[0006] The circuit includes a single-precision floating-point input preprocessing circuit, a coefficient lookup table circuit, a multiply-accumulate calculation circuit, and an output post-processing circuit; among which...

[0007] The single-precision floating-point input preprocessing circuit is used to preprocess the single-precision floating-point input x of the trigonometric function to obtain the corresponding sub-interval of x.

[0008] The coefficient lookup table circuit is used to perform a two-level lookup based on the corresponding sub-interval of x, and obtain the quadratic function coefficients C0, C1 and C2 of the corresponding sub-interval from the coefficient storage table; wherein, the data in the coefficient storage table is stored in the SRAM of the chip;

[0009] The multiply-accumulate calculation circuit is used to perform radix-4 Booth compression encoding on x and to perform parallel calculation using a three-level Wallace tree structure to obtain fixed-point calculation results.

[0010] The post-processing circuit is used to round and normalize the fixed-point calculation results to obtain floating-point output values.

[0011] Based on the above technical process, this invention achieves a significant improvement in the accuracy and efficiency of trigonometric function calculations, while effectively reducing resource consumption. Compared with traditional software calculation methods, the method of this invention, with its efficient five-stage pipeline structure and hardware module optimization, can quickly and accurately calculate trigonometric function values, ensuring the real-time performance and smoothness of the system, and completing trigonometric function calculation tasks in a shorter time.

[0012] Furthermore, the preprocessing of the single-precision floating-point input x of the trigonometric function includes:

[0013] A1. Divide the domain of the trigonometric function into several sub-intervals and approximate it using the quadratic function y = C0 + (C1 + C2x)x; where C0 is the coefficient of the constant term, C1 is the coefficient of the linear term, C2 is the coefficient of the quadratic term, x is the input independent variable, and y is the output dependent variable.

[0014] A2 divides the input floating-point independent variable x into an exponent part and a mantissa part, and obtains the corresponding sub-interval of the independent variable x based on the exponent part and the mantissa part.

[0015] Furthermore, the division of the domain of trigonometric functions into several sub-intervals includes:

[0016] A1-1, the domain of the trigonometric function is evenly divided into 512 initial subintervals, resulting in several initial subintervals;

[0017] A1-2, divide the first few initial subintervals and the last few initial subintervals evenly to obtain several smaller intervals;

[0018] A1-3 marks several small intervals and the remaining initial subintervals as several subintervals, thus obtaining several subintervals.

[0019] Furthermore, the uniform division of the first few initial sub-intervals and the last few initial sub-intervals includes:

[0020] The first few initial sub-intervals are further divided evenly with a width of 0.00001, and the last few initial sub-intervals are further divided evenly with a width of 0.001, resulting in several smaller intervals.

[0021] When the input is close to 0, the trigonometric function changes rapidly, requiring more precise segmentation; when the input is close to π / 2 or 1, the curve is relatively flat, requiring a wider interval. Further adjustments to the segmentation strategy for special intervals result in better approximation, effectively reducing overall calculation errors, meeting high-precision calculation requirements, and providing accurate calculation results.

[0022] Furthermore, obtaining the corresponding sub-interval of the independent variable x based on the exponent and the mantissa includes:

[0023] A2-1, using pre-designed interval division rules, obtain the large interval to which the independent variable x belongs based on the exponential part;

[0024] A2-2 utilizes a pre-built small interval indexing mechanism to further narrow down the large interval to a small interval based on the last part, thereby obtaining the small interval index, and then uses the small interval index to find the corresponding sub-interval of the independent variable x.

[0025] Furthermore, the method for obtaining the coefficient storage table includes:

[0026] The coefficients C0, C1, and C2 of the quadratic function in several sub-intervals are calculated using the minimum-maximum error method, and the coefficients of the quadratic function in several sub-intervals are stored in a fixed-point format to obtain a coefficient storage table.

[0027] Furthermore, the circuit implementation employs a five-stage pipeline structure, wherein,

[0028] The first-stage pipeline is used to complete the preprocessing of single-precision floating-point input and table lookup operations to obtain coefficients C0, C1 and C2.

[0029] And, convert the input floating-point variable x to a fixed-point number x';

[0030] The second-stage pipeline is used to obtain C2 and fixed-point number x' from the first-stage pipeline, and calculates C2x' using Booth coding technology and a fixed-point multiplier to obtain the calculation result of C2x'.

[0031] The third-level pipeline is used to obtain C1 and the number of fixed points x' from the first-level pipeline, and to obtain the calculation result of C2x' from the second-level pipeline. The Wallace tree structure is used to perform cumulative calculation to obtain the calculation result of (C1+C2x')x'.

[0032] The fourth-stage pipeline is used to obtain C0 from the first-stage pipeline, obtain the calculation result of (C1+C2x')x' from the third-stage pipeline, perform calculations using a high-precision fixed-point adder and a carry-retaining adder, and store the calculation result in a fixed-point format to obtain the fixed-point calculation result of C0+(C1+C2x')x'.

[0033] The fifth-level pipeline is used to obtain the fixed-point calculation result of C0+(C1+C2x')x' from the fourth-level pipeline, and convert the fixed-point calculation result into a floating-point number to obtain the floating-point output value.

[0034] The five-stage pipeline architecture divides the computation process into five stages: table lookup and floating-point to fixed-point conversion, multiplication, accumulation, final accumulation, and fixed-point to floating-point conversion. Each stage of the pipeline operates independently and is executed in parallel, which greatly improves the computation speed, allows multiple computation tasks to overlap, makes full use of hardware resources, and reduces computation time.

[0035] Furthermore, the conversion of fixed-point calculation results to floating-point numbers includes:

[0036] B1 performs a fixed-point shift operation on the fixed-point calculation result of C0+(C1+C2x)x in the fourth-level pipeline, converting the fixed-point calculation result into a format where the highest bit is 1 and the decimal point is after the highest bit.

[0037] B2 removes the highest bit from the fixed-point calculation result to obtain the converted floating-point mantissa;

[0038] B3, calculate the number of bits to be shifted in the shift operation, and subtract the number of bits to be shifted from the fixed offset value of the floating-point exponent to obtain the floating-point exponent; wherein, the fixed offset value of the floating-point exponent refers to the fixed value defined under the IEEE 754 standard, which is 127;

[0039] B4 marks the sign bit of the fixed-point calculation result as the floating-point sign bit, and combines the floating-point sign bit, the floating-point mantissa, and the floating-point exponent to obtain the converted floating-point number.

[0040] Furthermore, the single-precision floating-point input preprocessing circuit and the coefficient lookup table circuit are used to execute the first-stage pipeline;

[0041] The multiply-accumulate calculation circuit is used to execute the second to fourth stage pipeline;

[0042] The post-processing circuit is used to execute the fifth stage pipeline.

[0043] In the multiply-accumulate circuit, the multiplier uses Booth encoding to reduce the number of operations, incorporates a Wallace tree for parallel processing of partial products to improve multiplication efficiency, employs a fixed-point adder with a 34-bit width to support high-precision calculations, and uses a carry-saving adder (CSA) to reduce latency. These hardware optimizations effectively reduce computational complexity, lower hardware resource consumption, improve computational efficiency, and ensure computational accuracy.

[0044] Compared with the prior art, the beneficial effects of the present invention are:

[0045] Compared with the lookup table method, this invention avoids the large storage space required for large-scale lookup tables by storing coefficients in a fixed-point format in a small space. This is especially advantageous when dealing with high-precision or large-scale calculations, reducing the storage burden and making it more suitable for resource-constrained environments.

[0046] Compared with polynomial approximation methods, the piecewise quadratic function fitting model adopted in this invention, combined with hardware optimization measures such as Booth coding and Wallace tree structure, effectively reduces the complexity of multiplication and accumulation calculations, avoids the high computational complexity and hardware resource consumption problems caused by high-order polynomials, and reduces the latency of hardware implementation.

[0047] Compared with the CORDIC algorithm, this invention achieves a better balance between accuracy and latency by using reasonable interval partitioning and coefficient calculation methods, while ensuring high accuracy. It avoids the latency problem caused by the increase in the number of iterations. It is more suitable for application scenarios that require both accuracy and real-time performance. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A schematic diagram of the single-precision floating-point input preprocessing circuit and the floating-point to fixed-point conversion operation in the circuit design provided by the present invention;

[0050] Figure 2 This invention provides an operational schematic diagram of the multiply-accumulate calculation circuit in the circuit design.

[0051] Figure 3 This is a schematic diagram of the operation of the post-processing circuit in the circuit design provided by the present invention;

[0052] Figure 4 Error graph of sine function results obtained using the method of this invention is provided for this invention;

[0053] Figure 5 Error graph of the arctangent function result obtained by the method of the present invention is provided for the present invention;

[0054] Figure 6 This is a schematic flowchart of a circuit implementation method for hardware acceleration of trigonometric functions provided by the present invention. Detailed Implementation

[0055] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0056] Please see Figure 6 The first aspect of this invention provides a circuit implementation method for hardware acceleration of trigonometric functions, comprising:

[0057] The circuit includes a single-precision floating-point input preprocessing circuit, a coefficient lookup table circuit, a multiply-accumulate calculation circuit, and an output post-processing circuit; among which...

[0058] The single-precision floating-point input preprocessing circuit is used to preprocess the single-precision floating-point input x of the trigonometric function to obtain the corresponding sub-interval of x.

[0059] The coefficient lookup table circuit is used to perform a two-level lookup based on the corresponding sub-interval of x, and obtain the quadratic function coefficients C0, C1 and C2 of the corresponding sub-interval from the coefficient storage table; wherein, the data in the coefficient storage table is stored in the SRAM of the chip;

[0060] The multiply-accumulate calculation circuit is used to perform radix-4 Booth compression encoding on x and to perform parallel calculation using a three-level Wallace tree structure to obtain fixed-point calculation results.

[0061] The post-processing circuit is used to round and normalize the fixed-point calculation results to obtain floating-point output values.

[0062] Trigonometric functions (such as sine, cosine, and arctangent) are mathematically nonlinear functions, and direct calculation is costly. This invention divides their domain into multiple small intervals, each of which is approximated by a fitted quadratic function: y = C0 + (C1 - C2·x)·x; where C0 is the coefficient of the constant term, C1 is the coefficient of the linear term, C2 is the coefficient of the quadratic term, and x is the input variable, which participates in the calculation after floating-point to fixed-point conversion.

[0063] In this embodiment, the coefficients C0, C1, and C2 for each interval are determined by the following process:

[0064] First, based on the characteristics of the function curve's variation, the domain is divided into several subintervals:

[0065] For the sine and cosine functions, the domain is... The domain is divided into 512 intervals, each with a width of 0.001953125; the domain of the arctangent function is [0,1], and it is also divided into 512 intervals.

[0066] Then, the first few initial sub-intervals (i.e., the sub-intervals where the input is close to 0) are further divided evenly with a width of 0.00001. The latter few initial sub-intervals (i.e., for sine and cosine functions, the sub-intervals where the input is close to 0) are then further divided. When the input of the arctangent function is close to 1, several sub-intervals are further divided evenly with a width of 0.001 to obtain several smaller intervals;

[0067] Mark several small intervals and the remaining initial sub-intervals (i.e., excluding the first few initial sub-intervals and the last few initial sub-intervals) as several sub-intervals to obtain several sub-intervals;

[0068] Next, the coefficients are calculated using the minimum-maximum error method:

[0069] We construct an error function to measure the sum of squared deviations between the sampled values ​​and the fitted function, and find the parameter value that minimizes the error function. In the mathematical derivation, assuming there are n sampling points within the interval, the error function is defined as: Among them, y i =sin(x) i () represents the actual function value;

[0070] Then, partial derivatives of the error function with respect to the parameters are taken and set to zero to solve the system of equations, obtaining a set of coefficients C0, C1, C2 corresponding to each sub-interval of the fitted quadratic function; then, the coefficients are stored in a fixed-point format to obtain a coefficient storage table corresponding to each coefficient, so as to reduce storage space and reading time.

[0071] Next, the hardware design employs a five-stage pipeline architecture to ensure efficient parallel computing:

[0072] The first-level pipeline performs table lookup and floating-point to fixed-point conversion:

[0073] The input floating-point independent variable x is divided into an exponent part and a mantissa part. Then, the large interval to which the independent variable x belongs is obtained according to the exponent part using a pre-designed interval partitioning rule. The large interval is further reduced to a small interval according to the mantissa part using a pre-built small interval indexing mechanism to obtain the small interval index. The corresponding sub-interval of the independent variable x is then obtained using the small interval index.

[0074] Specifically, the process first extracts the 8-bit exponent from the input floating-point number. Then, based on the exponent value, the independent variable x is mapped to a corresponding large interval using pre-designed interval partitioning rules. For example, if the exponent is greater than a certain threshold (e.g., 150), it indicates that the independent variable x is large and belongs to the high interval; if the exponent is less than 150, it indicates that the independent variable x is small and belongs to the low interval. Next, a pre-built small interval indexing mechanism is used for subsequent operations. Based on the range of mantissa values, the mantissa is assigned to a fixed number of small intervals. For example, for a 23-bit mantissa, assuming it is mapped to 256 small intervals, the specific small interval in which the independent variable x is located can be determined by the mantissa value, and then the corresponding sub-interval of the independent variable x can be determined using the small interval index.

[0075] Next, the quadratic function coefficients C0, C1, and C2 for the corresponding sub-intervals are obtained from the coefficient storage table using the lookup table method;

[0076] Then, the input floating-point argument x is converted to a fixed-point number x' to adapt to subsequent hardware operations;

[0077] The second-stage pipeline performs multiplication calculations: it obtains C2 and fixed-point number x' from the first-stage pipeline, uses a fixed-point multiplier to calculate the result, retains the high-order bits to improve precision, and introduces Booth encoding to optimize the generation of partial products, reducing the complexity of the multiplier, and obtains the calculation result of C2x'.

[0078] The third-stage pipeline performs cumulative calculations: it obtains C1 and fixed-point number x' from the first-stage pipeline and the calculation result of C2x' from the second-stage pipeline. It then uses the Wallace tree structure to perform cumulative calculations, further improving the operation speed, and obtains the calculation result of (C1+C2x')x'. The calculation result is then directly passed to the next stage, reducing register read / write latency.

[0079] The fourth-level pipeline performs the final accumulation: obtain C0 from the first-level pipeline, obtain the calculation result of (C1+C2x')x' from the third-level pipeline, perform calculation using a high-precision fixed-point adder and a carry-retaining adder, and store the calculation result in a fixed-point format to obtain the fixed-point calculation result of C0+(C1+C2x')x';

[0080] The fifth-stage pipeline performs fixed-point to floating-point conversion: converting the fixed-point calculation result into a floating-point output, using a priority encoder to determine the most significant bit, adjusting the exponent, and generating a floating-point number conforming to the IEEE 754 standard through shifting and truncation processing, thus obtaining the floating-point output value.

[0081] like Figure 1As shown, the single-precision floating-point input preprocessing circuit and coefficient lookup table circuit play a crucial role in data preprocessing and coefficient acquisition during the entire trigonometric function hardware acceleration process. Their function is to convert the input floating-point numbers into a fixed-point format suitable for subsequent calculations and simultaneously acquire the corresponding quadratic function coefficients. The specific operation flow is as follows:

[0082] First, since floating-point representation has a larger range than fixed-point, an appropriate fixed-point format needs to be selected during conversion. This means determining the bit width of the fixed-point number, specifically how many bits the integer and fractional parts will occupy, and whether a sign bit is needed for the calculation. For example, based on the specific requirements of trigonometric function calculations and the actual hardware resources, the Q1.31 format can be selected, which includes 1 sign bit, 1 integer bit, and 31 fractional bits.

[0083] Then, the received floating-point number is decomposed into three parts according to the standard format: the sign bit, the exponent part, and the mantissa part. Taking the common 32-bit IEEE 754 standard floating-point number as an example, its highest bit (31st bit) is the sign bit, which is used to indicate whether the number is positive or negative; the 8 bits from the 30th bit to the 23rd bit are the exponent part, which is used to determine the position of the decimal point; and the 23 bits from the 22nd bit to the least significant bit (0th bit) are the mantissa part, which contains the significant digit information.

[0084] Next, the difference between the exponent of the floating-point number and the exponent specified by the selected fixed-point format is calculated. This difference determines the number of bits in the mantissa that need to be shifted. This is done to accurately adjust the significant digits of the floating-point number to their appropriate positions in the fixed-point number for subsequent fixed-point calculations. For example, if the exponent of the floating-point number is large, the mantissa needs to be shifted to the right by the corresponding number of bits, moving the decimal point to the appropriate position on the left; conversely, if the exponent of the floating-point number is small, the mantissa can be shifted to the left.

[0085] Finally, the sign bit is combined with the mantissa after the shift operation to obtain the final fixed-point number. The merging and conversion process usually involves rounding or truncation operations because floating-point numbers have a high representation range, and converting them to fixed-point numbers may result in the loss of some precision in some cases.

[0086] Simultaneously, a lookup table circuit is used to perform floating-point lookup table operations: by utilizing the interval information determined by the exponent and mantissa of the input floating-point number, the quadratic function coefficients C0, C1, and C2 required for subsequent multiplication and accumulation calculations are quickly searched in a pre-stored coefficient table.

[0087] Figure 2This is a flowchart of the multiply-accumulate calculation circuit. Based on the characteristics of quadratic functions, the fitted quadratic function is designed as a two-stage multiply-accumulate structure at the hardware circuit level, decomposing the calculation process into multiplication and accumulation operations, so as to facilitate subsequent optimization using efficient algorithms.

[0088] First, the Wallace Tree algorithm is used to perform the multiply-accumulate operation. The Wallace Tree algorithm is widely used in computing to implement multiplication or parallel multiplication and addition. Its basic idea is to transform a series of multiplication operations into parallel addition and subtraction operations, thereby achieving highly parallelized multiply-accumulate operations in hardware. In this way, multiple addition operations can be executed in parallel within a single clock cycle, greatly improving computational efficiency.

[0089] To further improve the efficiency of multiplication and accumulation, Booth encoding technology is introduced. Booth encoding is a technique specifically designed to optimize binary multiplication operations and plays an important role in hardware multiplication optimization in high-performance computing. Its core principle is to use different bit block states to represent the information of adjacent bits, thereby encoding the multiplier, which reduces the number of multiplications that actually need to be performed in the multiplier and lowers the computational complexity.

[0090] Specifically, in this embodiment, the binary number is divided into multiple bit blocks, each consisting of several consecutive bits. For signed Booth encoding, additional sign bits are typically added at both ends to handle positive and negative numbers. For each bit block, a Booth code is generated based on its bit pattern, where consecutive 00 states indicate no operation (equivalent to multiplying by 0), 01 states indicate addition, and 10 states indicate subtraction. The corresponding operation is performed according to the encoding state, and this process is repeated for each bit block until all bit blocks are processed. This effectively reduces the number of multiplier operations and improves computation speed.

[0091] The two-level multiplication and accumulation operations are evenly distributed over three clock cycles to achieve efficient pipelined computation.

[0092] In the first cycle, the Booth algorithm based on the multiplicand is first completed to generate the partial product of the Wallace tree. At the same time, the calculation of the partial product of the three levels (l0, l1, l2) is implemented. Finally, the calculated partial product is output to the Carry Save Adder (CSA) 4-2 (4 inputs, 2 outputs) and the result is generated.

[0093] In the second cycle, the Booth and Wallace tree level partial product 4-2 compression calculations for the second multiply-accumulate are performed using a 34-bit full adder. In this cycle, Booth encoding and the Wallace tree algorithm are further used to process the partial product, while a high-precision 34-bit full adder is used for addition calculations, gradually completing some calculation tasks in the two-level multiply-accumulate and advancing the calculation process.

[0094] In the third cycle, the final calculations of the CSA4-2 adder and the 34-bit full adder are performed. Following the preparation in the first two cycles, the final accumulation calculation is completed in this cycle, yielding the final multiply-accumulate result. It should be noted that the Wallace tree with three levels can calculate a maximum of 16 partial products (pp0-pp15) and generate a carry partial product (pp16). However, since the maximum bit width of the multiplication method in this invention is 30 bits, only 15 partial products are needed to complete the operation. Therefore, pp15 is replaced with all zeros in this process to ensure the accuracy and efficiency of the calculation.

[0095] Figure 3 This is a fixed-point / floating-point normalization flowchart. Its purpose is to convert the fixed-point calculation results obtained from two stages of multiplication and addition into a single-precision floating-point format that conforms to the IEEE standard. This is the fifth stage of the pipeline, and its specific operation steps are as follows:

[0096] First, a shift operation is performed on the fixed-point calculation result to adjust its representation format, making the highest bit 1 and the decimal point after the highest bit. Then, the high 23 bits of the fixed-point number are removed to obtain the converted floating-point mantissa. For example, if the original fixed-point number is [10101010101010101010101010101010] (this is just an example; the actual bit width and value depend on the calculation result), it can be shifted to [1.01010101010101010101010101010] (assuming the decimal point is after the highest bit 1). At this time, the high 23 bits [01010101010101010101010] are the floating-point mantissa (hidden bits are not considered for now). This step is the basis for converting a fixed-point number to a floating-point number, adjusting the format to match the mantissa representation of the floating-point number.

[0097] Next, the number of bits shifted in the previous step is calculated and subtracted from the offset of the floating-point exponent to obtain the final floating-point exponent. In the IEEE standard single-precision floating-point number, the exponent is represented using offset binary. By calculating the number of bits shifted, the magnitude of the floating-point exponent can be determined to accurately represent the range of values. For example, if the number of bits shifted is 5 (meaning the decimal point of the fixed-point number is moved 5 places to the left), and the offset of the floating-point exponent is 127 (the exponent offset of the IEEE 754 standard single-precision floating-point number), then the calculated floating-point exponent is 127 + 5 = 132 (converted to binary representation and filled into the exponent bits). This step ensures that the floating-point number correctly reflects the magnitude of the original fixed-point number and is one of the key steps in achieving accurate fixed-point to floating-point conversion.

[0098] The sign bit of a fixed-point number is directly used as the sign bit of the converted floating-point number. This simple and direct correspondence ensures the consistency of numerical sign during the conversion process. For example, if the sign bit of a fixed-point number is 0, representing a positive number, then the sign bit of the converted floating-point number is also 0; if the sign bit of a fixed-point number is 1, representing a negative number, then the sign bit of the floating-point number is also 1. This helps maintain the logical consistency of data between different numerical representations and avoids calculation errors caused by incorrect sign conversion.

[0099] Finally, the determined sign bit, exponent, and mantissa are merged according to the IEEE standard single-precision floating-point format to obtain the final floating-point number. During the merging process, the floating-point encoding standard must be strictly followed to ensure the correct position and representation of each part. For example, the 1 sign bit, 8 exponent bits (such as the 8-bit binary representation of the previously calculated 132), and 23 mantissa bits (such as the previously determined [01010101010101010101010], with consideration given to hidden bits, etc.) are combined sequentially to form a 32-bit floating-point number. This completes the conversion from a fixed-point number to an IEEE standard floating-point number, enabling the calculation result to be correctly recognized and used in a wide range of computing environments.

[0100] Throughout the conversion process, since the mantissa portion of a floating-point number has only 24 bits (1 hidden bit and 23 floating-point mantissa bits), while in this embodiment the decimal point of a fixed-point number is fixed at the highest bit, if the bit width of the fixed-point number is greater than 24 bits, some precision will inevitably be lost after the conversion. Therefore, rounding or truncation operations are usually required to handle the extra bits. Depending on the specific rounding strategy (such as rounding to the nearest even number, rounding to zero, etc.), the mantissa portion is adjusted to complete the conversion while ensuring a certain level of precision. A reasonable rounding strategy can effectively reduce the accumulation of errors caused by the conversion and improve the reliability of the calculation results.

[0101] Meanwhile, in the fifth cycle of the pipeline execution cycle, the conversion from fixed point to floating point is achieved through the priority encoder and shift logic. This also involves floating point normalization and rounding operations, which reflects the hardware design's optimization of the conversion process in terms of time and space. This ensures that the conversion operation can be completed efficiently and accurately, matching the rhythm of the entire computing pipeline and improving the overall performance of the system.

[0102] Please see Figure 4 - Figure 5 The second aspect of the present invention provides a performance evaluation comparison example of hardware acceleration for trigonometric functions, including:

[0103] The trigonometric function hardware instructions of the C2000 series processor from Texas Instruments (TI), used in motor control, were selected as a comparison object, and the method of this invention was compared with the method of the present invention in terms of computational accuracy and efficiency. Under the same test environment, a large amount of test data was input to both methods, and their respective calculation results were obtained. The error between these results and the standard results (using the CPU calculation results under the x86 architecture as the standard result) was calculated to evaluate the computational accuracy. Simultaneously, the number of clock cycles required to execute the instructions and the system clock frequency were recorded, and the execution time was calculated to evaluate the computational efficiency. The comparison results are shown in the figure below. Figure 4 , Figure 5 As shown:

[0104] In terms of efficiency, the C2000's trigonometric function hardware instruction execution requires 4 system clock cycles with a system clock frequency of 100MHz and an execution time of 40ns; while the system clock frequency of this invention is 400MHz, the instruction execution requires five cycles and an execution time of 12.5ns, reducing the execution time by 68.75%, and theoretically improving efficiency by up to 220%.

[0105] Regarding result accuracy, 81.35% of the results in the million-input level test were consistent with C2000. The CPU calculation results under the x86 architecture were introduced as a standard reference, and the results of this invention were closer to the standard results in inconsistent data. Since the [0,1] interval of floating-point numbers is not uniformly distributed, with far more numbers near 0 than near 1, 50,000 valid input data points within the defined domain were used for testing. Figure 4 The red curve in the figure represents the error between the present invention and the standard result, while the blue curve represents the error between TIC2000 and the standard result. It can be seen that in most cases, the blue curve covers the red curve, that is, the error of TIC2000 is greater than that of the present invention.

[0106] Due to the different design and implementation algorithms of the two parties, the error of C2000 is biased towards the upper part of the x-axis, while the error of the design fluctuates to the left and right sides of the x-axis. Therefore, the blue curve in the second half of the curve only covers the part of the red curve above the x-axis. However, from the comparison of the absolute value of the error in the test results, it can be seen that 68.89% of the test results of the sine function instruction of the present invention are consistent with C2000, 27.46% of the test results are more accurate than C2000, and only 3.65% of the test results are less accurate than C200028x49c, which proves the correctness and effectiveness of the present invention.

[0107] exist Figure 5 In the comparison results of the arctangent function, the red curve represents the error between the present invention and the standard result, while the blue curve represents the error between TIC2000 and the standard result. The input interval is the same for both, [0,1]. In most cases, the blue curve covers the red curve. Due to the different design and implementation algorithms of the two, the error of TI is biased below the x-axis, while the error of the present invention fluctuates to the left and right of the x-axis. Therefore, the second half of the blue curve only covers the part of the red curve below the x-axis. However, from the comparison of the absolute value of the error in the test results, it can be seen that the arctangent function instruction of the present invention is consistent with C2000 in 63.54% of the test results, has a higher accuracy than C2000 in 35.22% of the test results, and has a lower accuracy than C2000 in only 1.24% of the test results.

[0108] Some of the data in the above formula are calculated by removing dimensions and taking their numerical values. The formula is the closest to the real situation obtained by software simulation of a large amount of collected data. The preset parameters and preset thresholds in the formula are set by those skilled in the art according to the actual situation or obtained through simulation of a large amount of data.

[0109] Working principle of the invention:

[0110] First, the domain of the trigonometric functions is divided into several sub-intervals and approximated using the quadratic function y = C0 + (C1 + C2x)x. The sine and cosine functions are in [1, π / 2], and the arctangent function is in [0, 1]. 512 initial sub-intervals are evenly divided first, and then the interval width is adjusted according to the changes in the function curve. The intervals are finely divided in the rapidly changing regions and the width is increased in the regions with gentle changes, so that the quadratic function can be better fitted and the final sub-intervals are determined.

[0111] Then, the quadratic function coefficients C0, C1 and C2 of several sub-intervals are calculated using the minimum maximum error method, and the quadratic function coefficients of several sub-intervals are stored in a fixed-point format to obtain three independent coefficient storage tables.

[0112] Finally, a five-stage pipeline structure is designed to calculate the output values ​​within several sub-intervals, obtaining the trigonometric function calculation results. The first stage prepares the data, and subsequent stages sequentially perform multiplication, accumulation, final accumulation, and fixed-point to floating-point conversion. Hardware optimizations (such as high-precision adders) and algorithms (Booth coding, Wallace tree algorithm) are used to improve speed and accuracy, fully utilize hardware resources, and improve the real-time performance of the method.

[0113] The above embodiments are only used to illustrate the technical methods of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical methods of the present invention without departing from the spirit and scope of the technical methods of the present invention.

Claims

1. A method of circuit implementation for hardware acceleration of trigonometric functions, characterized by, The circuit comprises: a single-precision floating-point input preprocessing circuit, a coefficient lookup table circuit, a multiply-accumulate calculation circuit and an output post-processing circuit, wherein the single-precision floating-point input preprocessing circuit is configured to preprocess a single-precision floating-point input x of a trigonometric function to obtain a corresponding subinterval of x; wherein the preprocessing of the single-precision floating-point input x of the trigonometric function comprises: A1, dividing the domain of the trigonometric function into a plurality of subintervals, and approximating the trigonometric function by using a quadratic function y = C0 + (C1 + C2x)x; wherein C0 is a constant term coefficient, C1 is a first-order term coefficient, C2 is a second-order term coefficient, x is an input independent variable, and y is an output dependent variable; A2, dividing the input floating-point independent variable x into an exponent part and a mantissa part, and obtaining the corresponding subinterval of the independent variable x according to the exponent part and the mantissa part; the coefficient lookup table circuit is configured to perform two-level lookup according to the corresponding subinterval of x to obtain the quadratic function coefficients C0, C1 and C2 of the corresponding subinterval from a coefficient storage table; wherein the data in the coefficient storage table is stored in the SRAM of the chip; the multiply-accumulate calculation circuit is configured to perform base-4 Booth compression encoding on x, and perform parallel calculation by using a three-level Wallace tree structure to obtain a fixed-point calculation result; the post-processing circuit is configured to perform rounding and normalization operations on the fixed-point calculation result to obtain a floating-point output value.

2. The circuit implementation method of hardware acceleration of trigonometric functions according to claim 1, characterized in that, the dividing of the domain of the trigonometric function into a plurality of subintervals comprises: A1-1, uniformly dividing the domain of the trigonometric function into 512 initial subintervals to obtain a plurality of initial subintervals; A1-2, uniformly dividing the first plurality of initial subintervals and the last plurality of initial subintervals to obtain a plurality of small intervals; A1-3, marking the plurality of small intervals and the remaining initial subintervals as a plurality of subintervals to obtain a plurality of subintervals.

3. The circuit implementation method of hardware acceleration of trigonometric functions according to claim 2, characterized in that, the uniformly dividing of the first plurality of initial subintervals and the last plurality of initial subintervals comprises: continuing to uniformly divide the first plurality of initial subintervals with a width of 0.00001, and continuing to uniformly divide the last plurality of initial subintervals with a width of 0.001 to obtain a plurality of small intervals.

4. The circuit implementation method of hardware acceleration of trigonometric functions according to claim 1, characterized in that, the obtaining of the corresponding subinterval of the independent variable x according to the exponent part and the mantissa part comprises: A2-1, obtaining the large interval to which the independent variable x belongs according to the exponent part by using a pre-designed interval division rule; A2-2, further reducing the large interval to a small interval according to the mantissa part by using a pre-constructed small interval index mechanism, obtaining a small interval index, and obtaining the corresponding subinterval of the independent variable x by using the small interval index.

5. The circuit implementation method of hardware acceleration of trigonometric functions according to claim 1, characterized in that, the obtaining method of the coefficient storage table comprises: calculating the quadratic function coefficients C0, C1 and C2 of the plurality of subintervals by using the least maximum error method, and storing the quadratic function coefficients of the plurality of subintervals in a fixed-point format to obtain the coefficient storage table.

6. The circuit implementation method of hardware acceleration of trigonometric functions according to claim 1, characterized in that, the circuit implementation adopts a five-stage pipeline structure, wherein the first stage pipeline is configured to complete single-precision floating-point input preprocessing and lookup table operation to obtain the coefficients C0, C1 and C2; and, the input floating-point independent variable x is converted into a fixed-point number x' by using a fixed-point conversion circuit; The second pipeline is configured to obtain C2 and the fixed-point number x' of the first pipeline, calculate C2x' by using a Booth coding technique and a fixed-point multiplier, and obtain a calculation result of C2x'; The third pipeline is configured to obtain C1 and the fixed-point number x' of the first pipeline, obtain the calculation result of C2x' of the second pipeline, perform accumulation calculation by using a Wallace tree structure, and obtain a calculation result of (C1+C2x')x'; The fourth pipeline is configured to obtain C0 of the first pipeline, obtain the calculation result of (C1+C2x')x' of the third pipeline, perform calculation by using a high-precision fixed-point adder and a carry-save adder, and store the calculation result in a fixed-point format to obtain a fixed-point calculation result of C0+(C1+C2x')x'; The fifth pipeline is configured to obtain the fixed-point calculation result of C0+(C1+C2x')x' of the fourth pipeline, convert the fixed-point calculation result into a floating-point number, and obtain a floating-point output value.

7. The circuit implementation method of hardware acceleration of trigonometric functions according to claim 6, characterized in that, The conversion of the fixed-point calculation result into the floating-point number comprises: B1, performing a fixed-point shift operation on the fixed-point calculation result of C0+(C1+C2x')x' of the fourth pipeline, and converting the fixed-point calculation result into a format in which a highest bit is 1 and a decimal point is after the highest bit; B2, removing the highest bit from the fixed-point calculation result to obtain a converted floating-point mantissa; B3, calculating a shift bit number in the shift operation, and subtracting the shift bit number from a floating-point exponent fixed offset value to obtain a floating-point exponent; the floating-point exponent fixed offset value is a fixed value defined in the IEEE754 standard, and is 127; B4, marking a sign bit of the fixed-point calculation result as a floating-point sign bit, and combining the floating-point sign bit, the floating-point mantissa, and the floating-point exponent to obtain a converted floating-point number.

8. The circuit implementation method of hardware acceleration of trigonometric functions according to claim 1, characterized in that, The single-precision floating-point input preprocessing circuit and the coefficient lookup table circuit are configured to perform the first pipeline; The multiply-accumulate calculation circuit is configured to perform the second pipeline to the fourth pipeline; The post-processing circuit is configured to perform the fifth pipeline.

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