A method of controlling task deployment of a computer

Abstract

The application provides a task deployment method of a control computer, and belongs to the technical field of embedded computing systems and devices in unmanned aerial vehicles, and specifically comprises the following steps: deploying multiple tasks in the control computer on a multi-core general-purpose processor; core 0 performs an upgrade task through an RS422 interface, and the RS422 interface in communication with core 0 is connected with a PS end through HP0; core 1 performs data transceiving and completes data calculation through the RS422 interface, and the RS422 interface in communication with core 1 is connected with the PS end through HP1; core 2 performs data transceiving and completes data calculation through the RS422 interface, and the RS422 interface in communication with core 2 is connected with the PS end through HP2; and core 3 performs a parameter binding task. In a synchronous system, when multiple cores access an RS422 bus in parallel, the function of fast and efficient data reading and data sending is realized.

Description

Technical Field

[0001] The present application relates to the field of embedded computing systems and devices in unmanned aerial vehicles, and more particularly to a method for deploying tasks for a control computer. Background Art

[0002] Embedded computing systems in unmanned aerial vehicles (UAVs) are rapidly developing, highly integrated, and technologically complex. Each subsystem in the vehicle operates at a specific rhythm or cycle, and the acquisition and control of various interfaces within it have strict timing requirements. This information is highly time-dependent and is referred to as time-sensitive information.

[0003] Missile-borne aircraft have strict timing requirements for data acquisition and control across various interfaces, requiring the control computer to complete data acquisition and calculations in a short period of time. This places high demands on embedded computer systems. Currently, faced with the data pressure of numerous interfaces accessing data simultaneously, missile-borne aircraft control computers employ multi-core queuing by adding system semaphores within the system software. This approach allows for normal interface data collection, but wastes system resources and increases core runtime. Summary of the Invention

[0004] In view of this, the present application provides a task deployment method for a control computer, which solves the problems in the prior art and realizes fast and efficient data reading and data sending functions when multiple cores access the RS422 bus in parallel in a synchronous system.

[0005] The present application provides a method for controlling computer task deployment using the following technical solutions:

[0006] A method for controlling a task of a computer comprises the following steps:

[0007] Deploy multiple tasks in the control computer on a multi-core general-purpose processor, which includes core 0, core 1, core 2, and core 3;

[0008] Connect the RS422 interface of the processor PL end in the control computer to the PS end in the processor through the HP interface controller. Core 0 performs the upgrade task through the RS422 interface. The RS422 interface that communicates with Core 0 is connected to the PS end through HP0.

[0009] Core 1 receives and sends data and completes data processing via the RS422 interface. The RS422 interface communicating with Core 1 is connected to the PS end via HP1.

[0010] Core 2 receives and sends data through the RS422 interface and completes data processing. The RS422 interface that communicates with the core 2 task is connected to the PS end through HP2.

[0011] Core 3 performs parameter binding tasks.

[0012] Optionally, the task external interface control domains of core 0, core 1, core 2, and core 3 are composed of their own AXI HP controllers and UART IPs managed by each core. Each AXI HP controller is bound to a core separately and is set according to the user application.

[0013] Optionally, the data buffer in the RS422 interface controller is a dual-port RAM. When the RS422 interface receives a complete data packet, it automatically triggers the data sending function of the HP interface, and writes the data packet in the RS422 dual port to the DDR3 memory on the PS side at one time, completing the data reading function; when a core needs to send data, it writes the data to the corresponding storage area of ​​DDR3 at one time, and notifies the corresponding HP interface controller to start the RS422 write operation through a discrete signal, and writes the data in the DDR3 memory to the RS422 write buffer at one time, completing the data sending function.

[0014] Optionally, Core 1 runs guidance and control tasks and communicates with the seeker, servo control unit, autonomous decision-making component and static pressure sensor equipment of the external system through the RS422 interface.

[0015] Optionally, Core 2 runs an integrated navigation mission and communicates with the inertial measurement unit and satellite navigation receiver equipment of an external system through the RS422 interface.

[0016] Optionally, the task cycles on core 0, core 1, core 2 and core 3 are consistent, with a cycle of 2.5-10ms. The control computer synchronizes the timing with the external system through the synchronization pulse, so that the synchronization pulse of the control computer and the cycle process frequency of the processor core are consistent.

[0017] Optionally, core 1, core 2, and core 3 are synchronized with core 0 through inter-core interrupts, and core 0, core 1, core 2, and core 3 perform inter-core message communication through message queues.

[0018] In summary, this application has the following beneficial technical effects:

[0019] This method enables fast and efficient data reading and transmission when multiple cores access the RS422 bus in parallel, resolving conflicts when multiple cores access external devices simultaneously through a single AXI interface, addressing jitter in task execution time, and addressing inefficient RS422 interface access. This method is applicable to task deployment and interface access in multi-core integrated control computers within unmanned aerial vehicle control systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 Schematic diagram of the method for deploying tasks to control a computer. DETAILED DESCRIPTION

[0022] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0023] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0024] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0025] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0026] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples. However, one skilled in the art will appreciate that the aspects described can be practiced without these specific details.

[0027] An embodiment of the present application provides a method for deploying tasks to control a computer.

[0028] like Figure 1 As shown, a method for deploying tasks to control a computer includes the following steps:

[0029] Multiple tasks in a control computer are deployed on a multi-core general-purpose processor, which includes core 0, core 1, core 2, and core 3; the RS422 interface of the PL end of the processor in the control computer is connected to the PS end of the processor through an HP interface controller.

[0030] Core 0 performs upgrade tasks through the RS422 interface. The RS422 interface that communicates with core 0 is connected to the PS side through HP0; core 0 does not perform RS422 communication.

[0031] Core 1 sends and receives data and completes data analysis through the RS422 interface. The RS422 interface that communicates with Core 1 is connected to the PS end through HP1. Core 1 runs the guidance and control tasks and communicates with the seeker, servo control unit, autonomous decision-making component and static pressure sensor equipment of the external system through the RS422 interface.

[0032] Core 2 sends and receives data and completes data solution through the RS422 interface. The RS422 interface for communicating with the core 2 task is connected to the PS end through HP2. Core 2 runs the integrated navigation task and communicates with the inertial measurement component and satellite navigation receiver equipment of the external system through the RS422 interface.

[0033] Core 3 performs parameter binding tasks and does not perform RS422 communication.

[0034] The task external interface control domains for cores 0, 1, 2, and 3 each consist of their own AXI HP controller and a UART IP address assigned to each core. Each AXI HP controller is bound to a separate core and configured according to the user application. The UART IP address corresponding to the RS422 interface assigned to core 0 is located in the task external interface control domain of core 0, the UART IP address corresponding to the RS422 interface assigned to core 1 is located in the task external interface control domain of core 1, and the UART IP address corresponding to the RS422 interface assigned to core 2 is located in the task external interface control domain of core 1.

[0035] The data buffer in the RS422 interface controller is a dual-port RAM. When the RS422 interface receives a complete data packet, it automatically triggers the data sending function of the HP interface, and writes the data packet in the RS422 dual port to the DDR3 memory on the PS side at one time, completing the data reading function; when a core needs to send data, it writes the data to the corresponding storage area of ​​DDR3 at one time, and notifies the corresponding HP interface controller to start the RS422 write operation through a discrete signal, and writes the data in the DDR3 memory to the RS422 write buffer at one time, completing the data sending function.

[0036] The task cycles on cores 0, 1, 2, and 3 are consistent, with a period of 2.5-10ms. The control computer synchronizes timing with the external system through synchronization pulses, so that the synchronization pulses of the control computer and the cycle process frequency of the processor core are consistent.

[0037] Core 1, core 2, and core 3 are synchronized with core 0 through inter-core interrupts, and core 0, core 1, core 2, and core 3 communicate with each other through message queues.

[0038] The method of the present application deploys multiple tasks in the control computer on a multi-core general-purpose processor, and the external interface control domain of each core's task is composed of its own AXI HP controller and the UART IP in charge of each core. When the core and the external subsystem perform RS422 data communication, the RS422 interface and the HP interface work together to achieve fast and efficient data reading and data sending functions. The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any technical personnel familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for deploying tasks to control a computer, characterized in that: The steps include: Deploy multiple tasks in the control computer on a multi-core general-purpose processor, which includes core 0, core 1, core 2, and core 3; Connect the RS422 interface of the processor PL end in the control computer to the PS end in the processor through the HP interface controller. Core 0 performs the upgrade task through the RS422 interface. The RS422 interface that communicates with Core 0 is connected to the PS end through HP0. Core 1 receives and sends data and completes data processing via the RS422 interface. The RS422 interface communicating with Core 1 is connected to the PS end via HP1. Core 2 receives and sends data through the RS422 interface and completes data processing. The RS422 interface that communicates with the core 2 task is connected to the PS end through HP2. Core 3 performs parameter binding tasks; The task external interface control domains of cores 0, 1, 2, and 3 are composed of their own AXI HP controllers and the UART IP managed by each core. Each AXI HP controller is bound to a core individually and configured according to the user application. Core 1 runs the guidance and control tasks and communicates with the seeker, servo control unit, autonomous decision-making component and static pressure sensor equipment of the external system through the RS422 interface; Core 2 runs the integrated navigation task and communicates with the inertial measurement unit and satellite navigation receiver equipment of the external system through the RS422 interface.

2. The method for deploying tasks on a control computer according to claim 1, wherein: The data buffer in the RS422 interface controller is a dual-port RAM. When the RS422 interface receives a complete data packet, it automatically triggers the data sending function of the HP interface, and writes the data packet in the RS422 dual port to the DDR3 memory on the PS side at one time, completing the data reading function; when a core needs to send data, it writes the data to the corresponding storage area of ​​DDR3 at one time, and notifies the corresponding HP interface controller to start the RS422 write operation through a discrete signal, and writes the data in the DDR3 memory to the RS422 write buffer at one time, completing the data sending function.

3. The task deployment method for controlling a computer according to claim 1, characterized in that: The task cycles on cores 0, 1, 2, and 3 are consistent, with a period of 2.5-10ms. The control computer synchronizes timing with the external system through synchronization pulses, so that the synchronization pulses of the control computer and the cycle process frequency of the processor core are consistent.

4. The method for deploying tasks of a control computer according to claim 1, wherein: Core 1, core 2, and core 3 are synchronized with core 0 through inter-core interrupts, and core 0, core 1, core 2, and core 3 communicate with each other through message queues.

Images