Multi-thread scheduling method, server and computer system

Abstract

The embodiment of the invention discloses a multi-thread scheduling method, a server and a computer system, which are used for avoiding multi-thread cross-node far-end access and reducing the overhead for running a first thread and a second thread. The method comprises the steps that genetic relationship information between a first thread and a second thread is determined according to first memory access information of the first thread in a first operation stage and second memory access information of the second thread in a second operation stage; determining a first node according to the first memory access information, the second memory access information and the genetic relationship information; determining that the resource metric value of the first node is smaller than a resource threshold value; a processor unit for running the first thread and the second thread is selected from the first node.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a multi-threaded scheduling method, a server, and a computer system. Background Art

[0002] The architecture of computer devices has evolved from a single central processing unit (CPU) to multiple CPUs. As the number of CPUs increases, the computing power of computer devices is no longer a performance bottleneck. Multiple CPUs all access memory, and memory becomes a performance bottleneck.

[0003] The business in the computer system is relatively complex. The computer system distributes multiple threads to different nodes through load balancing to maximize the parallelism of tasks. However, this method of allocating nodes to threads will lead to remote access across nodes, and there is a problem of increased overhead in executing threads. Summary of the invention

[0004] The embodiments of the present application provide a multi-threaded scheduling method, a server, and a computer system for reducing the overhead of executing threads.

[0005] To solve the above technical problems, the present application provides the following technical solutions:

[0006] In the first aspect, an embodiment of the present application provides a multi-threaded scheduling method, including: determining the affinity information between the first thread and the second thread according to the first memory access information of the first thread in the first running stage and the second memory access information of the second thread in the second running stage; determining the first node according to the first memory access information, the second memory access information and the affinity information; determining that the resource measurement value of the first node is less than the resource threshold; and selecting a processor unit for running the first thread and the second thread according to the first node. In the above scheme, since the first node is selected by affinity information, and the processor unit is allocated to the first thread and the second thread on the first node when the resource measurement value of the first node is less than the resource threshold, remote access across nodes of multi-threads is avoided, and the overhead of running the first thread and the second thread is reduced.

[0007] In a possible implementation manner of the first aspect, the affinity between the first thread and the second thread refers to the degree of similarity between memory access information of the first thread and the memory access information of the second thread. The more similar the memory access information of the first thread and the memory access information of the second thread are, the stronger the affinity between the two threads is, and the greater the difference between the memory access information of the first thread and the memory access information of the second thread is, the weaker the affinity between the two threads is.

[0008] In a possible implementation of the first aspect, the method further includes: collecting status information of a performance management unit in the first running phase in a thread switching context, and determining the first memory access information based on the status information of the performance management unit. In the above scheme, a thread is the smallest unit of execution of a computer program, and a server schedules threads through a thread switching context. For example, the server determines through a thread switching context that the current thread switches to a first thread, and the first thread runs in a first phase. In the first running phase, the status information of the performance management unit is collected, and the address and frequency of memory access by the first thread are recorded in the status information of the performance management unit, so that the first memory access information can be obtained.

[0009] In a possible implementation of the first aspect, the collecting of the state information of the performance management unit in the first operation phase, and determining the first memory access information according to the state information of the performance management unit, include: reading the first state information from the register of the performance management unit at the start time of the first operation phase; reading the second state information from the register at the end time of the first operation phase; and determining the first memory access information according to the first state information and the second state information. In the above scheme, when the first thread is started, the server reads the first state information from the register of the performance management unit at the start time of the first operation phase, for example, the first state information may be the first PMU data. The memory access situation when the first thread is started can be tracked through the first state information. When the first thread ends, the server reads the register of the performance management unit again at the end time of the first operation phase to read the second state information, for example, the second state information may be the second PMU data. The memory access situation when the first thread ends can be tracked through the second state information. After the server obtains the first state information when the first thread starts and the second state information when the first thread ends, the server can compare the first state information and the second state information to determine the first memory access information of the first thread in the first operation phase.

[0010] In a possible implementation manner of the first aspect, the first memory access information includes: address information accessed by the first thread; the second memory access information includes: address information accessed by the second thread;

[0011] The method of determining the affinity information between the first thread and the second thread according to the first memory access information of the first thread in the first running stage and the second memory access information of the second thread in the second running stage includes: determining the same memory address range for memory access by the first thread and the second thread according to the address information accessed by the first thread and the address information accessed by the second thread; obtaining the interaction frequency between the first thread and the second thread according to the memory address range; and determining the affinity information between the first thread and the second thread according to the interaction frequency. In the above scheme, after the server obtains the interaction frequency between the first thread and the second thread, the server can determine the affinity between the first thread and the second thread according to the interaction frequency, and the server generates affinity information, which indicates the strength of the affinity between the first thread and the second thread.

[0012] In a possible implementation of the first aspect, the obtaining of the interaction frequency between the first thread and the second thread according to the memory address range includes: merging the first thread and the second thread into a thread affinity group according to the memory address range; obtaining the interaction frequency between the first thread in the thread affinity group when it is running in the first running stage and the second thread in the second running stage, wherein the first running stage and the second running stage overlap in time. In the above scheme, the server can record the interaction frequency between threads in the same thread affinity group, and the server can record the interaction frequency between two threads in the same thread affinity group. For example, the thread affinity group includes the first thread and the second thread, the first thread runs in the first stage, the second thread runs in the second stage, the first running stage and the second running stage overlap in time, and the server records the interaction frequency between the first thread and the second thread in the same thread affinity group.

[0013] In a possible implementation manner of the first aspect, the method further includes: acquiring resource occupancy information of the first node in a first time unit, and determining a resource load metric of the first node according to the resource occupancy information; and / or acquiring resource waiting information of the first node in a second time unit, and determining a resource interference metric of the first node according to the resource waiting information;

[0014] The determining that the resource metric value of the first node is less than a resource threshold includes: determining that the resource metric value of the first node is less than a resource threshold according to a resource load metric of the first node and / or a resource interference metric of the first node.

[0015] In the above scheme, the resource load measurement is used to measure the resource load situation, and the resource interference measurement is used to measure the resource interference situation. The server can determine the resource load size of the first node based on the resource load measurement. The server can determine the resource interference size of the first node based on the resource interference measurement. The server determines that the resource measurement value of the first node is less than the resource threshold based on at least one measurement value among the resource load measurement and the resource interference measurement. Through at least one measurement value among the above resource load measurement and resource interference measurement, multiple methods of determining that the resource measurement value of the first node is less than the resource threshold are implemented. Specifically, the method of determining the resource bottleneck can be selected in combination with the application scenario.

[0016] In a possible implementation of the first aspect, the determination that the resource measurement value of the first node is less than the resource threshold includes: obtaining the processor unit measurement value, and / or memory measurement value, and / or input-output measurement value of the first node; determining that the processor unit measurement value of the first node is less than the computing power threshold, and / or determining that the memory measurement value of the first node is less than the memory threshold, and / or determining that the output-input measurement value of the first node is less than the input-output threshold. In the above scheme, the operating system of the server can generate instructions for scheduling the processor unit or load balancing instructions, and the server can detect the resource information of the first node under the triggering of the above instructions to determine that the resource measurement value of the first node is less than the resource threshold, so that the server can determine that the resource measurement value of the first node is less than the resource threshold according to the instructions of the operating system.

[0017] In a possible implementation of the first aspect, the determining the first node according to the first memory access information, the second memory access information, and the affinity information includes: selecting a node with the most frequent memory access frequency from a task group as the first node according to the first memory access information, the second memory access information, and the affinity information. In the above scheme, the server determines that there is a strong affinity between the first thread and the second thread according to the affinity information between the first thread and the second thread, the server determines to allocate the same node to the first thread and the second thread, and the server selects the node with the most frequent memory access frequency from the task group as the first node.

[0018] In a possible implementation of the first aspect, after selecting a processor unit for running the first thread and the second thread from the first node, the method further includes: determining a thread with a low memory access frequency from the first thread and the second thread according to the memory access frequency of the first thread and the memory access frequency of the second thread; in response to the resource measurement value of the first node being less than the resource threshold, determining not to migrate the thread with a low memory access frequency. In the above scheme, the server can determine the thread with a low memory access frequency from the first thread and the second thread when implementing load balancing, and then the server determines whether there is a resource bottleneck in the first node. When the resource measurement value of the first node is less than the resource threshold, the server does not allow the thread with a low memory access frequency to migrate, so that the first thread and the second thread can be assigned to the same processor unit, thereby avoiding remote access across nodes of multiple threads and reducing the overhead of running the first thread and the second thread.

[0019] In a possible implementation of the first aspect, the method further includes: in response to the resource measurement value of the first node being greater than or equal to the resource threshold, migrating the thread with low memory access frequency from the first node to the second node, the second node being a remote node of the first node. In the above scheme, the server can determine the thread with low memory access frequency between the first thread and the second thread when implementing load balancing, and then the server determines whether there is a resource bottleneck in the first node. When the resource measurement value of the first node is greater than or equal to the resource threshold, it is necessary to migrate the thread with low memory access frequency, migrate the thread with low memory access frequency from the first node to the second node, the second node being a remote node of the first node, and execute the thread with low memory access frequency through the second node to ensure the execution efficiency of the thread currently retained on the first node, so as to achieve a balance between scheduling resources and performance.

[0020] In a possible implementation of the first aspect, the determination that the resource metric value of the first node is less than the resource threshold includes: periodically determining that the resource metric value of the first node is less than the resource threshold based on the resource information of the first node; or, in response to an instruction of a scheduling processor unit or a load balancing instruction, determining that the resource metric value of the first node is less than the resource threshold. In the above scheme, the operating system of the server can generate an instruction of the scheduling processor unit or a load balancing instruction, and the server can detect the resource information of the first node under the triggering of the above instruction to determine that the resource metric value of the first node is less than the resource threshold, so that the server can determine that the resource metric value of the first node is less than the resource threshold according to the instruction of the operating system.

[0021] In a second aspect, an embodiment of the present application further provides a server, including:

[0022] An affinity determination module, configured to determine affinity information between the first thread and the second thread according to first memory access information of the first thread in the first running stage and second memory access information of the second thread in the second running stage;

[0023] a node determination module, configured to determine a first node according to the first memory access information, the second memory access information and the affinity information;

[0024] A resource measurement module, configured to determine that a resource measurement value of the first node is less than a resource threshold;

[0025] A selection module is used to select a processor unit for running the first thread and the second thread according to the first node.

[0026] In the above scheme, first, the affinity information between the first thread and the second thread is determined according to the first memory access information of the first thread in the first running stage and the second memory access information of the second thread in the second running stage, and the affinity information indicates that there is an affinity between the first thread and the second thread. Then, the first node is determined according to the first memory access information, the second memory access information and the affinity information. For example, the first node can be a node in the NUMA architecture. Next, it is determined that the resource measurement value of the first node is less than the resource threshold. The absence of a resource bottleneck can indicate that the resources on the first node can be used by multiple threads. Finally, a processor unit for running the first thread and the second thread is selected from the first node. Since the first node is selected according to the affinity information in the embodiment of the present application, and the processor unit is allocated to the first thread and the second thread on the first node when the resource measurement value of the first node is less than the resource threshold, remote access across nodes of multiple threads is avoided, and the overhead of running the first thread and the second thread is reduced.

[0027] In the second aspect of the present application, the component modules of the server may also execute the steps described in the aforementioned first aspect and various possible implementations. For details, please refer to the aforementioned description of the first aspect and various possible implementations.

[0028] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, wherein instructions are stored in the computer-readable storage medium, and when the computer-readable storage medium is run on a computer, the computer executes the method described in the first aspect above.

[0029] In a fourth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect above.

[0030] In the fifth aspect, an embodiment of the present application provides a communication device, which may include entities such as a terminal device, a server, a computer system or a chip, and the communication device includes: a processor, a memory; the memory is used to store instructions; the processor is used to execute the instructions in the memory, so that the communication device performs a method as described in any one of the above-mentioned first aspects.

[0031] In a sixth aspect, the present application provides a chip system, which includes a processor for supporting a server or a computer system to implement the functions involved in the above aspects, for example, sending or processing the data and / or information involved in the above methods. In one possible design, the chip system also includes a memory, which is used to store program instructions and data necessary for the server or computer system. The chip system can be composed of chips, or it can include chips and other discrete devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of a system architecture applicable to a multi-threaded scheduling method provided in an embodiment of the present application;

[0033] Figure 2 A flowchart diagram of a multi-threaded scheduling method provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of an affinity relationship between threads provided in an embodiment of the present application;

[0035] Figure 4 A schematic diagram of an interaction frequency for communication between threads provided in an embodiment of the present application;

[0036] Figure 5 A schematic diagram of resource load measurement provided in an embodiment of the present application;

[0037] Figure 6 A schematic diagram of resource interference measurement provided in an embodiment of the present application;

[0038] Figure 7 A schematic diagram of the relationship between CPU and memory in a NUMA architecture provided in an embodiment of the present application;

[0039] Figure 8 A schematic diagram of dynamically determining intra-NUMA scheduling or inter-NUMA scheduling provided in an embodiment of the present application;

[0040] Fig. 9 A schematic diagram of an application scenario in which a server provided in an embodiment of the present application is applied to an NMUA architecture;

[0041] Fig.10A schematic diagram of the software and hardware structure of the server provided in the embodiment of the present application;

[0042] Fig.11 A schematic diagram of the structure of a server provided in an embodiment of the present application;

[0043] Fig.12 A schematic diagram of the structure of a computer system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The embodiments of the present application provide a multi-threaded scheduling method, a server, and a computer system for reducing the overhead of executing threads.

[0045] The embodiments of the present application are described below in conjunction with the accompanying drawings.

[0046] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0047] The technical solution of the embodiment of the present application can be applied to a server, which can adopt a non-uniform memory access (NUMA) architecture. The NUMA architecture is a computer system composed of multiple nodes, each of which has a processor unit and memory belonging to the node. From the perspective of a single processor unit, the memory can be divided into local memory and remote memory. The local memory has a small access latency, but limited capacity. The remote memory has a large capacity, but a large access latency, and it is necessary to choose whether to use local memory or remote memory. Due to the complexity of the business in the computer system, the computer system will distribute multiple threads to different nodes through load balancing to maximize the parallelism of the task. However, this method of allocating nodes to threads will result in remote access to nodes across NUMA, and there is a problem of increased overhead in executing threads.

[0048] In order to solve the problem of large thread overhead, the present application embodiment provides a multi-thread scheduling method, such as Figure 1As shown, first, the system architecture applicable to the method provided in the embodiment of the present application is briefly described. The method is executed by a server, and the server includes multiple memories and processor units. Multiple threads are enabled in the server, for example, the multiple threads include a first thread and a second thread. When the thread is running, the server obtains the memory access information of the thread, for example, the server obtains the first memory access information of the first thread in the first running stage and the second memory access information of the second thread in the second running stage, and determines the affinity information between the first thread and the second thread according to the first memory access information and the second memory access information. The server assigns the first thread and the second thread to the same node (i.e., the first node) according to the affinity information between the first thread and the second thread. Next, the server identifies whether there is a resource bottleneck in the first node. When the resource measurement value of the first node is less than the resource threshold, the server selects the processor unit for running the first thread and the second thread according to the first node. In the embodiment of the present application, the server selects the first node through the affinity information, and when the resource measurement value of the first node is less than the resource threshold, the processor unit is assigned to the first thread and the second thread on the first node, thereby avoiding remote access across nodes of multiple threads and reducing the overhead of running the first thread and the second thread.

[0049] The following is an explanation of the technical terms involved in the embodiments of the present application:

[0050] NUMA Architecture:

[0051] The NUMA architecture is a computing system composed of multiple nodes, each of which has its own central processing unit (CPU) and memory. The server can collect memory resource information to determine whether there is a memory resource bottleneck.

[0052] Resource bottleneck:

[0053] Resource bottleneck refers to the inability of the server to provide resources to the business in a timely or sufficient manner. When a resource bottleneck exists on the server, the performance of the business will be impaired. Resource bottlenecks mainly include at least one of the following: computing power bottleneck, memory bottleneck, and input output (IO) bottleneck.

[0054] Performance management unit (PMU) sampling:

[0055] In a computer system, a performance management unit is a hardware unit on an X64 or ARM processor that is used to record the various performance states of the processor when running application code. PMU sampling is a general term for methods that can read hardware performance registers. In a computer system, hardware performance register information is read periodically or in an event-triggered manner, and is bound to the currently running thread to identify the memory access information of the thread, which indicates the running state of the thread.

[0056] For example, the server can read the status information of the PMU register, and the status information of the PMU register includes: ARM statistical profiling extensions (SPE) information, where SPE information refers to the extension information of the general register on the ARM V8 architecture, which records the instruction address, data address, event type, time and other information. Based on this information, the memory access behavior of the thread can be quantified.

[0057] Interference Modeling:

[0058] Interference modeling is a quantitative analysis method for resource interference between threads in a computer system. It evaluates the degree of interference between threads by reading various information in the computer system.

[0059] Load Balancing:

[0060] Load balancing is the act of sharing tasks between multiple CPUs in a computer system. Each CPU has a task queue. Due to the different running times of different tasks, some CPUs are busy while others are idle. Load balancing is responsible for balancing the tasks on different CPUs.

[0061] Remote memory access / local memory access:

[0062] In the NUMA architecture, there are multiple CPU modules, each of which consists of multiple CPUs and has independent local memory, IO slots, etc. Since nodes can be connected and exchange information through interconnect modules, each CPU can access the memory of the entire system. From the perspective of a single CPU, there are local memory units and remote memory units. The speed of accessing local memory will be much higher than the speed of accessing remote memory, where remote memory is the memory of other nodes in the system.

[0063] Resource load metrics and resource interference metrics:

[0064] Resource load measurement measures the resource load by the resource occupation time or cycle. Resource load measurement is used to measure the busyness of resources. The busyness of resources refers to the degree to which resources are utilized. For example, if there are tasks running on the CPU within 1 second, it means that the CPU utilization rate is 100%, and the CPU is very busy or has a high load.

[0065] Resource interference measurement measures resource interference by resource waiting time or cycle. Resource interference measurement is used to measure the degree of resource contention. Resource contention refers to the process of multiple tasks competing for resources when multiple tasks want to use the same resource (such as CPU, memory, IO) at the same time. These multiple tasks compete or interfere with each other on resources such as CPU, memory, IO, etc.

[0066] Next, the multi-thread scheduling method proposed in the embodiment of the present application is described. The method can be applied to the scenario where the server allocates processor units to execute multi-threads. Figure 2 As shown, the multi-threaded scheduling method provided in the embodiment of the present application mainly includes the following steps:

[0067] 201. Determine affinity information between the first thread and the second thread according to first memory access information of the first thread in a first running phase and second memory access information of the second thread in a second running phase.

[0068] Multiple threads are enabled in the server, for example, the multiple threads include a first thread and a second thread. The first thread generates first memory access information when running in the first operation phase, and the second thread generates second memory access information when running in the second operation phase. The server may first collect the first memory access information and the second memory access information, and then determine the affinity information between the first thread and the second thread according to the first memory access information and the second memory access information. Among them, the server may perceive the affinity of the two threads through the memory access information of each of the two threads. The affinity between the threads refers to the similarity of the memory access information of different threads. The more similar the memory access information between the two threads is, the stronger the affinity between the two threads is, and the greater the difference in the memory access information between the two threads is, the weaker the affinity between the two threads is.

[0069] In some embodiments of the present application, in addition to executing the aforementioned step 201, the method provided by the embodiment of the present application further includes:

[0070] A1. In a first running phase in a thread switching context, state information of a performance management unit is collected, and first memory access information is determined according to the state information of the performance management unit.

[0071] Among them, a thread is the smallest unit of computer program execution. The server schedules threads through thread switching context. For example, the server determines that the current thread switches to the first thread through thread switching context. The first thread runs in the first stage. During the first running stage, the status information of the performance management unit is collected. The status information of the performance management unit records the address and frequency of the first thread's memory access, so that the first memory access information can be obtained.

[0072] In some embodiments of the present application, in addition to executing the aforementioned step 201, the method provided by the embodiment of the present application further includes:

[0073] In the second running phase in the thread switching context, state information of the performance management unit is collected, and second memory access information is determined according to the state information of the performance management unit.

[0074] Among them, the server determines that the current thread switches from the first thread to the second thread through the thread switching context. The second thread runs in the second stage. During the second running stage, the status information of the performance management unit is collected. The status information of the performance management unit records the address and frequency of the second thread's memory access, so that the second memory access information can be obtained.

[0075] In some embodiments of the present application, step A1 collects state information of the performance management unit in the first operation phase, and determines first memory access information according to the state information of the performance management unit, including:

[0076] A11, reading first status information from a register of the performance management unit at the beginning of the first operation phase;

[0077] A12, reading the second state information from the register at the end of the first operation phase;

[0078] A13. Determine first memory access information according to the first state information and the second state information.

[0079] When the first thread is started, the server reads first state information from the register of the performance management unit at the beginning of the first running phase. For example, the first state information may be first PMU data. The memory access condition when the first thread is started can be tracked through the first state information.

[0080] When the first thread ends, the server reads the register of the performance management unit again at the end of the first running stage to read the second state information, for example, the second state information can be the second PMU data. The second state information can be used to track the memory access at the end of the first thread. After the server obtains the first state information when the first thread starts and the second state information when it ends, the server can compare the first state information and the second state information to determine the first memory access information of the first thread in the first running stage.

[0081] In some embodiments of the present application, status information of a performance management unit is collected in a second operating phase in a thread switching context, and second memory access information is determined based on the status information of the performance management unit, including: reading third status information from a register of the performance management unit at the start of the second operating phase; reading fourth status information from the register at the end of the second operating phase; and determining the second memory access information based on the third status information and the fourth status information.

[0082] When the second thread starts, the server reads the third state information from the register of the performance management unit at the beginning of the second operation phase. For example, the third state information may be the third PMU data. The third state information may be used to track the memory access when the second thread starts. When the second thread ends, the server reads the register of the performance management unit again at the end of the second operation phase to read the fourth state information. For example, the fourth state information may be the fourth PMU data. The fourth state information may be used to track the memory access when the second thread ends. After the server obtains the third state information when the second thread starts and the second state information when it ends, the server may compare the third state information and the fourth state information to determine the second memory access information of the second thread in the second operation phase.

[0083] In some embodiments of the present application, the first memory access information includes: address information accessed by the first thread; the second memory access information includes: address information accessed by the second thread;

[0084] Step 201 determines the affinity information between the first thread and the second thread according to the first memory access information of the first thread in the first running stage and the second memory access information of the second thread in the second running stage, including:

[0085] B1. Determine, according to address information accessed by the first thread and address information accessed by the second thread, a memory address range that is the same as the memory address range accessed by the first thread and the second thread.

[0086] The server obtains address information accessed by the first thread from the first memory access information, and obtains address information accessed by the second thread from the second memory access information. The server compares the address information accessed by the two threads to determine whether the first thread and the second thread access the same memory address range.

[0087] It can be understood that, in the embodiment of the present application, taking the determination of the affinity between the first thread and the second thread as an example, when the first thread and the second thread access different memory address ranges, the server can re-acquire the other two threads and determine the memory address range that the two threads access the same based on the address information accessed by each thread.

[0088] B2. Obtain the interaction frequency between the first thread and the second thread according to the memory address range.

[0089] When the first thread and the second thread access the same memory address range, the server obtains the interaction frequency between the first thread and the second thread, wherein the interaction frequency is used to indicate the frequency of interaction between the first thread and the second thread during operation, and the interaction frequency can indicate the strength of the affinity between the first thread and the second thread.

[0090] B3. Determine the affinity information between the first thread and the second thread according to the interaction frequency.

[0091] After the server obtains the interaction frequency between the first thread and the second thread, the server may determine the affinity between the first thread and the second thread according to the interaction frequency, and the server generates affinity information, which indicates the strength of the affinity between the first thread and the second thread.

[0092] See also Figure 3 , is a schematic diagram of an affinity relationship between threads provided in an embodiment of the present application. Taking a server running 4 threads, namely thread A, thread B, thread C and thread D as an example, the interaction frequency between threads A and B is 20, the interaction frequency between threads A and C is 5, the interaction frequency between threads A and D is 40, the interaction frequency between threads B and C is 40, the interaction frequency between threads B and D is 5, and the interaction frequency between threads C and D is 20. Based on the above example of interaction frequency between threads, threads A and D, and threads B and C have the strongest affinity, threads A and B, and threads D and C have relatively strong affinity, and threads A and C, and threads B and D have the weakest affinity.

[0093] In some embodiments of the present application, step B2 obtains the interaction frequency between the first thread and the second thread according to the memory address range, including:

[0094] B21. Merge the first thread and the second thread into a thread affinity group according to the memory address range.

[0095] The first thread and the second thread access the same memory address range, and the server establishes a thread affinity group, and adds the first thread and the second thread that access the same memory address range to the thread affinity group. For example, the same memory address range can be the access address belonging to the same page in the memory. The thread affinity group can simplify the first thread and the second thread that access the same memory address range.

[0096] It can be understood that in the embodiment of the present application, if three or more threads access the same memory address range, the above multiple threads can be added to the thread affinity group.

[0097] B22. Obtain the interaction frequency between the first thread in the thread affinity group when it runs in the first running stage and the second thread when it runs in the second running stage, wherein the first running stage and the second running stage overlap in time.

[0098] The server may record the interaction frequency between threads in the same thread affinity group, and the server may record the interaction frequency between two threads in the same thread affinity group. For example, the thread affinity group includes a first thread and a second thread, the first thread runs in a first stage, and the second thread runs in a second stage, and the first running stage and the second running stage overlap in time, and the server records the interaction frequency between the first thread and the second thread in the same thread affinity group.

[0099] For an example, see Figure 4 , is a schematic diagram of the interaction frequency of communication between threads provided in an embodiment of the present application, the server runs thread 1 and thread 2, thread 1 includes 3 stages, namely task ready stage, task running stage, and task sleep stage. Thread 2 includes 2 stages, namely task running stage and task sleep stage.

[0100] In the context of thread switching, the server uses PMU sampling to identify the affinity and strength of threads. Specifically, the PMU sampling technology is used to accurately identify the memory access behavior of threads. When the CPU switches to a thread, the state value of the PMU register is read once. The PMU register contains the SPE register. When the thread ends and switches to the next thread, the state value of the PMU register is read again. The difference between the two read PMU register state values ​​is used to identify the memory access information of the thread during operation.

[0101] Taking the sampling when thread 2 is running as an example, PMU sampling is performed at the beginning and end of the task running of thread 2, and the PMU data obtained by sampling includes: access address and number of times, for example, when the access address is XXXXXX, the access number is 100 times, or when the access address is XXXXXX, the access number is 200 times. The page (Page) information accessed by thread 2 is searched through the access address, the thread ID (id) that recently accessed the same page is recorded, the interaction frequency between threads is updated, and the interaction frequency is normalized.

[0102] The server aggregates threads that access the same memory address range into the same group based on the address information and access frequency of the threads. For example, the same memory address range refers to the same page in the memory. The server sets an array in each group to record the interaction frequency when threads communicate with each other.

[0103] 202. Determine a first node according to the first memory access information, the second memory access information, and the kinship information.

[0104] After the server senses the affinity information between the first thread and the second thread, the server selects the same node for the first thread and the second thread from multiple memories of the server according to the affinity information and the first memory access information of the first thread and the second memory access information of the second thread, and the same node is defined as the first node. When the affinity between the first thread and the second thread is strong, both are assigned to the first node.

[0105] An example is given below. In the thread scheduling process, the server selects a NUMA node based on the memory access information and affinity of the two threads. The memory access information may include: thread access address information and memory access frequency. The server selects a NUMA node based on the memory access frequency in descending order. The NUMA node can be used to run the two threads.

[0106] In some embodiments of the present application, step 202 determines the first node according to the first memory access information, the second memory access information and the affinity information, including:

[0107] C1. Selecting a node with the most frequent memory access frequency from the task group as the first node according to the first memory access information, the second memory access information and the affinity information.

[0108] Among them, the server determines that there is a strong affinity between the first thread and the second thread based on the affinity information between the first thread and the second thread, the server determines to allocate the same node to the first thread and the second thread, and the server selects the node with the most frequent memory access frequency from the task group as the first node. When selecting the first node, the server still needs to execute subsequent step 203 to determine that the resource measurement value of the first node is less than the resource threshold. If the resource measurement value of the first node is greater than or equal to the resource threshold, the server re-executes step 202 to select the first node.

[0109] 203. Determine whether the resource metric value of the first node is less than a resource threshold.

[0110] After the server determines the first node, the server collects resource measurement information of the first node, and the resource measurement information may include measurement values ​​of one or more resource types, wherein the node has multiple resource types, for example, CPU resources, memory resources, IO resources, etc. According to the resource information of the first node, it is identified whether the resource measurement value of the first node is less than the resource threshold value, and when the resource measurement value of the first node is less than the resource threshold value, the subsequent step 203 is triggered to be executed.

[0111] It is understandable that in the embodiment of the present application, the server identifies whether the resource measurement value of the first node is less than the resource threshold, so that the server can determine whether the first node has a resource bottleneck. For example, if the resource measurement value of the first node is less than the resource threshold, the server determines that the first node has a resource bottleneck. If the resource measurement value of the first node is greater than or equal to the resource threshold, the server determines that the first node does not have a resource bottleneck. For another example, if the resource measurement value of the first node is less than or equal to the resource threshold, the server determines that the first node has a resource bottleneck. If the resource measurement value of the first node is greater than the resource threshold, the server determines that the first node does not have a resource bottleneck. The specific value-taking method of the above-mentioned resource threshold is not limited, and specifically depends on the resource type of the node and the thresholds corresponding to various types of resources in the actual application scenario. In the subsequent embodiments, the resource measurement value of the first node is less than the resource threshold to explain in detail the specific entity implementation method of the first node not having a resource bottleneck.

[0112] In some embodiments of the present application, Figure 5 As shown, in addition to executing the aforementioned steps 201 to 203, the method provided in the embodiment of the present application further includes:

[0113] D1. Obtain resource occupancy information of the first node in the first time unit;

[0114] D2. Determine a resource load metric of the first node according to the resource occupancy information.

[0115] The resource information collected by the server from the first node may specifically be the resource occupancy information of the first node in the first time unit, and the resource occupancy information may represent the resource occupancy time or the resource occupancy cycle. The resource load is measured by the resource occupancy information to determine the resource load measurement of the first node, and the resource busyness is measured by the resource load measurement. For example, the resource busyness refers to the degree to which the resource is utilized. For example, if there are tasks running on the CPU in 1 second, it means that the CPU utilization rate is 100%, and the CPU is very busy or the load is very high.

[0116] like Figure 5As shown, the resource occupancy cycle includes: cycle 1 and cycle 2, cycle 1 includes the time period from time (time) 1 to time 2, cycle 2 includes the time period from time 2 to time 3, the resource occupancy time of the first node is obtained for cycle 1 and cycle 2 respectively, the resource load measurement of the first node in cycle 1 is determined according to the resource occupancy time of cycle 1, and the resource load measurement of the first node in cycle 2 is determined according to the resource occupancy time of cycle 2.

[0117] In the implementation scenario where the server executes steps D1 to D2, step 203 determines that the resource metric value of the first node is less than the resource threshold, including:

[0118] E1. Determine, according to the resource load measurement of the first node, that the resource measurement value of the first node is less than a resource threshold.

[0119] The resource load metric is used to measure the resource load. The server can determine the resource load size of the first node based on the resource load metric. When the resource load metric is small, it is determined that the resource metric value of the first node is less than the resource threshold.

[0120] In some embodiments of the present application, in addition to executing the aforementioned steps 201 to 203, the method provided in the embodiment of the present application further includes:

[0121] F1. Obtain resource waiting information of the first node in the second time unit;

[0122] F2. Determine a resource interference metric of the first node according to the resource waiting information.

[0123] The resource information collected by the server from the first node may specifically be the resource waiting information of the first node in the second time unit, and the resource waiting information may represent the resource waiting time or the resource waiting cycle. The resource interference situation is measured by the resource waiting information, and the resource interference measurement of the first node is determined. The resource contention degree is measured by the resource interference measurement. The resource contention degree refers to the fact that multiple tasks of the same resource (such as CPU, memory, IO) use the resource at the same time. At this time, there is a process of competing for resources between the multiple tasks, and these multiple tasks compete or interfere with resources such as CPU, memory, IO, etc.

[0124] like Figure 6 As shown, cycle 1 includes the time period from time 1 to time 2. The waiting time of the resources of the first node in cycle 1 is calculated, and the resource interference measurement of the first node is determined based on the waiting time. A thread is started on each NUMA to periodically measure whether the resources of NUMA have reached a bottleneck. When the CPU, memory, IO utilization or interference reaches a threshold, it is determined that NUMA has reached a resource bottleneck. The threshold is set by the system default or input by the business program.

[0125] In the implementation scenario where the server executes steps F1 to F2, step 203 determines that the resource metric value of the first node is less than the resource threshold, including:

[0126] G1. Determine, according to the resource interference measurement of the first node, that a resource measurement value of the first node is less than a resource threshold.

[0127] The resource interference metric is used to measure the interference of resources. The server can determine the resource interference size of the first node according to the resource interference metric. When the resource interference metric is small, it is determined that the resource metric value of the first node is less than the resource threshold.

[0128] In some embodiments of the present application, in addition to executing the aforementioned steps 201 to 203, the method provided in the embodiment of the present application further includes:

[0129] H1. Obtain resource occupancy information of the first node in the first time unit, and determine the resource load measurement of the first node based on the resource occupancy information; and / or, H2. Obtain resource waiting information of the first node in the second time unit, and determine the resource interference measurement of the first node based on the resource waiting information.

[0130] The resource occupancy information and resource waiting information may be specifically as described above. Figure 5 and Figure 6 As shown, no detailed description is given here.

[0131] In the implementation scenario where the server executes step H1 and / or H2, step 203 determines that the resource metric value of the first node is less than the resource threshold, including:

[0132] I1. Determine, according to a resource load metric of the first node and / or a resource interference metric of the first node, that a resource metric value of the first node is less than a resource threshold.

[0133] Among them, the resource load measurement is used to measure the load situation of the resource, and the resource interference measurement is used to measure the interference situation of the resource. The server can determine the resource load size of the first node based on the resource load measurement. The server can determine the resource interference size of the first node based on the resource interference measurement. The server determines that the resource measurement value of the first node is less than the resource threshold based on at least one measurement value of the resource load measurement and the resource interference measurement. Through at least one measurement value of the above-mentioned resource load measurement and resource interference measurement, multiple methods of determining that the resource measurement value of the first node is less than the resource threshold are implemented. Specifically, the method of determining the resource bottleneck can be selected in combination with the application scenario.

[0134] In some embodiments of the present application, step 203 determines that the resource metric value of the first node is less than the resource threshold, including:

[0135] J1. Obtain a processor unit metric value, and / or a memory metric value, and / or an input / output metric value of the first node;

[0136] J2. Determine that the processor unit metric value of the first node is less than the computing power threshold, and / or determine that the memory metric value of the first node is less than the memory threshold, and / or determine that the output-input metric value of the first node is less than the input-output threshold.

[0137] The server may sense resource bottlenecks, for example, the resources of the first node may include at least one of the following: a processor unit metric value, a memory metric value, and an input / output metric value. The server may sense resource bottlenecks based on at least one of the above resources, and no matter which of the above resources has a bottleneck, the server may determine that the resource metric value of the first node is greater than or equal to a resource threshold.

[0138] For example, the processor unit metric value of the first node may include the operation information of the CPU, and it is determined that the processor unit metric value of the first node is less than the computing power threshold. For example, the processor unit metric value of the first node is less than the computing power threshold, and the server determines that the first node has a computing power bottleneck. The size of the computing power threshold can be flexibly selected according to the application scenario and is not limited here. When the first node has a computing power bottleneck, the server will not allocate the same processor resources to the first thread and the second thread to avoid reducing the execution efficiency of the threads.

[0139] The memory metric value of the first node may include memory operation information. It is determined that the memory metric value of the first node is less than the memory threshold. For example, if the memory metric value of the first node is less than the memory threshold, the server determines that the first node has a memory bottleneck. The size of the memory threshold can be flexibly selected according to the application scenario and is not limited here. When the first node has a memory bottleneck, the server will not allocate the same processor resources to the first thread and the second thread to avoid reducing the execution efficiency of the threads.

[0140] The input-output metric value of the first node may include IO information, and the input-output metric value of the first node is determined to be less than the input-output threshold value. For example, when the input-output metric value of the first node is less than the input-output threshold value, the server determines that the first node has an input-output bottleneck. The size of the input-output threshold value can be flexibly selected according to the application scenario and is not limited here. When the first node has an input-output bottleneck, the server will not allocate the same processor resources to the first thread and the second thread to avoid reducing the execution efficiency of the threads.

[0141] In some embodiments of the present application, step 203 determines that the resource metric value of the first node is less than the resource threshold, including:

[0142] L1. According to the resource information of the first node, periodically determine whether the resource metric value of the first node is less than the resource threshold; or,

[0143] L2. In response to an instruction of a scheduling processor unit or a load balancing instruction, determine that a resource metric value of the first node is less than a resource threshold.

[0144] Among them, the triggering execution of the server determining that the resource metric value of the first node is less than the resource threshold can be a periodic operation, and the server can determine that the resource metric value of the first node is less than the resource threshold by periodically detecting the resource information of the first node, so that the server can promptly determine that the resource metric value of the first node is less than the resource threshold. Alternatively, the triggering execution of the server determining that the resource metric value of the first node is less than the resource threshold can be receiving an instruction from a scheduling processor unit or a load balancing instruction, and the instruction of the scheduling processor unit can also be called a "core selection instruction". The server's operating system can generate an instruction from a scheduling processor unit or a load balancing instruction, and the server can detect the resource information of the first node under the triggering of the above instruction to determine that the resource metric value of the first node is less than the resource threshold, so that the server can determine that the resource metric value of the first node is less than the resource threshold according to the instruction of the operating system.

[0145] 204. Select a processor unit for running the first thread and the second thread according to the first node.

[0146] When the resource metric value of the first node is less than the resource threshold, the server may select a processor unit from the first node, and the processor unit may be used to run the first thread and the second thread simultaneously.

[0147] like Figure 7 As shown, taking a server adopting NUMA architecture as an example, the server includes: CPU1, CPU2, memory 1 and memory 2. Each memory and each CPU are connected together through a bus. Each CPU has a local memory with fast access speed. The CPU can also access the local memory of other CPUs, that is, the CPU accesses the remote memory, and the speed of accessing the remote memory is slightly slower than that of accessing the local memory.

[0148] In some embodiments of the present application, after step 204 selects a processor unit for running the first thread and the second thread according to the first node, the method provided by the embodiment of the present application further includes:

[0149] M1. Determine a thread with a lower memory access frequency from the first thread and the second thread according to the memory access frequency of the first thread and the memory access frequency of the second thread;

[0150] M2. In response to the resource metric value of the first node being less than the resource threshold, determine not to migrate the thread with a low memory access frequency.

[0151] The server can obtain the memory access frequency of the first thread in the first operation stage from the first memory access information of the first thread, obtain the memory access frequency of the second thread in the second operation stage from the second memory access information of the second thread, and determine the thread to be migrated from the memory access frequencies of the two threads, and the thread to be migrated is the thread with the lower memory access frequency of the first thread and the second thread. When implementing load balancing, the server can determine the thread with the lower memory access frequency of the first thread and the second thread, and then determine whether there is a resource bottleneck in the first node. When the resource measurement value of the first node is less than the resource threshold, the server does not allow the thread with the lower memory access frequency to migrate, so that the first thread and the second thread can be reported to be allocated to the same processor unit, thereby avoiding remote access across nodes of multiple threads and reducing the overhead of running the first thread and the second thread.

[0152] In some embodiments of the present application, in addition to performing the aforementioned steps M1 to M2, the method provided in the embodiment of the present application further includes:

[0153] N1. In response to a resource metric value of the first node being greater than or equal to a resource threshold, a thread with a low memory access frequency is migrated from the first node to a second node, where the second node is a remote node of the first node.

[0154] The server can obtain the memory access frequency of the first thread in the first operation stage from the first memory access information of the first thread, obtain the memory access frequency of the second thread in the second operation stage from the second memory access information of the second thread, and determine the thread to be migrated from the memory access frequencies of the two threads, and the thread to be migrated is the thread with the low memory access frequency of the first thread and the second thread. When implementing load balancing, the server can determine the thread with the low memory access frequency in the first thread and the second thread, and then determine whether there is a resource bottleneck in the first node. When the resource measurement value of the first node is greater than or equal to the resource threshold, it is necessary to migrate the thread with the low memory access frequency, and migrate the thread with the low memory access frequency from the first node to the second node, which is a remote node of the first node. The thread with the low memory access frequency is executed through the second node to ensure the execution efficiency of the thread currently retained on the first node, so as to achieve a balance between scheduling resources and performance.

[0155] The following example illustrates that the server modifies the current core selection and load balancing mechanism based on affinity and resource bottlenecks, such as Figure 8As shown, a schematic diagram of dynamically determining scheduling within NUMA or scheduling between NUMAs provided by an embodiment of the present application, taking the server adopting NUMA architecture as an example, the server can dynamically decide whether to schedule within a NUMA or between NUMAs. The server creates a process, for example, by creating a process through a fork function, and selects a NUMA node for each process according to the interleave strategy. When the thread wakes up, an optimal node is selected according to the memory access information of the task group, and it is determined whether this node has a resource bottleneck. If there is a resource bottleneck, the other optimal nodes of the task group are selected, wherein the optimal node selection strategy is "this node is the node with the most frequent memory access of the task group". During load balancing, multiple threads are sorted according to the strength of the NUMA memory access frequency, and the thread with the weaker memory access frequency migrates first. When the thread migrates, if this NUMA is the optimal node for the task, it is determined whether the NUMA node has reached the resource bottleneck. If the resource bottleneck has not been reached, the thread with the weak memory access frequency is not allowed to migrate.

[0156] In the embodiment of the present application, the server guides thread scheduling within and between NUMAs based on affinity and whether there are bottlenecks in resources, so as to achieve a balance between scheduling resources and performance in a multi-NUMA environment.

[0157] Through the examples of the above-mentioned embodiments, it can be seen that the affinity information between the first thread and the second thread is first determined according to the first memory access information of the first thread in the first running stage and the second memory access information of the second thread in the second running stage, and the affinity information indicates that there is an affinity between the first thread and the second thread. Then, the first node is determined according to the first memory access information, the second memory access information and the affinity information. For example, the first node can be a node in the NUMA architecture. Next, it is determined that the resource measurement value of the first node is less than the resource threshold. The absence of a resource bottleneck can indicate that the resources on the first node can be used by multiple threads. Finally, a processor unit for running the first thread and the second thread is selected from the first node. Since the first node is selected according to the affinity information in the embodiment of the present application, and the processor unit is allocated to the first thread and the second thread on the first node when the resource measurement value of the first node is less than the resource threshold, remote access across nodes of multiple threads is avoided, and the overhead of running the first thread and the second thread is reduced.

[0158] In order to better understand and implement the above-mentioned solutions in the embodiments of the present application, the following examples are given for specific explanation by using corresponding application scenarios.

[0159] Please refer to Fig. 9As shown, it is a schematic diagram of an application scenario of a server provided in an embodiment of the present application applied to a NMUA architecture. The system architecture applied in the embodiment of the present application can be a server scenario based on a NUMA architecture, the server can be a server of various types, and the user layer application software includes distributed storage (ceph), in-memory database (redis), relational database (such as HBASE, mysql), etc.

[0160] The server's real-time operating system (Kernel) includes software modules: an adaptive perception module and a scheduling module. The following describes the adaptive perception module and the scheduling module respectively:

[0161] The adaptive perception module includes a kinship perception module and a resource bottleneck perception module.

[0162] Among them, the affinity perception module is used to perceive the affinity between threads, identify multiple threads accessing the same memory block through the memory access behavior of the threads, and determine the affinity threads; threads with the same affinity are assigned to the same thread affinity group, and the memory access information of the threads and groups is recorded.

[0163] The resource bottleneck perception module is used to perceive the resource bottleneck of the NUMA node (Node) by identifying the computing power bottleneck, memory bottleneck, and input output (IO) bottleneck. For example, if the resource measurement value of the NUMA node is less than the resource threshold, the server determines that the NUMA node has a resource bottleneck. If the resource measurement value of the NUMA node is greater than or equal to the resource threshold, the server determines that the NUMA node does not have a resource bottleneck. For another example, if the resource measurement value of the NUMA node is less than or equal to the resource threshold, the server determines that the NUMA node has a resource bottleneck. If the resource measurement value of the NUMA node is greater than the resource threshold, the server determines that the NUMA node does not have a resource bottleneck.

[0164] The scheduling module is used to optimize the current core selection and load balancing logic, breaking the original load balancing model. In the thread scheduling process, a NUMA node is selected based on the memory access information of the thread group, and the NUMA node is selected in descending order of memory access frequency. When a NUMA node is selected, it is determined whether there is a bottleneck in the resources of this NUMA node.

[0165] If the NUMA node has no bottleneck, the NUMA node is selected, and an optimal CPU is selected in the NUMA node according to the system's native core selection process. For example, the system's native core selection process includes that when there is no resource bottleneck of the NUMA node, the optimal CPU is inside the NUMA node.

[0166] If there is a resource bottleneck on this NUMA node, the next NUMA node is selected. If there is no suitable NUMA node, the core is selected according to the system's native logic. For example, one system's native logic may be the fork core selection logic, which performs core selection when a thread is just generated. This core selection logic traverses the system's CPUs and selects an idle CPU. Another system's native logic is the wake-up core selection logic, which determines the CPU with the lightest load based on the CPU where the thread was previously running and the CPU where the current wake-up thread is located when the thread is awakened. The CPU with the lightest load is selected as the center and an idle CPU is selected.

[0167] Specifically, the scheduling module may include four sub-modules, which respectively implement a fork balance strategy, a wakeup balance strategy, a load balance strategy, and a NUMA balance strategy.

[0168] Among them, four sub-modules are used to implement the core selection process of the scheduling module, specifically:

[0169] Fork balance refers to the implementation of core selection when a task is created. At this time, the CPUs of the entire system will be traversed, and a CPU with the lightest load will be selected based on load information.

[0170] Wakeup balance refers to the selection of cores when a task is newly awakened. Based on the CPU where the thread previously ran and the CPU where the current awakened thread is located, the CPU with the lightest load is determined, and then an idle CPU is selected with this CPU with the lightest load as the center.

[0171] Load balance means that the system periodically determines whether there is a load imbalance in the system. If there is a load imbalance, the tasks on the heavily loaded CPU are migrated to the lightly loaded CPU.

[0172] NUMA balance means that the system periodically determines whether there is an imbalance between NUMAs in the system. If there is an imbalance between NUMAs, memory migration or task migration is performed.

[0173] Fig.10 The following is a schematic diagram of the software and hardware structure of the server provided in the embodiment of the present application. Next, the implementation form of the embodiment of the present application in the platform software and server hardware is described. The product implementation form of the embodiment of the present application is the program code contained in the operating system kernel and deployed on the server hardware. Fig.10Taking the application scenario shown as an example, the program code of the embodiment of the present application exists in the scheduling system of the kernel module, wherein the hardware structure of the server includes a scheduler, an affinity perception module and a resource bottleneck perception module.

[0174] The method implemented in the embodiment of the present application includes the following steps:

[0175] S01. In the program running context, the memory access of the thread is tracked by sampling the performance management unit (power management unit, PMU) data.

[0176] This step is executed in the thread running context. When the CPU switches to this thread and starts running, the PMU data is read once. When this thread runs to the end, the PMU data is read again. The difference between the two PMU data is used to obtain the memory access information in this thread running stage.

[0177] S02. Merge threads accessing the same memory address into a thread affinity group.

[0178] This step is triggered periodically or immediately after S01 is executed. According to the memory access information of the thread running phase obtained in S01, multiple threads accessing the same block address are merged into the same group.

[0179] S03. Record the interaction frequency between the same group of threads to determine affinity.

[0180] For example, kinship includes: strong or weak kinship.

[0181] S03 may be triggered periodically or immediately after S02 is executed, and is executed after S02 is completed. Based on the information of S01 and S02, the interaction frequency between multiple threads in the same group is recorded to determine the strength of affinity.

[0182] S04. Determine whether there is a resource bottleneck on the NUMA node.

[0183] S04 can be executed periodically or in a scheduling core selection or load balancing path, and determines whether a NUMA node has a resource bottleneck by obtaining load information of a NUMA node or interference information between tasks on a NUMA node. The interference strength of two threads is determined by measuring the waiting time caused by two threads running on the same CPU.

[0184] S05. Optimize the core selection and load balancing process to aggregate threads with affinity to one NUMA node.

[0185] This step is on the critical path of task core selection and load balancing. When selecting a core, a node is selected first based on the memory access information of the task group to determine whether this node has a resource bottleneck. If there is no resource bottleneck, this node is selected. If there is a resource bottleneck, the next node with the most frequent memory access is selected. When the system load is balanced, when it is necessary to migrate tasks across NUMA, if the current node is the node with the most memory access, it is determined whether this node has a resource bottleneck. If there is no resource bottleneck, the thread does not need to be migrated; only when this node has a resource bottleneck, threads with low memory access frequency need to be migrated.

[0186] It can be seen from the above examples that in the embodiment of the present application, lightweight PMU sampling is used during thread switching context to accurately obtain memory access information, identify the interaction frequency between threads, and thereby identify the affinity between multiple threads, which has the advantages of high recognition accuracy and low overhead.

[0187] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0188] In order to better implement the above-mentioned solution of the embodiment of the present application, relevant devices for implementing the above-mentioned solution are also provided below.

[0189] See also Fig.11 As shown, a server 1100 provided in an embodiment of the present application may include: a relationship determination module 1101, a node determination module 1102, a resource measurement module 1103, and a selection module 1104, wherein:

[0190] An affinity determination module, configured to determine affinity information between the first thread and the second thread according to first memory access information of the first thread in the first running stage and second memory access information of the second thread in the second running stage;

[0191] a node determination module, configured to determine a first node according to the first memory access information, the second memory access information and the affinity information;

[0192] A resource measurement module, configured to determine that a resource measurement value of the first node is less than a resource threshold;

[0193] A selection module is used to select a processor unit for running the first thread and the second thread according to the first node.

[0194] It should be noted that the information interaction, execution process, etc. between the modules / units of the above-mentioned device are based on the same concept as the method embodiment of the present application, and the technical effects they bring are the same as those of the method embodiment of the present application. For specific contents, please refer to the description in the method embodiment shown above in the present application, and will not be repeated here.

[0195] An embodiment of the present application also provides a computer storage medium, wherein the computer storage medium stores a program, and the program executes some or all of the steps recorded in the above method embodiment.

[0196] Next, another computer system provided by the embodiment of the present application is introduced. Fig.12 As shown, the computer system 1200 includes:

[0197] Receiver 1201, transmitter 1202, processor 1203 and memory 1204 (the number of processors 1203 in computer system 1200 can be one or more, Fig.12 In some embodiments of the present application, the receiver 1201, the transmitter 1202, the processor 1203 and the memory 1204 may be connected via a bus or other means, wherein: Fig.12 The example of connecting through bus is taken in the following.

[0198] The memory 1204 may include a read-only memory and a random access memory, and provides instructions and data to the processor 1203. A portion of the memory 1204 may also include a non-volatile random access memory (NVRAM). The memory 1204 stores an operating system and operating instructions, executable modules or data structures, or a subset thereof, or an extended set thereof, wherein the operating instructions may include various operating instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and processing hardware-based tasks.

[0199] The processor 1203 controls the operation of the computer system, and the processor 1203 may also be referred to as a central processing unit (CPU). In a specific application, the various components of the computer system are coupled together through a bus system, wherein the bus system may include a power bus, a control bus, and a status signal bus in addition to a data bus. However, for the sake of clarity, various buses are referred to as bus systems in the figure.

[0200] The method disclosed in the above embodiment of the present application can be applied to the processor 1203, or implemented by the processor 1203. The processor 1203 can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 1203. The above processor 1203 can be a general processor, a digital signal processor (digital signal processing, DSP), an application specific integrated circuit (application specific integrated circuit, ASIC), a field programmable gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to execute, or the hardware and software modules in the decoding processor can be executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 1204, and the processor 1203 reads the information in the memory 1204 and completes the steps of the above method in combination with its hardware.

[0201] The receiver 1201 may be used to receive input digital or character information, and to generate signal input related to the relevant settings and function control of the computer system. The transmitter 1202 may include a display device such as a display screen, and the transmitter 1202 may be used to output digital or character information through an external interface.

[0202] In the embodiment of the present application, the processor 1203 is used to execute the above Figure 2 The multi-threaded scheduling method shown.

[0203] In another possible design, when the computer system is a chip, the chip includes: a processing unit and a communication unit, the processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, a pin or a circuit, etc. The processing unit may execute the computer execution instructions stored in the storage unit so that the chip executes any one of the methods of the first aspect above. Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, etc., and the storage unit may also be a storage unit located outside the chip, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc.

[0204] The processor mentioned in any of the above places may be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the program of the above-mentioned first aspect method.

[0205] It should also be noted that the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the drawings of the device embodiments provided by the present application, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines.

[0206] Through the description of the above implementation mode, the technicians in the field can clearly understand that the present application can be implemented by means of software plus necessary general hardware, and of course, it can also be implemented by special hardware including application-specific integrated circuits, special CPUs, special memories, special components, etc. In general, all functions completed by computer programs can be easily implemented with corresponding hardware, and the specific hardware structure used to implement the same function can also be various, such as analog circuits, digital circuits or special circuits. However, for the present application, software program implementation is a better implementation mode in more cases. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer floppy disk, a U disk, a mobile hard disk, a ROM, a RAM, a magnetic disk or an optical disk, etc., including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0207] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0208] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, a computer, a server, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

Claims

1. A multi-threaded scheduling method, characterized in that: include: Determine affinity information between the first thread and the second thread according to first memory access information of the first thread in the first running stage and second memory access information of the second thread in the second running stage; Determine a first node according to the first memory access information, the second memory access information and the affinity information; Determining that the resource metric value of the first node is less than a resource threshold; A processor element for executing the first thread and the second thread is selected according to the first node.

2. The method according to claim 1, characterized in that: The method further comprises: In the first running phase in the thread switching context, state information of a performance management unit is collected, and the first memory access information is determined according to the state information of the performance management unit.

3. The method according to claim 2, characterized in that The collecting the status information of the performance management unit in the first operation phase, and determining the first memory access information according to the status information of the performance management unit, includes: Reading first status information from a register of the performance management unit at the start of the first operation phase; Reading second status information from the register at the end of the first operation phase; The first memory access information is determined according to the first state information and the second state information.

4. The method according to claim 1, characterized in that The first memory access information includes: address information accessed by the first thread; the second memory access information includes: address information accessed by the second thread; The determining of affinity information between the first thread and the second thread according to first memory access information of the first thread in the first running stage and second memory access information of the second thread in the second running stage comprises: Determine, according to the address information accessed by the first thread and the address information accessed by the second thread, a memory address range in which the first thread and the second thread access the same memory; Acquire the interaction frequency between the first thread and the second thread according to the memory address range; Affinity information between the first thread and the second thread is determined according to the interaction frequency.

5. The method according to claim 4, characterized in that The acquiring the interaction frequency between the first thread and the second thread according to the memory address range includes: merging the first thread and the second thread into a thread affinity group according to the memory address range; Obtain an interaction frequency between the first thread in the thread affinity group when it is running in the first running stage and the second thread in the second running stage, wherein the first running stage and the second running stage overlap in time.

6. The method according to any one of claims 1 to 5, characterized in that The method further includes: acquiring resource occupancy information of the first node in a first time unit, and determining a resource load metric of the first node according to the resource occupancy information; and / or acquiring resource waiting information of the first node in a second time unit, and determining a resource interference metric of the first node according to the resource waiting information; The determining that the resource metric value of the first node is less than a resource threshold includes: It is determined that the resource metric value of the first node is less than a resource threshold value according to the resource load metric of the first node and / or the resource interference metric of the first node.

7. The method according to any one of claims 1 to 5, characterized in that The determining that the resource metric value of the first node is less than a resource threshold includes: Obtaining a processor unit metric value, and / or a memory metric value, and / or an input / output metric value of the first node; Determine that the processor unit metric value of the first node is less than a computing power threshold, and / or determine that the memory metric value of the first node is less than a memory threshold, and / or determine that the output-input metric value of the first node is less than an input-output threshold.

8. The method according to any one of claims 1 to 7, characterized in that The determining the first node according to the first memory access information, the second memory access information and the affinity information includes: A node with the most frequent memory access frequency is selected from a task group as the first node according to the first memory access information, the second memory access information and the affinity information.

9. The method according to any one of claims 1 to 8, characterized in that After selecting a processor unit for running the first thread and the second thread from the first node, the method further includes: Determining a thread with a lower memory access frequency from the first thread and the second thread according to the memory access frequency of the first thread and the memory access frequency of the second thread; In response to the resource metric value of the first node being less than a resource threshold, it is determined not to migrate the thread with a low memory access frequency.

10. The method according to claim 9, characterized in that The method further comprises: In response to the resource metric value of the first node being greater than or equal to a resource threshold, the thread with low memory access frequency is migrated from the first node to a second node, where the second node is a remote node of the first node.

11. The method according to any one of claims 1 to 10, characterized in that The determining that the resource metric value of the first node is less than a resource threshold includes: According to the resource information of the first node, periodically determine whether the resource metric value of the first node is less than a resource threshold; or, In response to an instruction of a scheduling processor unit or a load balancing instruction, it is determined that the resource metric value of the first node is less than a resource threshold.

12. A server, characterized in that: include: An affinity determination module, configured to determine affinity information between the first thread and the second thread according to first memory access information of the first thread in the first running stage and second memory access information of the second thread in the second running stage; a node determination module, configured to determine a first node according to the first memory access information, the second memory access information and the affinity information; A resource measurement module, configured to determine that a resource measurement value of the first node is less than a resource threshold; A selection module is used to select a processor unit for running the first thread and the second thread according to the first node.

13. A computer system, characterized in that: The computer system comprises: a processor and a memory; the processor and the memory communicate with each other; The memory is used to store instructions; The processor is configured to execute the instructions in the memory to perform the method according to any one of claims 1 to 11.

14. A computer-readable storage medium comprising instructions, which, when executed on a computer, causes the computer to execute the method according to any one of claims 1 to 11.

15. A computer program product comprising instructions, which, when executed on a computer, causes the computer to perform the method according to any one of claims 1 to 11.

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