Universal input / output pin verification method, system, device, equipment and medium
By building parameter configuration documents and code template engine documents, verification components and testing programs are automatically generated, and the integrated chip GPIO verification is automated, solving the problems of low verification efficiency, high cost and poor accuracy in the existing technology, and improving the efficiency and accuracy of verification.
Patent Information
- Application Number
- CN202411662891.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-04-25
AI Technical Summary
In the prior art, GPIO verification of integrated chips mainly relies on manual methods, which leads to inefficient verification, high cost, accuracy and reliability that are difficult to guarantee. Especially when the number of GPIO pins increases, it is difficult to cope with large-scale and high-precision testing needs.
By building parameter configuration documents and code template engine documents, extracting configuration parameters and rendering and filling generation driver components, monitor components, scoreboard components and target test programs, automatically generate components and test programs required for verification, and combine these components to automatically verify the GPIO pins.
It improves the efficiency of GPIO verification, reduces labor and time costs, enhances the accuracy and reliability of tests, avoids errors introduced by human factors, and can cope with large-scale and high-precision testing needs.
Smart Images
Figure CN119883779A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of chip function verification, and in particular to a method, system, device, equipment and medium for verifying general input and output pins. Background Art
[0002] With the rapid development of microelectronics technology, the application fields of integrated chips are constantly expanding. In the research and development process of integrated chips, after the integrated chip is designed, the general purpose input / output (GPIO) functions of the integrated chip need to be verified to ensure the correctness of the final produced chip.
[0003] Currently, GPIO verification of integrated chips is mostly done manually, by configuring GPIO parameters one by one and applying high-level or low-level signals, and then reading the response of the integrated chip to the external level to verify its input function.
[0004] Although this method is feasible and intuitive to a certain extent, with the advancement of technology and the increase in the number of GPIO pins on integrated chips, manually verifying each pin has become extremely time-consuming and laborious, significantly increasing the manpower and time costs of testing. In addition, repetitive labor is not only inefficient, but also prone to errors due to human factors, reducing the accuracy and reliability of the test. In addition, the entire verification process is cumbersome and complicated, making it difficult to meet large-scale and high-precision testing requirements. Summary of the invention
[0005] In order to solve the above technical problems, the present disclosure provides a general input and output pin verification method, system, device, equipment and medium to improve verification efficiency, reduce labor costs and time costs, and improve test accuracy and reliability.
[0006] In a first aspect, an embodiment of the present disclosure provides a general input / output pin verification method, the method comprising:
[0007] Build parameter configuration documents and code template engine documents;
[0008] Extracting configuration parameters from the parameter configuration document, rendering and filling the code template engine document based on the configuration parameters, and generating a driver component, a monitor component, a scoreboard component, and a target test program;
[0009] Burning the target test program onto a target chip to be tested, and executing the target test program through the target chip to be tested;
[0010] Based on the target test program combined with the driver component, the monitor component and the scoreboard component, the general input and output pins are verified to obtain a verification result.
[0011] In some embodiments, the parameter configuration document has a plurality of column variables, the plurality of column variables including a source end path, a destination end path, a register address, a register data, a reference clock, and a clock cycle;
[0012] The code format templates of various components are defined in the code template engine document.
[0013] In some embodiments, extracting the configuration parameters in the parameter configuration document, rendering and filling the code template engine document based on the configuration parameters, and generating a driver component, a monitor component, a scoreboard component, and a target test program include:
[0014] Get pre-written automation scripts;
[0015] The configuration parameters in the parameter configuration document are extracted by the automation script, and the code template engine document is rendered and filled based on the configuration parameters to generate a driver component, a monitor component, a scoreboard component and a target test program.
[0016] In some embodiments, burning the target test program onto a target chip to be tested, and executing the target test program through the target chip to be tested, includes:
[0017] Compiling the target test program to generate a binary machine file;
[0018] Burning the binary machine file into the program storage unit of the target chip to be tested;
[0019] The binary machine file is read and executed by the central processing unit of the target chip to be tested.
[0020] In some embodiments, after generating the driver component, the monitor component, the scoreboard component, and the target test program, the method further includes:
[0021] Integrate the driver component, the monitor component, the scoreboard component and the target test program to obtain a verification environment;
[0022] Correspondingly, burning the target test program onto the target chip to be tested and executing the target test program through the target chip to be tested includes:
[0023] Burning the target test program onto the target chip to be tested;
[0024] Start the verification environment and begin compiling and simulating;
[0025] The target test program is executed through the target chip to be tested.
[0026] In some embodiments, the verification of the general input and output pins based on the target test program in combination with the driver component, the monitor component and the scoreboard component to obtain the verification result includes:
[0027] The driver component monitors the first flag signal, applies a level driving value to the source end of the general input / output pin, and sends the level driving value to the scoreboard component, wherein the level driving value includes a high level signal or a low level signal;
[0028] The second flag signal is monitored by the monitor component, an actual level value of the destination end of the general input / output pin is collected, and the actual level value is sent to the scoreboard component;
[0029] The level driving value and the level actual value are compared by the scoreboard component to obtain the verification result of the general input and output pin.
[0030] In a second aspect, an embodiment of the present disclosure provides a general input / output pin verification system, wherein the general input / output pin verification system is applied to a verification platform, wherein the verification platform includes a parameter configuration document, a code template engine document, a driver component, a monitor component, a scoreboard component, and a target test program;
[0031] The parameter configuration document is used to store the source end path, the destination end path, the register address, the register data, the reference clock and the clock cycle;
[0032] The code template engine document is used to define the code format templates of each component;
[0033] The target test program is used to combine the driver component, the monitor component and the scoreboard component to verify the general input and output pins;
[0034] The driver component is used to apply a level driving value to the source end of the general input and output pin;
[0035] The monitor component is used to collect the actual value of the level of the destination end of the general input and output pin;
[0036] The scoreboard component is used to compare the level drive value with the level actual value to obtain the verification result of the general input and output pin.
[0037] In a third aspect, an embodiment of the present disclosure provides a general input / output pin verification device, the device comprising:
[0038] Construction module, used to build parameter configuration documents and code template engine documents;
[0039] A rendering module, used to extract the configuration parameters in the parameter configuration document, render and fill the code template engine document based on the configuration parameters, and generate a driver component, a monitor component, a scoreboard component and a target test program;
[0040] An execution module, used for burning the target test program into a target chip to be tested, and executing the target test program through the target chip to be tested;
[0041] The verification module is used to verify the general input and output pins based on the target test program in combination with the driver component, the monitor component and the scoreboard component to obtain a verification result.
[0042] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including:
[0043] Memory;
[0044] Processor; and
[0045] Computer programs;
[0046] The computer program is stored in the memory and is configured to be executed by the processor to implement the method as described in the first aspect.
[0047] In a fifth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the method as described in the first aspect.
[0048] In a sixth aspect, an embodiment of the present disclosure further provides a computer program product, which includes a computer program or instructions, and when the computer program or instructions are executed by a processor, the method described in the first aspect is implemented.
[0049] The general input and output pin verification method, system, device, equipment and medium provided by the embodiment of the present disclosure, by constructing a parameter configuration document and a code template engine document, extracting the configuration parameters in the parameter configuration document, rendering and filling the code template engine document based on the configuration parameters, generating a driver component, a monitor component, a scoreboard component and a target test program, burning the target test program to the target chip to be tested, executing the target test program through the target chip to be tested, and verifying the general input and output pins based on the target test program in combination with the driver component, the monitor component and the scoreboard component to obtain a verification result. Compared with the prior art, the present disclosure, by constructing a parameter configuration document and a code template engine document, extracting the configuration parameters in the parameter configuration document, rendering and filling the code template engine document based on the configuration parameters, generating a driver component, a monitor component, a scoreboard component and a target test program, can automatically generate the components and test programs required for verification, and verifying the general input and output pins based on the target test program in combination with the driver component, the monitor component and the scoreboard component, can improve the verification efficiency, reduce the labor cost and time cost, and avoid the errors introduced by human factors, and improve the accuracy and reliability of the test. BRIEF DESCRIPTION OF THE DRAWINGS
[0050] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0051] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0052] Figure 1 A flow chart of a general input / output pin verification method provided in an embodiment of the present disclosure;
[0053] Figure 2 A schematic diagram of a parameter configuration document provided in an embodiment of the present disclosure;
[0054] Figure 3 A flow chart of a general input / output pin verification method provided by another embodiment of the present disclosure;
[0055] Figure 4 A flow chart of a general input / output pin verification method provided by another embodiment of the present disclosure;
[0056] Figure 5 A schematic diagram of the architecture of a universal input / output pin verification system and verification platform provided in an embodiment of the present disclosure;
[0057] Figure 6 A schematic diagram of the structure of a general input / output pin verification device provided by an embodiment of the present disclosure;
[0058] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0059] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.
[0060] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.
[0061] With the rapid development of microelectronics technology, the application fields of integrated chips are constantly expanding. In the research and development process of integrated chips, after the integrated chip is designed, the general purpose input / output (GPIO) functions of the integrated chip need to be verified to ensure the correctness of the final produced chip.
[0062] Currently, GPIO verification of integrated chips is mostly done manually, by configuring GPIO parameters one by one and applying high or low level signals, and then reading the response of the integrated chip to the external level to verify its input function.
[0063] Although this method is feasible and intuitive to a certain extent, with the advancement of technology and the increase in the number of GPIO pins on integrated chips, manually verifying each pin has become extremely time-consuming and laborious, significantly increasing the manpower and time costs of testing. In addition, repetitive labor is not only inefficient, but also prone to errors due to human factors, reducing the accuracy and reliability of the test. In addition, the entire verification process is cumbersome and complicated, making it difficult to meet large-scale and high-precision testing requirements.
[0064] To address this problem, an embodiment of the present disclosure provides a general input / output pin verification method, which is described below in conjunction with a specific embodiment.
[0065] Figure 1The flowchart of the universal input-output pin verification method provided in the embodiment of the present disclosure is an electronic device. The electronic device can be a portable mobile device such as a smart phone, a tablet computer, a laptop computer, a car navigation device, and a smart sports equipment; it can also be a fixed device such as a personal computer and a smart home appliance. The method can be applied to the scenario of verifying the universal input-output pins, which can improve the verification efficiency, reduce the manpower cost and time cost, and improve the accuracy and reliability of the test. It can be understood that the universal input-output pin verification method provided in the embodiment of the present disclosure can also be applied in other scenarios.
[0066] Below Figure 1 The general input and output pin verification method shown in the figure is introduced, which includes the following steps:
[0067] S101. Build parameter configuration documents and code template engine documents.
[0068] In this step, the user will write the parameter configuration document and the code template engine document, and the electronic device will generate the parameter configuration document and the code template engine document in response to the operation written by the user.
[0069] In some embodiments, the parameter configuration document contains multiple column variables, including source path, destination path, register address, register data, reference clock and clock cycle; the code format template of each component is defined in the code template engine document.
[0070] Specifically, the parameter configuration document is responsible for storing key parameters such as the path information of the general purpose input and output (GPIO) source, the path information of the destination, the register address, and the register data; Figure 2 As shown, there are multiple column variables in the parameter configuration document, each column variable corresponds to a configuration parameter, and the multiple column variables include a source path (source), a destination path (destination), a register address (reg_addr), a register data (reg_data), a reference clock (reference_Clock) and a clock cycle (clock_time).
[0071] like Figure 5 As shown, the code template engine document defines the fixed format of each component code, including the fixed format of the driver component code (driver.mako), the fixed format of the monitor component code (monitor.mako), the fixed format of the scoreboard component code (scoreboard.mako), and the fixed format of the target test program code (mainc.mako).
[0072] Mako is a Python template engine that allows dynamic content to be embedded in Python code. The Mako format template class is used in the code template engine document to render the template, convert the extracted configuration parameters into json data, and further render the json data into the mako template in the code template engine document to generate the corresponding components. Among them, json (JavaScript Object Notation) is a lightweight data exchange format.
[0073] Description of Mako format template: In the generation of UVM components, the variable parts such as component name, interface, transaction, etc. can be extracted and represented by Mako placeholder ${name}. Then, when the template is rendered, the actual configuration parameters are passed in through the Python script to replace ${name}. These actual configuration parameters are stored in the json data file.
[0074] S102: extract configuration parameters from the parameter configuration document, render and fill the code template engine document based on the configuration parameters, and generate a driver component, a monitor component, a scoreboard component, and a target test program.
[0075] In this step, after constructing the parameter configuration document and the code template engine document, the electronic device extracts the configuration parameters in the parameter configuration document, renders and fills the code template engine document based on the configuration parameters, and generates a driver component, a monitor component, a scoreboard component, and a target test program. In some embodiments, the electronic device extracts the configuration parameters in the parameter configuration document through a Python script, and fills the configuration parameters into the code template engine document to generate a driver component, a monitor component, a scoreboard component, and a target test program.
[0076] S103 , burning the target test program into a target chip to be tested, and executing the target test program through the target chip to be tested.
[0077] In this step, the electronic device burns the target test program onto the target chip to be tested, and executes the target test program through the target chip to be tested.
[0078] S104: Based on the target test program, in combination with the driver component, the monitor component and the scoreboard component, verify the general input and output pins to obtain a verification result.
[0079] In this step, the electronic device will verify the general input and output pins based on the target test program in combination with the driver component, the monitor component and the scoreboard component to obtain the verification results, which can improve the verification efficiency and reduce the labor cost and time cost.
[0080] The embodiment of the present disclosure constructs a parameter configuration document and a code template engine document, extracts the configuration parameters in the parameter configuration document, renders and fills the code template engine document based on the configuration parameters, generates a driver component, a monitor component, a scoreboard component and a target test program, burns the target test program to the target chip to be tested, executes the target test program through the target chip to be tested, verifies the general input and output pins based on the target test program in combination with the driver component, the monitor component and the scoreboard component, and obtains the verification result. Compared with the prior art, the present disclosure constructs a parameter configuration document and a code template engine document, extracts the configuration parameters in the parameter configuration document, renders and fills the code template engine document based on the configuration parameters, generates the driver component, the monitor component, the scoreboard component and the target test program, can automatically generate the components and test programs required for verification, verifies the general input and output pins based on the target test program in combination with the driver component, the monitor component and the scoreboard component, can improve the verification efficiency, reduce the labor cost and time cost, and avoid the errors introduced by human factors, and improve the accuracy and reliability of the test.
[0081] Figure 3 A flowchart of a general input / output pin verification method provided by another embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the method includes the following steps:
[0082] S301, build parameter configuration documents and code template engine documents.
[0083] Specifically, the implementation principle and process of S301 and S101 are the same, and will not be repeated here.
[0084] S302: Obtain a pre-written automation script.
[0085] In this step, the user will pre-write the automation script, import it into the electronic device for storage, and the electronic device will obtain the pre-written automation script. Optionally, the automation script is a Python automation script, which is not limited.
[0086] S303: extract the configuration parameters in the parameter configuration document through the automation script, render and fill the code template engine document based on the configuration parameters, and generate a driver component, a monitor component, a scoreboard component and a target test program.
[0087] In this step, the electronic device can extract the configuration parameters in the parameter configuration document through the automation script, and fill the configuration parameters into the code template engine document to generate the driver component, the monitor component, the scoreboard component and the target test program. Through the synergy of the automation script and the code template engine document, the driver component, the monitor component, the scoreboard component and the target test program can be automatically generated.
[0088] S304: Compile the target test program to generate a binary machine file.
[0089] The electronic device can compile the target test program, such as a C program, to generate a binary executable file, that is, a binary machine file. In some embodiments, the binary machine file can be compiled through a professional tool chain.
[0090] S305: Burn the binary machine file into the program storage unit of the target chip to be tested.
[0091] After the binary machine file is generated, the binary machine file is further burned into the program storage unit of the target chip to be tested. Optionally, the binary machine file can be burned into the program storage unit of the target chip to be tested by backdoor burning.
[0092] S306: Read and execute the binary machine file through the central processing unit of the target chip to be tested.
[0093] S307 , based on the target test program in combination with the driver component, the monitor component and the scoreboard component, verify the general input and output pins to obtain a verification result.
[0094] Specifically, the implementation principle and process of S307 and S104 are the same, and will not be repeated here.
[0095] The disclosed embodiment constructs a parameter configuration document and a code template engine document, obtains a pre-written automation script, extracts the configuration parameters in the parameter configuration document through the automation script, renders and fills the code template engine document based on the configuration parameters, and generates a driver component, a monitor component, a scoreboard component and a target test program. Further, the target test program is compiled to generate a binary machine file, the binary machine file is burned into the program storage unit of the target chip to be tested, and the binary machine file is read and executed by the central processing unit of the target chip to be tested. Then, based on the target test program combined with the driver component, the monitor component and the scoreboard component, the general input and output pins are verified to obtain the verification results. Through this method, the verification efficiency can be improved, the labor cost and time cost can be reduced, while avoiding errors introduced by human factors and improving the accuracy and reliability of the test.
[0096] Figure 4 A flowchart of a general input / output pin verification method provided by another embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the method includes the following steps:
[0097] S401. Build parameter configuration documents and code template engine documents.
[0098] Specifically, the implementation principle and process of S401 and S101 are the same, and will not be repeated here.
[0099] S402: extract configuration parameters from the parameter configuration document, render and fill the code template engine document based on the configuration parameters, and generate a driver component, a monitor component, a scoreboard component, and a target test program.
[0100] Specifically, the implementation principle and process of S402 and S102 are the same, and will not be repeated here.
[0101] S403, integrating the driver component, the monitor component, the scoreboard component and the target test program to obtain a verification environment.
[0102] like Figure 5 As shown, the electronic device can integrate the driver component, monitor component, scoreboard component and target test program to obtain the UVM verification environment. These components can be automatically integrated into the system-level UVM verification environment to jointly complete the end-to-end verification of the GPIO specific function.
[0103] S404, burning the target test program into the target chip to be tested.
[0104] In this step, the electronic device will burn the target test program into the program storage unit of the target chip to be tested. Optionally, the target test program can be burned into the program storage unit of the target chip to be tested by backdoor burning.
[0105] S405: Start the verification environment and start compiling and simulating.
[0106] S406: Execute the target test program through the target chip to be tested.
[0107] S407: The driver component monitors the first flag signal, applies a level driving value to the source end of the general input / output pin, and sends the level driving value to the scoreboard component, wherein the level driving value includes a high level signal or a low level signal.
[0108] In this step, the electronic device will wait for the first flag signal through the driver component. When the first flag signal is detected, the driver component applies a level driving value to the source end of the general input and output pin, and sends the level driving value to the scoreboard component. The level driving value includes a high level signal or a low level signal. In this embodiment, the driver component can monitor the bus in real time and detect the first flag signal from the bus. Optionally, the first flag signal can be a signal that the target register address configuration is completed, without specific limitation.
[0109] S408: Monitor the second flag signal through the monitor component, collect the actual value of the level of the destination end of the general input and output pin, and send the actual value of the level to the scoreboard component.
[0110] In this step, the electronic device will wait for the second flag signal through the monitor component. When the second flag signal is detected, after waiting for the set clock cycle, the monitor component collects the actual value of the level of the destination end of the general input and output pin, and sends the actual value of the level to the scoreboard component. In this embodiment, the driver component can send the second flag signal to the monitor component, and the monitor component receives the second flag signal. Optionally, the second flag signal can be a signal that the level drive value is applied, which is not specifically limited.
[0111] S409: Compare the level driving value with the level actual value through the scoreboard component to obtain the verification result of the general input and output pin.
[0112] In this step, the electronic device compares the level driving value with the level actual value through the scoreboard component and displays the verification result of the general input and output pin.
[0113] In some embodiments, if the level driving value and the actual level value are compared and found to be the same, the GPIO verification succeeds; if the level driving value and the actual level value are compared and found to be different, the GPIO verification fails.
[0114] The disclosed embodiment constructs a parameter configuration document and a code template engine document, extracts the configuration parameters in the parameter configuration document, renders and fills the code template engine document based on the configuration parameters, generates a driver component, a monitor component, a scoreboard component and a target test program, integrates the driver component, the monitor component, the scoreboard component and the target test program, and obtains a verification environment. Further, the target test program is burned onto the target chip to be tested, the verification environment is started, the compilation simulation is started, and the target test program is executed through the target chip to be tested. Then, the first flag signal is monitored by the driver component, a level driving value is applied to the source end of the general input and output pin, and the level driving value is sent to the scoreboard component, the level driving value includes a high level signal or a low level signal, and the second flag signal is monitored by the monitor component, the actual level value of the destination end of the general input and output pin is collected, and the actual level value is sent to the scoreboard component. Then, the level driving value and the actual level value are compared by the scoreboard component to obtain the verification result of the general input and output pin. Through this method, the rapid configuration of GPIO parameters and the automatic application and response reading of signals can be achieved, thereby improving verification efficiency, reducing labor costs and time costs, while avoiding errors introduced by human factors and improving test accuracy and reliability.
[0115] Figure 5 The general input and output pin verification system and verification platform architecture diagram provided by the embodiment of the present disclosure. The general input and output pin verification system is applied to the verification platform, such as Figure 5 As shown, the verification platform includes a parameter configuration document, a code template engine document, a driver component, a monitor component, a scoreboard component and a target test program; the parameter configuration document is used to store a source end path, a destination end path, a register address, a register data, a reference clock and a clock cycle; the code template engine document is used to define the code format template of each component; the target test program is used to combine the driver component, the monitor component and the scoreboard component to verify the general input and output pins; the driver component is used to apply a level driving value to the source end of the general input and output pin; the monitor component is used to collect the actual value of the level of the destination end of the general input and output pin; the scoreboard component is used to compare the level driving value and the actual value of the level to obtain the verification result of the general input and output pin.
[0116] Optional, such as Figure 5 As shown, the verification platform also includes an automation script; the automation script is used to extract the configuration parameters in the parameter configuration document, render and fill the code template engine document based on the configuration parameters, and generate a driver component, a monitor component, a scoreboard component and a target test program.
[0117] Figure 6 The schematic diagram of the structure of the universal input-output pin verification device provided in the embodiment of the present disclosure. The universal input-output pin verification device may be an electronic device as in the above embodiment, or the universal input-output pin verification device may be a component or assembly in the electronic device. The universal input-output pin verification device provided in the embodiment of the present disclosure may execute the processing flow provided in the embodiment of the universal input-output pin verification method, such as Figure 6 As shown, the general input and output pin verification device 50 includes: a construction module 51, a rendering module 52, an execution module 53, and a verification module 54; wherein the construction module 51 is used to construct a parameter configuration document and a code template engine document; the rendering module 52 is used to extract the configuration parameters in the parameter configuration document, render and fill the code template engine document based on the configuration parameters, and generate a driver component, a monitor component, a scoreboard component, and a target test program; the execution module 53 is used to burn the target test program to the target chip to be tested, and execute the target test program through the target chip to be tested; the verification module 54 is used to verify the general input and output pins based on the target test program in combination with the driver component, the monitor component, and the scoreboard component to obtain a verification result.
[0118] Optionally, the parameter configuration document contains multiple column variables, including source path, destination path, register address, register data, reference clock and clock cycle; the code format template of each component is defined in the code template engine document.
[0119] Optionally, the rendering module 52 extracts the configuration parameters in the parameter configuration document, renders and fills the code template engine document based on the configuration parameters, and generates a driver component, a monitor component, a scoreboard component, and a target test program. It is specifically used to: obtain a pre-written automation script; extract the configuration parameters in the parameter configuration document through the automation script, render and fill the code template engine document based on the configuration parameters, and generate a driver component, a monitor component, a scoreboard component, and a target test program.
[0120] Optionally, the execution module 53 burns the target test program onto the target chip to be tested. When the target test program is executed by the target chip to be tested, it is specifically used to: compile the target test program to generate a binary machine file; burn the binary machine file into the program storage unit of the target chip to be tested; and read and execute the binary machine file by the central processing unit of the target chip to be tested.
[0121] Optionally, after generating the driver component, the monitor component, the scoreboard component and the target test program, the device 50 further includes: an integration module 55; the integration module 55 is used to integrate the driver component, the monitor component, the scoreboard component and the target test program to obtain a verification environment;
[0122] Correspondingly, the execution module 53 burns the target test program onto the target chip to be tested. When the target test program is executed by the target chip to be tested, it is specifically used to: burn the target test program onto the target chip to be tested; start the verification environment and start compiling and simulating; and execute the target test program by the target chip to be tested.
[0123] Optionally, the verification module 54 verifies the general input / output pin based on the target test program in combination with the driver component, the monitor component and the scoreboard component. When the verification result is obtained, it is specifically used to: monitor the first flag signal through the driver component, apply a level drive value to the source end of the general input / output pin, and send the level drive value to the scoreboard component, wherein the level drive value includes a high level signal or a low level signal; monitor the second flag signal through the monitor component, collect the actual level value of the destination end of the general input / output pin, and send the actual level value to the scoreboard component; compare the level drive value and the actual level value through the scoreboard component to obtain the verification result of the general input / output pin.
[0124] Figure 6 The general input / output pin verification device of the illustrated embodiment can be used to execute the technical solution of the above method embodiment, and its implementation principle and technical effect are similar, which will not be described in detail here.
[0125] Figure 7 The electronic device provided by the embodiment of the present disclosure can execute the processing flow provided by the embodiment of the general input and output pin verification method, such as Figure 7 As shown, the electronic device 60 includes: a memory 61, a processor 62, a computer program and a communication interface 63; wherein the computer program is stored in the memory 61 and is configured so that the processor 62 executes the general input and output pin verification method as described above.
[0126] In addition, an embodiment of the present disclosure further provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the general input and output pin verification method described in the above embodiment.
[0127] In addition, an embodiment of the present disclosure further provides a computer program product, which includes a computer program or instructions, and when the computer program or instructions are executed by a processor, the general input and output pin verification method as described above is implemented.
[0128] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.
[0129] In some embodiments, the client and the server may communicate using any currently known or future developed network protocol such as HTTP (HyperTextTransferProtocol), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an adhoc peer-to-peer network), as well as any currently known or future developed network.
[0130] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.
[0131] The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device:
[0132] Build parameter configuration documents and code template engine documents;
[0133] Extracting configuration parameters from the parameter configuration document, rendering and filling the code template engine document based on the configuration parameters, and generating a driver component, a monitor component, a scoreboard component, and a target test program;
[0134] Burning the target test program onto a target chip to be tested, and executing the target test program through the target chip to be tested;
[0135] Based on the target test program combined with the driver component, the monitor component and the scoreboard component, the general input and output pins are verified to obtain a verification result.
[0136] In addition, the electronic device may also execute other steps in the general input / output pin verification method described above.
[0137] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages or a combination thereof, including, but not limited to, object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).
[0138] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.
[0139] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of a unit does not, in some cases, constitute a limitation on the unit itself.
[0140] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.
[0141] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
[0142] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0143] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A general input and output pin verification method, characterized in that: The method comprises: Build parameter configuration documents and code template engine documents; Extracting configuration parameters from the parameter configuration document, rendering and filling the code template engine document based on the configuration parameters, and generating a driver component, a monitor component, a scoreboard component, and a target test program; Burning the target test program onto a target chip to be tested, and executing the target test program through the target chip to be tested; Based on the target test program combined with the driver component, the monitor component and the scoreboard component, the general input and output pins are verified to obtain a verification result.
2. The method according to claim 1, characterized in that The parameter configuration document includes a plurality of column variables, and the plurality of column variables include a source end path, a destination end path, a register address, a register data, a reference clock, and a clock cycle; The code format templates of various components are defined in the code template engine document.
3. The method according to claim 1, characterized in that The extracting the configuration parameters in the parameter configuration document, rendering and filling the code template engine document based on the configuration parameters, and generating a driver component, a monitor component, a scoreboard component, and a target test program include: Get pre-written automation scripts; The configuration parameters in the parameter configuration document are extracted by the automation script, and the code template engine document is rendered and filled based on the configuration parameters to generate a driver component, a monitor component, a scoreboard component and a target test program.
4. The method according to claim 1, characterized in that: The step of burning the target test program onto a target chip to be tested and executing the target test program through the target chip to be tested comprises: Compiling the target test program to generate a binary machine file; Burning the binary machine file into the program storage unit of the target chip to be tested; The binary machine file is read and executed by the central processing unit of the target chip to be tested.
5. The method according to claim 1, characterized in that: After generating the driver component, the monitor component, the scoreboard component and the target test program, the method further includes: Integrate the driver component, the monitor component, the scoreboard component and the target test program to obtain a verification environment; Correspondingly, burning the target test program onto the target chip to be tested and executing the target test program through the target chip to be tested includes: Burning the target test program onto the target chip to be tested; Start the verification environment and begin compiling and simulating; The target test program is executed through the target chip to be tested.
6. The method according to claim 1, characterized in that The method of verifying the general input and output pins based on the target test program in combination with the driver component, the monitor component and the scoreboard component to obtain the verification result includes: The driver component monitors the first flag signal, applies a level driving value to the source end of the general input / output pin, and sends the level driving value to the scoreboard component, wherein the level driving value includes a high level signal or a low level signal; The second flag signal is monitored by the monitor component, an actual level value of the destination end of the general input / output pin is collected, and the actual level value is sent to the scoreboard component; The level driving value and the level actual value are compared by the scoreboard component to obtain the verification result of the general input and output pin.
7. A general purpose input and output pin verification system, characterized in that: The general input and output pin verification system is applied to a verification platform, which includes a parameter configuration document, a code template engine document, a driver component, a monitor component, a scoreboard component, and a target test program; The parameter configuration document is used to store the source end path, the destination end path, the register address, the register data, the reference clock and the clock cycle; The code template engine document is used to define the code format templates of each component; The target test program is used to combine the driver component, the monitor component and the scoreboard component to verify the general input and output pins; The driver component is used to apply a level driving value to the source end of the general input and output pin; The monitor component is used to collect the actual value of the level of the destination end of the general input and output pin; The scoreboard component is used to compare the level drive value with the level actual value to obtain the verification result of the general input and output pin.
8. A general purpose input / output pin verification device, characterized in that: include: Construction module, used to build parameter configuration documents and code template engine documents; A rendering module, used to extract the configuration parameters in the parameter configuration document, render and fill the code template engine document based on the configuration parameters, and generate a driver component, a monitor component, a scoreboard component and a target test program; An execution module, used for burning the target test program into a target chip to be tested, and executing the target test program through the target chip to be tested; The verification module is used to verify the general input and output pins based on the target test program in combination with the driver component, the monitor component and the scoreboard component to obtain a verification result.
9. An electronic device, characterized in that: include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and is configured to be executed by the processor to implement the method according to any one of claims 1 to 6.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.