Memory data migration method, memory management system and memory tracking circuit

Abstract

An apparatus for executing a software program, comprising: a processing unit; at least one memory component, each memory component connected to the processing unit and mapped to a memory address range of the processing unit; a memory mapping circuit connected to the processing unit and the memory component and configured to: in each of the plurality of iterations: access a statistical counter collected when the processing unit executes the software program; generating mapping between the first memory address range and the second memory address range under the condition that the first range and the second range are identified according to the analysis of the statistical counter; and in response to a memory access command which is received from the processing unit and comprises a first memory address in the first range, replacing the first memory address in the memory access command with a second memory address in the second range according to the mapping.

Description

[0001] This application is a divisional application. The application number of the original application is 202280092124.X, and the original application date is February 23, 2022. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present invention relates to the field of computers, and in particular to a memory data migration method, a memory management system and a memory tracking circuit. Background Art

[0003] The present invention relates to a computerized device and, more particularly, but not exclusively, to a computerized device having more than one memory component.

[0004] For the sake of brevity, the term "system" is hereinafter used to refer to a computerized system, and the terms are used interchangeably.

[0005] There are numerous metrics used to measure the performance of computerized systems, such as throughput, which is the amount of tasks executed in a determined time interval, and latency, which is the amount of time a task is delayed before being executed. Improving the performance of a system, such as by increasing the throughput of the system and / or reducing the latency of the system, depends on, among other factors, the amount of computer resources available in the system and how well the various components of the system work together. For example, reducing the latency when accessing memory and / or increasing the throughput of memory accesses can improve the performance of a system.

[0006] Memory components with relatively high performance access characteristics, such as low latency memory components or high throughput memory components, such as static RAM (SRAM), are generally more expensive than memory components with lower performance access characteristics, such as dynamic RAM (DRAM). It is common practice to design the memory of a system using more than one type of memory component to balance the cost and performance of the system. Some common system designs organize multiple memory components in multiple memory tiers, where small and fast tiers are above larger and slower tiers as caches for the larger tiers. In some designs, there is a hierarchy of tiers, where only the largest tier is available to software programs, i.e., addressable using the software program's application memory address, and the other tiers in the hierarchy are used as hierarchical caches.

[0007] Some other system designs make all memory tiers addressable using the software program's application memory address. In such systems, the performance of the system is affected by the distribution of the software program's application memory among multiple memory tiers (i.e., among one or more memory components of the system). When the software program's application memory includes multiple application memory regions, performance can be improved when frequently accessed application memory regions are stored in one or more high-performance memory components, while lower-performance memory components are used to store infrequently accessed application memory regions.

[0008] The term non-uniform memory access (NUMA) refers to a computerized system with more than one memory component where some characteristics of memory access from a processing unit to the memory component (e.g., latency and / or throughput) depend on the topology of the system, such as the location of the memory component relative to the processing unit. In a manner similar to the above-described systems, in a system with NUMA, the performance of the system may be affected by the distribution of a software program's application memory among one or more memory components. Summary of the invention

[0009] The present invention includes a description of an apparatus and method for memory management. In some embodiments described herein, a memory mapping circuit is used to map application memory of a software program executed by a processing unit between one or more memory components connected to a processing unit without requiring computation by the processing unit and without affecting a memory mapping table used by an operating system executed by the processing unit. In addition, in these embodiments, the memory mapping circuit is used to replace a first memory address in a first memory address range with a second memory address in a second memory address range in a memory access command received from the processing unit based on a mapping between a first memory address range and a second memory address range, wherein the mapping between the first memory address range and the second memory address range is generated based on an analysis of one or more statistical counters collected when the processing unit executes the software program. Using the memory mapping circuit to generate a mapping between the first memory address range and the second memory address range and replacing memory addresses in the memory access command based on the generated mapping reduces the processing overhead required by the processing unit to update the distribution of multiple application memory regions of the software program between one or more memory components, thereby improving the performance of the apparatus.

[0010] The above and other objects are achieved by the features of the independent claims. Other implementations are apparent from the dependent claims, the description and the drawings.

[0011] According to a first aspect, a device for executing a software program is provided, the device comprising: a processing unit; at least one memory component, each memory component connected to the processing unit and mapped to at least one memory address range of a plurality of memory address ranges of the processing unit; a memory mapping circuit connected to the processing unit and the at least one memory component, the memory mapping circuit being used to: in each management iteration of a plurality of management iterations: access one or more of a plurality of statistical counters collected when the processing unit executes the software program; in a case where the first memory address range and the second memory address range are identified based on an analysis of the one or more statistical counters, generate a mapping between a first memory address range in the plurality of memory address ranges and a second memory address range in the plurality of memory address ranges; in response to at least one memory access command including a first memory address in the first memory address range received from the processing unit, replace the first memory address in the at least one memory access command with a second memory address in the second memory address range according to the mapping.

[0012] According to a second aspect, a method for managing memory in a device for executing one or more software programs is provided, the method comprising: in each of a plurality of management iterations, performing the following operations by a memory mapping circuit connected to a processing unit and at least one memory component connected to the processing unit, wherein each of the at least one memory component is mapped to at least one memory address range among a plurality of memory address ranges of the processing unit: accessing one or more of a plurality of statistical counters collected when the processing unit executes at least one of the one or more software programs; generating a mapping between a first memory address range among the plurality of memory address ranges and a second memory address range among the plurality of memory address ranges in a case where the first memory address range and the second memory address range are identified based on an analysis of the one or more statistical counters; and in response to at least one memory access command including a first memory address in the first memory address range received from the processing unit, replacing the first memory address in the at least one memory access command with a second memory address in the second memory address range according to the mapping.

[0013] According to a third aspect, there is provided a software program product for memory management, the software program product comprising: a non-transitory computer-readable storage medium; first program instructions for: in each of a plurality of management iterations, performing the following operations by a memory mapping circuit connected to a processing unit and to at least one memory component connected to the processing unit, wherein each of the at least one memory component is mapped to at least one memory address range of a plurality of memory address ranges of the processing unit: accessing one or more of a plurality of statistical counters collected when the processing unit executes at least one of one or more software programs; in the case where the first memory address range and the second memory address range are identified based on an analysis of the one or more statistical counters, generating a mapping between a first memory address range in the plurality of memory address ranges and a second memory address range in the plurality of memory address ranges; second program instructions for: in response to at least one memory access command received from the processing unit including a first memory address in the first memory address range, replacing the first memory address in the at least one memory access command with a second memory address in the second memory address range according to the mapping. According to the third aspect, the first program instruction and the second program instruction are executed by at least one computerized processor from the non-transitory computer-readable storage medium.

[0014] In an implementation form of the first aspect and the second aspect, the multiple statistical counters include a high access counter, a low access counter, and a plurality of range access counters, each range access counter being associated with one of the multiple memory address ranges. Optionally, accessing the one or more statistical counters includes: accessing at least one of the low access counter and the high access counter; performing another analysis including at least one of the low access counter and the high access counter; and accessing at least one range access counter based on another result of the another analysis. In addition to the multiple range access counters, using a watermark counter (e.g., a high access counter or a low access counter) helps to reduce the amount of access to the multiple range access counters, thereby reducing the amount of computing resources required for memory mapping compared to a method of accessing all of the multiple range access counters.

[0015] In another implementation form of the first aspect and the second aspect, the apparatus further comprises at least one memory tracking circuit connected to the processing unit and the at least one memory component. Optionally, at least one of the plurality of statistical counters is implemented in the at least one memory tracking circuit, and the at least one memory tracking circuit is used to update at least one of the plurality of statistical counters in each tracking iteration of a plurality of tracking iterations in response to a memory access command received from the processing unit. Compared with the method of implementing statistical counters in a page table of an operating system executed by a processing unit executing a software program, implementing statistical counters in the memory tracking circuit reduces the amount of computing resources required to track one or more memory accesses. Optionally, the memory mapping circuit is further used to access one or more of the plurality of statistical counters by accessing the at least one memory tracking circuit. Optionally, the memory mapping circuit is further used to configure at least one of a low access threshold and a high access threshold in the at least one memory tracking circuit. Optionally, according to another result of another analysis including the one or more statistical counters, the memory mapping circuit configures at least one of the low access threshold and the high access threshold in the at least one memory tracking circuit. Configuring the low access threshold and / or the high access threshold improves the accuracy of the high access counter and the low access counter, and improves the accuracy of the memory map calculated based on the one or more statistical counters.

[0016] In another implementation form of the first aspect and the second aspect, the memory mapping circuit further comprises a plurality of address mappings, each address mapping mapping one of the plurality of memory address ranges to a media address range, wherein the media address range is another memory address range of the plurality of memory address ranges. Mapping one of the plurality of memory address ranges to a media address range that is another memory address range of the plurality of memory address ranges enables moving the application memory area of ​​the software program from one memory component to another memory component without modifying a page table of an operating system that maps the application address of the software program to a physical address of a processing unit, thereby reducing the amount of interruption to one or more services provided by a device that executes the software program. Optionally, generating a mapping between the first memory address range and the second memory address range comprises updating a corresponding media address range of a corresponding address mapping of the first memory address range to the second memory address range. Optionally, the memory mapping circuit is configured to perform the plurality of management iterations when the processing unit executes the software program. Performing the plurality of management iterations of generating the memory mapping when the processing unit executes the software program can improve the performance of the device that executes the software program without increasing the amount of interruption to one or more services provided by the device that executes the software program.

[0017] In another implementation form of the first aspect and the second aspect, the memory mapping circuit is further used to: in the case where the first memory address range and the second memory address range are identified based on the analysis of the multiple statistical counters, copy at least one data value stored in a first memory component in the at least one memory component associated with the first memory address range to a second memory component in the at least one memory component associated with the second memory address range. Optionally, the application memory of the software program includes multiple application memory areas, each application memory area is stored in one of the at least one memory component. Optionally, the at least one data value is a part of at least one application memory area of ​​the multiple application memory areas. Copying one or more data values ​​that are part of the application memory of the software program improves the performance of the device executing the software program without increasing the amount of interruption to one or more services provided by the device executing the software program.

[0018] In yet another implementation of the first aspect and the second aspect, the processing unit executes the software program by executing an operating system having an operating system page size for memory management. Optionally, at least one of the plurality of memory address ranges addresses an amount of memory different from the operating system page size. Using a memory address range having a range size that is not equal to any one of a set of operating system page sizes to map memory improves the accuracy of analysis of one or more statistical counters, thereby improving the performance of the device executing the software program.

[0019] Other systems, methods, features and advantages of the present invention will be or become apparent to those skilled in the art after studying the following drawings and detailed description. It is intended that all such other systems, methods, features and advantages be included in this description, be within the scope of the present invention, and be protected by the accompanying claims.

[0020] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as those known to those of ordinary skill in the art to which the implementation belongs. Although methods and materials similar or equivalent to the methods and materials described herein can be used in the practice or testing of the implementation, exemplary methods and / or materials are described below. In the event of a conflict, this patent specification (including definitions) shall prevail. In addition, these materials, methods and examples are illustrative only and are not necessarily restrictive. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Some embodiments are described herein by way of example only in conjunction with the accompanying drawings. The following detailed descriptions with specific reference to the accompanying drawings emphasize that the details shown are only examples and are for illustrative purposes only in discussing the embodiments. Thus, based on the accompanying drawings, those skilled in the art will readily understand how to practice the embodiments.

[0022] In the attached picture:

[0023] Figure 1 is a schematic block diagram of an exemplary apparatus provided by some embodiments;

[0024] Figure 2 is a schematic block diagram of an exemplary address mapping provided by some embodiments;

[0025] Figure 3 is a schematic block diagram of an exemplary content mapping provided by some embodiments;

[0026] Figure 4 is a schematic block diagram of another exemplary content mapping provided by some embodiments;

[0027] Figure 5 is a flowchart that schematically represents an optional operation flow for memory mapping provided by some embodiments. DETAILED DESCRIPTION

[0028] As used herein, the term "processing unit" refers to any type of programmable or non-programmable circuitry for performing the operations described below. A processing unit may include hardware and software. For example, a processing unit may include one or more processors and a transient or non-transient memory that carries a program that, when executed by the one or more processors, causes the processing unit to perform the corresponding operations.

[0029] In addition, the term "physical address" as used herein refers to the address used by the processing unit in a memory access request to access a memory component. In addition, the term "application address" as used herein refers to the address used in the application. The application address may be a virtual address, in which case the application address needs to be converted to a physical address in order to access one or more memory components. In addition, the term "media address" as used herein refers to an address recognized by a memory component. The processing unit may use a media address in a memory access request. Optionally, a memory address in a memory access request is mapped to a media address. The term "memory mapping" as used herein refers to mapping an application memory address of a software program to a physical address in a memory access request sent by a processing unit. This mapping can be used to convert an application address to a physical address that identifies a location in a memory component where application data or instructions are stored.

[0030] Furthermore, as used herein, the terms "memory access request" and "memory access command" are both used to refer to a request to access a memory component in order to read from and / or write to the memory component, and these terms are used interchangeably. A memory access request may be generated when computer instructions of a software program including memory access computer instructions are executed.

[0031] In addition, the terms "range of memory addresses" and "memory address range" used in this article are both used to refer to the range of memory addresses and can be used interchangeably.

[0032] In order to allocate each of a plurality of application memory regions to one or more memory components connected to a processing unit, thereby improving the performance of the system, some systems track accesses to one or more memory components and use the collected tracking information to identify application memory regions that should be moved from one memory component to another memory component. Some existing tracking methods maintain access counters in a page table used by an operating system executed by the processing unit to map application addresses of software programs to physical addresses of the processing unit. Some such methods update the counters in the page table each time the memory is accessed. Analyzing multiple counters in the page table requires merging counters of multiple virtual pages mapped to a common physical page. Some methods require sorting multiple counters to classify page table entries, for example, to identify page table entries describing high-access application memory regions. In addition, moving an application memory region from one memory component to another memory component requires computing resources of the processing unit to update the page table, and may also require copying the application memory region from one memory component to another memory component. This method reduces the performance of the system because it requires computing resources of the processing unit. In addition, when the page table is updated, one or more services provided by the system executing the software program may be interrupted.

[0033] In order to reduce the amount of computer resources of a processing unit used to map application memory to one or more memory components, in some embodiments described herein, the inventors propose using a memory mapping circuit connected to the processing unit and one or more memory components to generate a mapping between one or more physical addresses of the processing unit and one or more media addresses of the one or more memory components, and replacing the memory address of the memory access command with the media address of one of the memory components in a memory access command received from the processing unit according to the generated mapping. Optionally, the memory address of the memory access command is a first physical memory address in a first memory address range of the processing unit, and the memory address range is one of a plurality of memory address ranges of the processing unit. Optionally, the media address is a second physical memory address in a second memory address range of the plurality of memory address ranges. This mapping between the one or more physical addresses used by the processing unit and the one or more media addresses identified by the one or more memory components enables the application memory region to be moved from one memory component to another without modifying the page table of the operating system that maps the application address of the software program to the physical address of the processing unit. Avoiding modification of the page table reduces the amount of interruption to one or more services provided by the system executing the software program. Optionally, the memory mapping circuit generates the mapping in each of a plurality of management iterations. Optionally, the memory mapping circuit generates the map when the processing unit executes the software program.

[0034] Optionally, the mapping is generated based on an analysis of one or more statistical counters collected when the processing unit executes the software program. Optionally, the statistical counter indicates a plurality of memory access commands. For example, when the processing unit has a plurality of memory address ranges, and each of the one or more memory components is mapped to one or more of the plurality of memory address ranges, the statistical counter may be a range access counter associated with the memory address range, indicating the number of times the memory address range is accessed in the plurality of memory access commands. Optionally, the statistical counter indicates the amount of range access counters that meet the identified criteria. For example, the statistical counter may be a watermark counter indicating the amount of range access counters that exceed a high access threshold, wherein the high access threshold indicates the amount of access to the memory address range that is considered high. Alternatively, the watermark counter may indicate the amount of range access counters that is less than a low access threshold, wherein the low access threshold indicates another amount of access to the memory address range that is considered low. Optionally, the statistical counter indicates the amount of memory access commands received from the processing unit. Optionally, the one or more processing circuits receive the memory access command in each of a plurality of iterations, and update at least one of the plurality of statistical counters in each of the plurality of iterations.

[0035] Performing the analysis by the memory-mapped circuitry reduces the amount of computing resources of the processing unit required to perform the analysis, as compared to performing the analysis by the processing unit, and improves the performance of the system when executing the software program, for example, increasing throughput and / or reducing latency when executing one or more tasks of the software program.

[0036] Optionally, the memory mapping circuit is further configured to copy one or more data values ​​stored in a first memory component of the one or more memory components to a second memory component of the one or more memory components, wherein the first memory component is associated with a first memory address range and the second memory component is associated with a second memory address range. Optionally, the one or more data values ​​are copied from the first memory component to the second memory component when the first memory address range and the second memory address range are identified based on an analysis of the one or more statistical counters. Copying the one or more data values ​​by the memory mapping circuit reduces an amount of disruption to one or more services provided by the system executing the software program as compared to copying the one or more data values ​​by the processing unit.

[0037] Optionally, at least one of the one or more statistics counters is implemented in one or more tracking circuits connected to the processing unit and the one or more memory components. Implementing the statistics counters in the tracking circuits reduces the amount of resources used by the processing unit to track multiple memory accesses, such as reducing the amount of memory accesses performed by the processing unit and / or reducing the amount of processor cycles of the processing unit used to calculate the memory map. Optionally, the memory map circuit is also used to configure the one or more tracking circuits.

[0038] When the processing unit executes the operating system, the operating system can use multiple operating system memory pages to address multiple memory components. It is common practice not to use arbitrary page sizes for multiple operating system memory pages, that is, each of the multiple operating system memory pages has a page size in the identified page size set. When memory access tracking is completed using the page table of the operating system, the granularity of the memory access tracking is based on the corresponding page size of each of the multiple operating system memory pages. In some embodiments described herein, at least one identified memory address range in the multiple memory address ranges has a range size that is not equal to any one in the page size set. Using one or more range access counters to track multiple memory access commands based on multiple memory address ranges supports tracking multiple memory access commands at a granularity different from the page size of the operating system, and improves the accuracy of the memory map calculated according to multiple statistical counters compared to the memory map calculated when tracking according to the operating system page size, thereby improving the accuracy of allocating multiple application memory areas to one or more memory components and improving the performance of the system.

[0039] Before describing at least one embodiment in detail, it should be understood that the embodiments are not necessarily limited to the details of the construction and arrangement of the components and / or methods described in the following description and / or drawings and / or examples. The implementations described herein support other embodiments or support being practiced or executed in various ways.

[0040] The embodiments may be a system, method and / or computer program product. The computer program product may include one or more computer-readable storage media having computer-readable program instructions that cause a processor to perform various aspects of the embodiments.

[0041] The computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. The computer-readable storage medium may be, but is not limited to, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above devices. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, and any suitable combination of the above. The computer-readable storage medium used herein should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0042] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0043] The computer-readable program instructions for performing the operation of the embodiment can be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code, local compilation or real-time compilation (just-in-time, JIT), written in any combination of one or more programming languages, the one or more programming languages ​​include object-oriented programming languages, such as Smalltalk, C++, Java, object-oriented Fortran, etc., interpret programming languages, such as JavaScript, Python, etc., and traditional procedural programming languages, such as "C" programming language, Fortran or similar programming languages. The computer-readable program instructions can be executed entirely on the user's computer, partially on the user's computer; as an independent software package, partially on the user's computer and partially on the remote computer, or completely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), and can also be connected to an external computer (e.g., by using the Internet of an Internet service provider). In some embodiments, electronic circuits including programmable logic circuits, field-programmable gate arrays (FPGAs) or programmable logic arrays (PLAs), etc., can execute computer-readable program instructions to customize the electronic circuits by using state information of the computer-readable program instructions, thereby performing various aspects of the embodiments.

[0044] The present invention is combined with the flowchart and / or block diagram of the method, device (system) and computer program product provided by the embodiment to describe various aspects of the embodiment. It should be understood that each box in the flowchart illustration and / or block diagram and the combination of boxes in the flowchart illustration and / or block diagram can be implemented by computer-readable program instructions.

[0045] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a module for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can instruct a computer, a programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable storage medium storing the instructions includes an article containing the instructions, which are used to implement various aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0046] Computer-readable program instructions can also be loaded into a computer, other programmable data processing apparatus, or other device, so that a series of operating steps are performed on the computer, other programmable apparatus, or other device, thereby producing a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0047] The flow chart and block diagram in the figure illustrate the architecture, function and operation of the possible implementation of the system, method and computer program product provided by various embodiments. In this regard, each box in the flow chart or block diagram can represent a module, a section or a partial instruction, which includes one or more executable instructions for implementing one or more specified logical functions. In some alternative implementations, the function described in the box may not be implemented in the order described in the figure. For example, in fact, the two boxes shown in succession can be executed almost simultaneously, or sometimes in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart and the box combination in the block diagram and / or flow chart can be implemented by a system based on special-purpose hardware, which performs specific functions or actions, or performs a combination of special-purpose hardware and computer instructions.

[0048] Reference now Figure 1 , which shows a schematic block diagram of an exemplary apparatus provided by some embodiments. In these embodiments, the processing unit 101 is connected to at least one memory component 120.

[0049] For the sake of brevity, hereinafter, the term "memory component 120" is used to mean "at least one memory component 120", and these terms are used interchangeably. Optionally, the memory component 120 includes one memory component, such as memory component 120C. Optionally, the memory component 120 includes more than one memory component, such as memory component 120A, memory component 120B, and memory component 120C. The memory component can be a random access memory (random access memory, RAM) component, such as an SRAM component or a DRAM component. Other examples of memory components include read-only memory (read only memory, ROM) components, electrically erasable programmable ROM (electrically erasable programmable ROM, EEPROM) and non-volatile RAM (non-volatile RAM, NVRAM). Optionally, one or more of the memory components 120 are electrically coupled to the processing unit 101. Optionally, one or more of the memory components 120 are connected to the processing unit 101 via a host memory controller (not shown).

[0050] Optionally, one or more of the memory components 120 are cache memory components of the processing unit 101. Optionally, one or more of the memory components 120 are connected to another cache memory component (not shown) that is additionally connected to the processing unit 101.

[0051] Optionally, one or more memory tracking circuits 130 are connected to the processing unit 101 and the memory components 120. Optionally, each memory component 120 is mapped to at least one memory address range of a plurality of memory address ranges of the processing unit 101.

[0052] Now refer to Figure 2 , which shows a schematic block diagram of an exemplary address mapping 200 provided by some embodiments. In this example, the memory component 120A is mapped to the memory address range 201A, the memory address range 201B, and the memory address range 201C of the plurality of memory address ranges 201. Therefore, when the processing unit 101 accesses a memory address in the memory address range 201A, the memory address range 201B, and the memory address range 201C, the processing unit 101 accesses the memory component.

[0053] Similarly, the memory component 120B is mapped to the memory address range 201D of the multiple memory address ranges 201 , and the memory component 120C is mapped to the memory address range 201E and the memory address range 201F of the multiple memory address ranges 201 .

[0054] Optionally, processing unit 101 executes an operating system that uses a plurality of operating system memory pages to address memory component 120. Optionally, each of the plurality of operating system memory pages has a page size that is one of the identified set of page sizes. Optionally, a size of at least one of the plurality of memory address ranges 201 is not a member of the identified set of page sizes.

[0055] Now refer to it again Figure 1 Optionally, a memory mapping circuit 110 is connected to the processing unit 101 and the memory component 120 .

[0056] Optionally, the memory mapping circuit 110 includes a plurality of address mappings. Optionally, each of the plurality of address mappings maps a memory address range in the plurality of memory address ranges 201 to a media address range, wherein the media address range is another memory address range in the plurality of memory address ranges 201 .

[0057] Now refer to Figure 3 , which shows a schematic block diagram of an exemplary memory map 300 provided by some embodiments. In this example, multiple address maps 321 include address map 321A, which maps memory address range 201A to a media address range, which is a memory address range associated with memory component 120A, such as memory address range 201A.

[0058] Similarly, in this example, multiple address mappings 321 include address mapping 321D, which maps memory address range 201D to another media address range, which is another memory address range associated with memory component 120B, such as memory address range 201D.

[0059] Additionally, in this example, the plurality of address mappings 321 includes an address mapping 321E that maps the memory address range 201E to an additional media address range, which is an additional memory address range associated with the memory component 120C, such as the memory address range 201E.

[0060] Further, in this example, the plurality of address mappings 321 include an address mapping 321B that maps the memory address range 201B, an address mapping 321C that maps the memory address range 201C, and an address mapping 321F that maps the memory address range 201F.

[0061] When the application memory of the software program executed by the processing unit 101 includes multiple application memory areas 301, one or more of the multiple memory areas may be stored in one of the memory components and associated with one of the multiple memory address ranges 201. In this example, the application memory area 301A of the multiple application memory areas 301 is stored in the memory component 120A and associated with the memory address range 201A. When the processing unit 101 sends a memory access command to access the application memory area 301A, the memory access command includes a first memory address in the memory address range 201A. When the address mapping 321A maps the memory address range 201A to the media address range as the memory address range 201A, the memory component 120A responds to the memory address command.

[0062] Similarly, application memory area 301B of multiple application memory areas 301 is stored in memory component 120B and associated with memory address range 201D, and application memory area 301C of multiple application memory areas 301 is stored in memory component 120C and associated with memory address range 201E.

[0063] According to some embodiments, the memory mapping circuit 110 optionally generates a new mapping for the memory address ranges of the plurality of memory address ranges 201 .

[0064] Now refer to Figure 4 , which shows a schematic block diagram of another exemplary memory mapping 400 provided by some embodiments. In this example, a new memory mapping 421A is generated instead of the memory mapping 321A, and the memory address range 201A is mapped to a new media address range, such as the memory address range 201F, which is a memory address range in the memory component 120C. Optionally, the application memory area 301A associated with the memory address range 201A is now stored in the memory component 120C instead of being stored in the memory component 120A. In this example, when the processing unit 101 sends a new memory access command to access the application memory area 301A, the new memory access command includes the first memory address in the memory address range 201A. Since in this example, address mapping 421A maps memory address range 201A to a new media address range as memory address range 201F, in some embodiments, memory mapping circuit 120 replaces the first memory address with the second memory address in memory address range 201F in a new memory access command, so that memory component 120C responds to the new memory address command instead of memory component 120A.

[0065] Therefore, in this example, without modifying the page table that maps multiple application memory areas 301 to multiple memory address ranges 201, the processing unit 101 accesses the application memory area 301A using the memory address range 201A, even though the application memory area 301A is now stored in the memory component 120C instead of being stored in the memory component 120A as before.

[0066] To manage memory, the memory mapping circuit 110 in the system 100 may implement the following optional methods.

[0067] Now refer to Figure 5 , which shows a flowchart schematically representing an optional operation flow 500 for memory mapping provided by some embodiments.

[0068] For brevity, the term "mapping circuit" is hereafter used to mean "memory mapping circuit", and the terms may be used interchangeably.

[0069] In these embodiments, in 501, the mapping circuit 110 accesses one or more statistical counters of a plurality of statistical counters collected when the processing unit 101 executes the software program. Optionally, the plurality of statistical counters include a plurality of range access counters, each range access counter being associated with one of the plurality of memory address ranges 201. Optionally, the plurality of statistical counters include one or more watermark counters, each watermark counter being associated with a frequency of access to a memory component. The watermark counter may indicate the amount of memory access ranges accessed at a frequency associated with the watermark counter. The watermark counter may be a high access counter indicating the amount of range access counters exceeding a high access threshold among the plurality of range access counters, thereby indicating frequent access to the corresponding memory component associated with the range access counter exceeding the high access threshold. For example, the range access counter of the memory address range 201A exceeding the high access threshold may indicate frequent access to the memory component 120A associated with the memory address range 201A. Another example of a watermark counter is a low access counter indicating the amount of range access counters exceeding a low access threshold among the plurality of range access counters. There may be more than two watermark counters, each associated with one of the plurality of access frequencies to the memory component. Each of the two or more watermark counters may be associated with an access threshold indicating an access frequency associated therewith, ie indicating an amount of range access counters of the plurality of range access counters exceeding the threshold associated with the watermark counter.

[0070] Optionally, accessing the one or more statistical counters comprises the mapping circuit accessing at least one of a low access counter and a high access counter. Optionally, accessing the one or more statistical counters comprises the mapping circuit performing an initial analysis, the initial analysis comprising accessing the low access counter and / or the high access counter. Optionally, accessing the one or more statistical counters comprises: the mapping circuit accessing at least one range access counter based on an initial result of the initial analysis.

[0071] Optionally, in each of the one or more access iterations, the mapping circuit 110 accesses one of the one or more range access counters at a time. Optionally, in each of the one or more access iterations, the mapping circuit 110 accesses a subset of the plurality of range access counters. Optionally, the management component 110 denies access to at least one range access counter upon identifying a stop condition, e.g., the amount of received range access counters exceeds a threshold value, the threshold value being equal to the value of a previously accessed watermark counter.

[0072] Optionally, at least one of the plurality of statistical counters is implemented in one or more memory tracking circuits 130. Optionally, the one or more memory tracking circuits 130 are configured to update at least one of the plurality of statistical counters in each of the plurality of tracking iterations in response to a memory access command received from the processing unit 101. Optionally, the memory mapping circuit accesses the one or more statistical counters by accessing the one or more memory tracking circuits 130.

[0073] Optionally, at least one other statistic counter of the plurality of statistic counters is implemented in one of the memory components 120. Optionally, one of the memory components implementing at least one other statistic counter is a cache memory component of the processing unit 101. Optionally, at least one other statistic counter of the plurality of statistic counters is implemented in another cache memory component connected to the one or more memory components 120.

[0074] Optionally, when the processing unit 101 executes a software program, the memory mapping circuit 110 accesses one or more statistical counters.

[0075] In 502, the mapping circuit 110 optionally performs an analysis of one or more statistical counters. Optionally, in 507, the mapping circuit 110 identifies a first memory address range (e.g., memory address range 201A) and a second memory address range (e.g., memory address range 201F). Optionally, the mapping circuit 110 identifies the first memory address range and the second memory address range based on the analysis of the one or more statistical counters. For example, when the result of the analysis indicates that the application memory area 301A is accessed frequently using the memory address range 201A, the mapping circuit 110 may identify the memory address range 201A as the first memory address range.

[0076] At 510, mapping circuitry 110 optionally generates a mapping between a first memory address range and a second memory address range, for example, mapping 421A between memory address range 201A and memory address range 201F. Optionally, mapping 421A is generated by updating a media address range of mapping 321A from memory address range 210A to memory address range 201F.

[0077] Optionally, when the processing unit 101 executes the software program, the memory mapping circuit 110 generates the mapping.

[0078] Optionally, in 520, the mapping circuit 110 copies one or more data values ​​(e.g., at least a portion of the application memory area 301A) from the memory component 120A associated with the memory address range 201A to the memory component 120C associated with the memory address range 201F.

[0079] Optionally, before generating mapping 421A and before copying one or more data values, mapping circuitry 110 disables access to memory component 120A and memory component 120C from processing unit 101. Optionally, after copying one or more data values, processing circuitry 110 re-enables access to memory component 120A and memory component 120C from processing unit 101.

[0080] Optionally, copying the one or more data values ​​from memory component 120A to memory component 120C includes: exchanging between the one or more data values ​​and one or more other data values ​​stored in memory component 120C, such that after the exchange, the one or more data values ​​are stored in memory component 120C and the one or more other data values ​​are stored in memory component 120A. Optionally, exchanging between the one or more data values ​​and the one or more other data values ​​includes using one or more intermediate memory regions. Optionally, the one or more intermediate memory regions are located in one of the memory components 120. Optionally, the one or more intermediate memory regions are located in mapping circuit 110.

[0081] Optionally, the mapping circuit 110 repeats one or more of 501, 502, 507, 510 and 520 in each of a plurality of management iterations. Optionally, the mapping circuit 110 performs a plurality of management iterations when the processing unit 101 executes a software program.

[0082] Optionally, in 540, the memory mapping circuit 110 receives one or more memory access commands from the processing unit 101. Optionally, the one or more memory access commands include a first memory address in the memory address range 201A. Optionally, in response to receiving the one or more memory access commands, in 541, the mapping circuit 110 replaces the first memory address in the one or more memory access commands with a second memory address in the memory address range 201F according to the memory map 421A.

[0083] Optionally, the processing unit 101 sends one or more memory access commands when executing a software program, optionally accessing the application memory of the software program, such as the application memory area 301A.

[0084] Optionally, the memory mapping circuit 110 configures one or more of the plurality of thresholds, such as a low access threshold or a high access threshold, in the one or more memory tracking circuits 130. Optionally, the memory mapping circuit 110 performs a further analysis including one or more statistical counters. Optionally, the memory mapping circuit 110 configures one or more thresholds based on a further result of the further analysis.

[0085] Optionally, when the processing unit 101 executes the software program, the memory mapping circuit 110 optionally configures a low access threshold and / or configures a high access threshold in at least one management iteration of the plurality of management iterations.

[0086] The descriptions of various embodiments are for illustrative purposes only, but these descriptions are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles, practical applications, or technological advances of the embodiments, or to enable other persons skilled in the art to understand the embodiments disclosed herein, as compared to existing technologies on the market.

[0087] It is expected that many related memory mapping circuits and memory tracking circuits will be developed during the life of the patent expiring on this application, and the scope of the terms memory mapping circuit and memory tracking circuit are intended a priori to include all such new technologies.

[0088] As used herein, the term "about" refers to ± 10%.

[0089] The terms "including," "having," and variations thereof mean "including but not limited to." This term encompasses the terms "consisting of" and "consisting essentially of.

[0090] The phrase "consisting essentially of" means that the composition or method may include additional ingredients and / or steps, but only if the additional ingredients and / or steps do not materially alter the basic and novel characteristics of the claimed composition or method.

[0091] As used herein, the singular forms "a", "an" and "the" include plural references unless the context clearly indicates otherwise. For example, the term "a compound" or "at least one compound" may include a plurality of compounds, including mixtures thereof.

[0092] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and / or to exclude the incorporation of features of other embodiments.

[0093] As used herein, the word “optionally” means “provided in some embodiments and not provided in other embodiments.” Any particular embodiment may include multiple “optional” features, unless such features are in conflict.

[0094] In the present application, various embodiments can be presented by range format.It should be understood that the description of range format is only for convenience and brevity, and should not be interpreted as a fixed limitation to the scope of the embodiment.Therefore, the description of the range should be considered to have specifically disclosed all possible sub-ranges and the individual numerical values ​​in the range.For example, the description of the range such as from 1 to 6 should be considered to have specifically disclosed the sub-ranges from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc. and the individual numbers such as 1, 2, 3, 4, 5 and 6 in the range.No matter how wide the scope is, this applies.

[0095] When a numerical range is indicated herein, it is meant to include any listed numerals (fractional or integer) within the indicated range. The phrases "range between a first indicated number and a second indicated number" and "range from a first indicated number to a second indicated number" are used interchangeably herein to include the first indicated number and the second indicated number and all fractions and integers between the two.

[0096] It should be understood that certain features of the embodiments described in the context of separate embodiments for the sake of brevity may also be provided in a single embodiment by combination. Conversely, individual features of the embodiments described in the context of a single embodiment for the sake of brevity may also be provided in any other described embodiment individually or by any suitable sub-combination or as appropriate. Certain features described in the context of individual embodiments are not considered essential features of these embodiments, unless the embodiments are inoperable without these elements.

[0097] Although the embodiments have been described in conjunction with their specific embodiments, it is evident that many alternatives, modifications and variations are apparent to those skilled in the art. Therefore, it is intended to encompass all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims.

[0098] It is the purpose of the applicant that all publications, patents and patent applications mentioned in this specification are incorporated herein by reference in their entirety, as if each individual publication, patent or patent application was specifically and individually indicated when it was mentioned to be incorporated herein by reference. In addition, the reference or identification of any reference of the present application cannot be regarded as allowing such reference to take precedence over the present invention in the prior art. With respect to the use of section headings, section headings should not be understood as necessary limitations. In addition, the entire contents of any one or more priority documents of the present application are incorporated herein by reference.

Claims

1. A memory data migration method, characterized in that: The method is applied to a memory system, the memory system comprising a memory tracking circuit, a memory mapping circuit, a first memory component and a second memory component, and the method comprises: The memory tracking circuit tracks memory access commands sent from the processing unit and updates at least one statistical counter; The memory tracking circuitry provides the at least one statistical counter to the memory management component; The memory mapping circuit exchanges data between a first memory component and a second memory component based on statistical data in the at least one statistical technician, wherein the second memory component has higher performance access characteristics than the first memory component.

2. The method according to claim 1, characterized in that The memory management component manages multiple application memory areas, the multiple application memory areas include the application memory area, and the multiple application memory areas correspond to multiple memory address ranges.

3. The method according to claim 1 or 2, characterized in that: The memory tracking circuit tracks the memory access command sent from the processing unit and updates at least one statistical counter, including: The memory access command includes a first address. Based on the first address, a first memory address range corresponding to the first address is determined, and a first statistical counter corresponding to the first memory address range is updated.

4. The method according to claim 3, characterized in that The first memory address range corresponds to the first memory component.

5. The method according to claim 2, characterized in that: The exchanging of data between the first memory component and the second memory component based on the statistical data in the at least one statistical counter comprises: The memory management component performs analysis of the at least one statistical counter; The memory mapping circuit moves data of at least one application memory area among the multiple application memory areas from the first memory component to the second memory component based on the result of the analysis, wherein the multiple application memory areas are memory areas accessible to the software program.

6. The method according to claim 5, characterized in that When the processing unit executes the software program, the memory mapping component maps the multiple application memory areas.

7. The method according to claim 2, characterized in that include: At least one memory address range among the multiple memory address ranges is not equal to the range size of any page size in the page size set.

8. The method according to claim 3 or 4, characterized in that: include: The memory mapping circuit replaces the first address with a second address, where the second address is an address on the second memory component.

9. A memory data migration method, characterized in that: The method is performed by a memory tracking circuit, comprising: tracking memory access commands sent from the processing unit and updating at least one statistical counter; The at least one statistical counter is provided to a memory management component to instruct the memory management component to move an application memory area between a first memory component and a second memory component, wherein the second memory component has higher performance access characteristics than the first memory component, and the application memory area is an area frequently accessed by a software program.

10. The method according to claim 9, characterized in that The tracking of the memory access command sent from the processing unit and updating at least one statistical counter includes: The memory access command includes a first address. Based on the first address, a first memory address range corresponding to the first address is determined, and a first statistical counter corresponding to the first memory address range is updated.

11. The method according to claim 10, characterized in that The first memory address range corresponds to the first memory component.

12. The method according to claim 10, characterized in that include: At least one memory address range among the multiple memory address ranges is not equal to the range size of any page size in the page size set.

13. The method according to any one of claims 10 to 12, characterized in that: include: The first address is replaced with a second address, where the second address is an address on the second memory component.

14. A memory management system, characterized in that: The invention comprises a processing unit, a memory tracking circuit, a memory management component and a plurality of memory components, wherein the memory component comprises a first memory component and a second memory component, wherein the memory tracking circuit is connected to the processing unit, the first memory component and the second memory component: The memory tracking circuit is used to track memory access commands sent from the processing unit and update at least one statistical counter; The memory tracking circuit is further configured to provide the at least one statistical counter to the memory management component; The memory management component is used to access the at least first statistical counter and move data in an application memory area between the first memory component and the second memory component based on the at least one statistical counter, wherein the second memory component has higher performance access characteristics than the first memory component, and the application memory area is a memory area frequently accessed by software programs.

15. The memory management system according to claim 14, characterized in that: include: The at least one statistics counter is located in the memory tracking circuit.

16. The memory management system according to claim 14, characterized in that: include: The at least one statistics counter is located in the first memory component or the second memory component.

17. The memory management system according to any one of claims 14 to 16, characterized in that: The memory management component is also used to manage multiple application memory areas, the multiple application memory areas include the application memory area, and the multiple application memory areas correspond to multiple memory address ranges.

18. The memory management system according to any one of claims 14 to 17, characterized in that: The memory tracking circuit tracks the memory access command sent from the processing unit and updates at least one statistical counter, specifically including: The memory access command includes a first address. Based on the first address, a first memory address range corresponding to the first address is determined, and a first statistical counter corresponding to the first memory address range is updated.

19. The memory management system according to claim 18, characterized in that: The first memory address range corresponds to the first memory component.

20. The memory management system according to claim 15, characterized in that: The exchanging data between the first memory component and the second memory component based on the statistical data in the at least one statistical counter specifically includes: The memory management component performs analysis of the at least one statistical counter; Based on the result of the analysis, at least one of the multiple application memory areas is moved from the first memory component to the second memory component, wherein the multiple application memory areas are memory areas accessible to the software program.

21. The memory management system according to claim 20, characterized in that: The memory management system further comprises a memory mapping component, and the memory mapping component is used to map the plurality of application memory areas when the processing unit executes the software program.

22. The memory management system according to claim 17, characterized in that: include: At least one memory address range among the multiple memory address ranges is not equal to the range size of any page size in the page size set.

23. The memory management system according to claim 18 or 19, characterized in that: include: The memory mapping circuit replaces the first address with a second address, where the second address is an address on the second memory component.

24. A memory tracking circuit, characterized in that: The memory tracking circuit is used to execute the method of any one of claims 9-13.

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