Memory isolation method and device, server, storage medium and program product

Abstract

The invention relates to a memory isolation method and device, a server, a storage medium and a program product. The method comprises the steps that firstly, a memory address of a target memory where single-bit errors occur multiple times is obtained from a preset storage space which can be jointly accessed by an operating system and a BIOS, then, a physical address corresponding to the target memory is determined based on the memory address, the physical address is written into the storage space, and finally, indication information is generated, the indication information is used for indicating the CPU to perform memory isolation on the target memory according to the physical address in the process of running the kernel program. The method can be applied to a platform in which the physical address of the target memory cannot be directly obtained when the CPU runs the operating system, and the application range is wider.

Description

Technical Field

[0001] This application relates to the technical field of operating systems, and particularly to a memory isolation method, apparatus, server, storage medium, and program product. Background Art

[0002] With the development of information technology and the innovation of manufacturing processes, computer systems are becoming increasingly complex, and the reliability requirements for large computer systems are also getting higher and higher. Among them, in a computer system, a single-bit error is a common memory error. If a large number of single-bit errors occur due to hardware failures, it will affect the system performance. Therefore, it is necessary to isolate the memory where a large number of single-bit errors occur during runtime.

[0003] In traditional technologies, the operating system obtains the memory where a large number of single-bit errors occur through register information, and then performs memory isolation on the memory through a page isolation interface.

[0004] However, the method of performing memory isolation on memory in traditional technologies has the problem of poor applicability. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a memory isolation method, apparatus, server, storage medium, and program product that can be applicable to different platforms.

[0006] In a first aspect, this application provides a memory isolation method, which includes:

[0007] Obtain the memory address of a target memory where single-bit errors occur multiple times from a preset storage space; the storage space is a data space jointly accessed by the operating system and the Basic Input / Output System (BIOS);

[0008] Determine the physical address corresponding to the target memory based on the memory address, and write the physical address into the storage space;

[0009] Generate indication information; the indication information is used to indicate the CPU to perform memory isolation on the target memory according to the physical address during the process of running the kernel program.

[0010] In the above memory isolation method, first, when the CPU runs the BIOS program, it obtains the memory address of the target memory that has had single-bit errors occur multiple times from a preset storage space that can be jointly accessed by the operating system and the BIOS. Then, when the CPU runs the BIOS program, it determines the physical address corresponding to the target memory based on the memory address and writes the physical address into the storage space. Finally, when the CPU runs the BIOS program, it generates an indication message, and the indication message is used to indicate that the CPU isolates the target memory according to the physical address during the process of running the kernel program. In this way, when the CPU runs the BIOS program, it can determine the physical address of the target memory that has had single-bit errors occur multiple times, and then write the physical address corresponding to the target memory into the storage space. The storage space is a data space that can be jointly accessed by the operating system and the BIOS program. During the process of running the kernel program, the CPU can isolate the target memory according to the obtained physical address of the target memory. This method can be applied to platforms where the CPU cannot directly obtain the physical address of the target memory during the process of running the operating system, and has a wider scope of application.

[0011] In one embodiment, determining the physical address corresponding to the target memory based on the memory address includes:

[0012] Parsing the memory address to obtain register information related to the physical address; converting the memory address to the physical address according to the register information.

[0013] In this embodiment, when the CPU runs the BIOS program, it obtains the information of the register related to the physical address, and according to the specific content in the register, it realizes the conversion of the memory address to the physical address, solving the problem that the CPU cannot obtain the memory physical address when running Linux application programs in some CPU platforms.

[0014] In one embodiment, the method further includes:

[0015] After writing the physical address into the storage space, obtaining first memory information of the target memory according to the memory address;

[0016] Obtaining the conversion relationship between the memory information of the CPU and the memory information of the motherboard silk screen;

[0017] Determining second memory information of the target memory on the motherboard silk screen according to the first memory information and the conversion relationship, and the second memory information is used to determine the actual location of the target memory.

[0018] In this embodiment, when the CPU runs the BIOS program, it obtains the conversion relationship between the memory information of the CPU and the memory information silk-screened on the motherboard, and then converts the target memory into the memory information silk-screened on the motherboard, so as to determine the position of the target memory on the motherboard silk-screen, that is, to determine the actual position of the target memory, which is convenient for the operation and maintenance personnel to perform fault handling according to the actual position of the target memory.

[0019] In one embodiment, the first memory information includes first memory channel information and first memory module information. Obtaining the conversion relationship between the memory information of the CPU and the memory information silk-screened on the motherboard includes:

[0020] Obtaining the conversion relationship between the memory channel information of the CPU and the memory channels silk-screened on the motherboard, and obtaining the conversion relationship between the memory module information of the CPU and the memory modules silk-screened on the motherboard.

[0021] In this embodiment, when the CPU runs the BIOS program, it obtains the conversion relationship between the memory information of the CPU and the memory information silk-screened on the motherboard, and then converts the target memory into the memory information silk-screened on the motherboard, so as to determine the position of the target memory on the motherboard silk-screen, that is, to determine the actual position of the target memory, which is convenient for the operation and maintenance personnel to perform fault handling according to the actual position of the target memory.

[0022] In one embodiment, the method further includes:

[0023] Writing the second memory information into the storage space so that the CPU saves the second memory information to the log during the process of running the application program.

[0024] In this embodiment, the CPU determines the second memory information of the target memory when running the BIOS program, that is, the position of the target memory on the motherboard silk-screen, and then writes the second memory information into the storage space. When the CPU runs the application program, it obtains the second memory information from the storage space and records it in the log, which is convenient for the operation and maintenance personnel to quickly locate the position of the faulty target memory for replacement, realizing the precise positioning of the faulty memory, thereby reducing the system downtime.

[0025] In one embodiment, obtaining the memory address of the target memory that has had single-bit errors occur multiple times from the preset storage space includes:

[0026] After receiving the interrupt notification sent during the process of the CPU running the application program, obtaining the memory address of the target memory from the storage space; the interrupt notification is sent after the CPU writes the memory address of the target memory into the storage space during the process of running the application program.

[0027] In this embodiment, during the process of the CPU running the BIOS program, it can receive an interrupt notification sent by the CPU during the process of running an application program. This interrupt notification is sent after the CPU writes the memory address of the target memory with a single-bit error into a preset storage space. In this way, during the process of the CPU running the BIOS program, it can timely obtain the memory address of the target memory from the storage space based on the interrupt notification, and then convert the obtained memory address of the target memory into a physical address, thereby achieving memory isolation for the target memory and improving the real-time response ability for handling faulty memory.

[0028] In a second aspect, the present application further provides a memory isolation device, which includes:

[0029] An acquisition module, configured to acquire the memory address of the target memory with multiple single-bit errors from a preset storage space; the storage space is a data space jointly accessible by the operating system and the Basic Input / Output System (BIOS);

[0030] A determination module, configured to determine the physical address corresponding to the target memory based on the memory address and write the physical address into the storage space;

[0031] A generation module, configured to generate an indication message; the indication message is used to indicate that the CPU performs memory isolation on the target memory according to the physical address during the process of running the kernel program.

[0032] In a third aspect, the present application further provides a server, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the memory isolation method according to any one of the first aspects above.

[0033] In a fourth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the memory isolation method according to any one of the first aspects above.

[0034] In a fifth aspect, the present application further provides a computer program product, including a computer program. When the computer program is executed by a processor, it implements the memory isolation method according to any one of the first aspects above.

[0035] The above-mentioned memory isolation method, device, server, storage medium, and program product. First, when the CPU runs the BIOS program, it obtains the memory address of the target memory that has experienced single-bit errors multiple times from a preset storage space that can be jointly accessed by the operating system and the BIOS. Then, when the CPU runs the BIOS program, it determines the physical address corresponding to the target memory based on the memory address and writes the physical address into the storage space. Finally, when the CPU runs the BIOS program, it generates an indication message, which is used to indicate that the CPU isolates the target memory according to the physical address during the process of running the kernel program. In this way, when the CPU runs the BIOS program, it can determine the physical address of the target memory that has experienced single-bit errors multiple times, and then write the physical address corresponding to the target memory into the storage space. The storage space is a data space that can be jointly accessed by the operating system and the BIOS program. During the process of running the kernel program, the CPU can isolate the target memory according to the obtained physical address of the target memory. This method can be applied to platforms where the CPU cannot directly obtain the physical address of the target memory during the process of running the operating system, and has a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for the description of the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0037] Figure 1 It is a schematic diagram of the modules of the existing memory isolation method in one embodiment;

[0038] Figure 2 It is an application environment diagram of the memory isolation method in one embodiment;

[0039] Figure 3 It is a flowchart of the memory isolation method in one embodiment;

[0040] Figure 4 It is a flowchart of the memory isolation method in another embodiment;

[0041] Figure 5 It is a flowchart of the memory isolation method in another embodiment;

[0042] Figure 6 It is a flowchart of the memory isolation method in another embodiment;

[0043] Figure 7 It is a flowchart of the memory isolation method in another embodiment;

[0044] Figure 8 It is a structural block diagram of a memory isolation device in an embodiment;

[0045] Figure 9 It is a structural block diagram of a memory isolation device in another embodiment;

[0046] Figure 10 It is an internal structure diagram of a server in an embodiment. Detailed implementation manners

[0047] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0048] In the traditional technology, as Figure 1 shown, in the Linux system, the operating system includes a Linux application program and a Linux kernel program. The Linux application program includes an error handling module and an error recording and display module. The error handling module obtains the error data collected by the Linux kernel program, and in the form of a daemon process, it records in real time the memory address where a correctable memory error occurs, and makes a judgment according to a threshold. If the correctable error of a memory address exceeds the threshold, it calls the Page Offine interface of the Linux kernel program to isolate the memory address. The error recording and display module records the error information into a custom folder or a system file, and at the same time, through network communication, it can realize the real-time acquisition of various types of error information. The Linux kernel program obtains the error information of the hardware layer such as the CPU or the memory. Since the PageOffine interface provided by the Linux kernel program isolates the physical address of the memory, for some types of CPU platforms, because the Linux application program cannot directly obtain the physical address of the memory, it is impossible to isolate the memory with multiple single-bit errors, resulting in poor applicability of the traditional memory isolation method.

[0049] Based on this, the present application proposes a memory isolation method, which can be applied to such as Figure 1In the application environment shown. Among them, the server includes a CPU, and Linux application programs, Linux kernel programs, and BIOS programs can run on the CPU. When the CPU runs the BIOS program, it can determine the physical address of the target memory where single-bit errors occur multiple times, and then when the CPU runs the BIOS program, it writes the physical address corresponding to the target memory into the storage space. The storage space is a data space that can be jointly accessed by the operating system and the BIOS program. During the process of running the kernel program, the CPU can isolate the target memory according to the obtained physical address of the target memory. This method can be applied to platforms where the CPU cannot directly obtain the physical address of the target memory during the process of running the operating system, and the applicable range is wider.

[0050] In an exemplary embodiment, as Figure 3 shown, a memory isolation method is provided. Taking the server in Figure 2 as an example, the method includes the following steps:

[0051] S301, Obtain the memory address of the target memory where single-bit errors occur multiple times from a preset storage space.

[0052] Among them, the storage space is a data space jointly accessed by the operating system and the Basic Input / Output System (BIOS). In this embodiment, the preset storage space can be that the server pre-divides the storage space in the server based on the access environment information of the operating system and the BIOS, and divides a certain storage area in the server that can be accessed by both the operating system and the BIOS into the preset storage space.

[0053] In this embodiment, the target memory is the memory where single-bit errors occur multiple times determined by the Linux application program running on the CPU. When single-bit errors occur multiple times in the memory, it may affect the system performance. Therefore, it is necessary to process the target memory. Memory isolation processing can be performed on the target memory. Through real-time isolation of the target memory, the memory address of the target memory will not be accessed again. In order to implement memory isolation of the target memory, the Linux application program can write the memory address of the target memory into the above storage space. When the CPU runs the BIOS program, it can read the memory address of the target memory from the storage space when it determines that there is a memory that needs to be memory-isolated.

[0054] S302, Determine the physical address corresponding to the target memory based on the memory address, and write the physical address into the storage space.

[0055] In this embodiment, since the Page Offline interface of the Linux kernel program isolates memory by isolating the physical address of the memory, after obtaining the memory address of the target memory, it is necessary to convert the memory address into the physical address corresponding to the target memory. However, in some CPU platforms, the Linux application program cannot directly obtain the physical address of the target memory. Therefore, in this embodiment, when the CPU runs the BIOS program, it can obtain the value of the register related to the physical address, convert the determined memory address of the target memory into the corresponding physical address according to the value of the register, and then write the physical address into the above storage space, so that the Linux application program can obtain the physical address of the target memory.

[0056] S303, generate indication information for indicating that the CPU isolates the target memory according to the physical address during the process of running the kernel program.

[0057] It should be noted that after the CPU writes the physical address into the above storage space when running the BIOS program, it generates indication information for indicating that the Linux application program obtains the physical address of the target memory from the storage space. Then, when the CPU runs the Linux application program, it can send the physical address to the Linux kernel program. When the CPU runs the Linux kernel program, it isolates the target memory according to the physical address through the Page Offline interface. It can be understood that after isolating the target memory, the address of the target memory will not be accessed again, thereby improving the stability of the operating system.

[0058] In the above memory isolation method, first, when the CPU runs the BIOS program, it obtains the memory address of the target memory that has had single-bit errors occur multiple times from a preset storage space that can be jointly accessed by the operating system and the BIOS. Then, when the CPU runs the BIOS program, it determines the physical address corresponding to the target memory based on the memory address and writes the physical address into the storage space. Finally, when the CPU runs the BIOS program, it generates indication information for indicating that the CPU isolates the target memory according to the physical address during the process of running the kernel program. In this way, when the CPU runs the BIOS program, it can determine the physical address of the target memory that has had single-bit errors occur multiple times, and then write the physical address corresponding to the target memory into the storage space. The storage space is a data space that can be jointly accessed by the operating system and the BIOS program. When the CPU runs the kernel program, it can isolate the target memory according to the obtained physical address of the target memory. This method can be applied to platforms where the CPU cannot directly obtain the physical address of the target memory during the process of running the operating system, and has a wider range of applications.

[0059] In this embodiment, the detailed process of determining the physical address corresponding to the target memory based on the memory address will be described. In one embodiment, as Figure 4 shown, step S202 above includes:

[0060] S401, Parse the memory address to obtain register information related to the physical address.

[0061] S402, Convert the memory address to a physical address according to the register information.

[0062] Since the physical address corresponding to the target memory does not exist in the registers of some CPU platforms, the Linux application programs running on the CPU cannot determine the physical address of the target memory. In this embodiment, when the CPU runs the BIOS program, it can parse the memory address to obtain register information related to the physical address. Through the content of the register information, the memory address of the target memory can be converted into a physical address. Optionally, in this embodiment, according to the preset correspondence between the register information and the physical address, the memory address of the target memory can be converted into the corresponding physical address according to the obtained register information related to the physical address of the target memory.

[0063] In this embodiment, when the CPU runs the BIOS program, it obtains the information of the register related to the physical address, and according to the specific content in the register, it realizes the conversion of the memory address into a physical address, solving the problem that the CPU cannot obtain the physical memory address when running Linux application programs in some CPU platforms.

[0064] In the embodiment of the present application, after determining the target memory with a fault, in order to facilitate the maintenance personnel to determine the actual location of the target memory with a fault and facilitate the replacement of the memory module, the memory address of the target memory can be converted into the actual location of the target memory, that is, the location of the target memory on the motherboard. As Figure 5 shown, the above method further includes:

[0065] S501, After writing the physical address into the storage space, obtain the first memory information of the target memory according to the memory address.

[0066] Optionally, the first memory information may include memory channel information. A memory channel is a physical channel on the motherboard for memory slots. Generally, there are multiple memory slots on the motherboard, and different memory slots are connected to different memory channels. One memory channel can insert one memory module or two memory modules. The first memory information may further include memory module information.

[0067] It can be understood that after determining the memory address of the target memory, the first memory information of the CPU side of the target memory can be determined based on the memory address of the target memory. The first memory information is the memory information of the target memory in the CPU. The operation and maintenance personnel cannot determine the specific location of the target memory printed on the motherboard through the memory information of the CPU, and cannot locate the faulty memory module in a timely manner. Therefore, it is necessary to convert the first memory information.

[0068] S502. Obtain the conversion relationship between the memory information of the CPU and the memory information printed on the motherboard.

[0069] Optionally, there is a one-to-one correspondence between the memory information of the CPU and the memory information printed on the motherboard. The memory information printed on the motherboard is also the actual location information of the memory on the motherboard. By obtaining the conversion relationship between the memory information of the CPU and the memory information printed on the motherboard, the memory information of the CPU can be converted into the memory information printed on the motherboard, which can facilitate the determination of the actual location of the target memory.

[0070] Among them, in one embodiment, the first memory information includes the first memory channel information and the first memory module information. Correspondingly, obtaining the conversion relationship between the memory information of the CPU and the memory information printed on the motherboard may include: obtaining the conversion relationship between the memory channel information of the CPU and the memory channels printed on the motherboard, and obtaining the conversion relationship between the memory module information of the CPU and the memory module information printed on the motherboard.

[0071] Optionally, after the model of the CPU is determined, the conversion relationship between the memory channel information of the CPU and the memory channels printed on the motherboard, and the conversion relationship between the memory module information of the CPU and the memory module information printed on the motherboard can be obtained by reading the configuration file.

[0072] S503. Determine the second memory information of the target memory printed on the motherboard according to the first memory information and the conversion relationship.

[0073] Among them, the second memory information is used to determine the actual location of the target memory.

[0074] In this embodiment, according to the first memory information of the target memory and the conversion relationship determined above, the memory information of the CPU of the target memory can be converted into the memory information printed on the motherboard, that is, the second memory information.

[0075] In this embodiment, when the CPU runs the BIOS program, it obtains the conversion relationship between the memory information of the CPU and the memory information printed on the motherboard, and then converts the target memory into the memory information printed on the motherboard, so as to be able to determine the location of the target memory printed on the motherboard, that is, to determine the actual location of the target memory, which is convenient for the operation and maintenance personnel to perform fault handling according to the actual location of the target memory.

[0076] Optionally, as a further implementation, the second memory information can also be written into the storage space so that the CPU saves the second memory information to the log during the process of running the application program. Furthermore, the CPU can obtain the second memory information from the storage space during the process of running the application program and then record it in the log, which facilitates the operation and maintenance personnel to determine the actual location information of the target memory that has had multiple correctable memory errors through the second memory information.

[0077] In this embodiment, the CPU determines the second memory information of the target memory when running the BIOS program, that is, the location of the target memory on the motherboard silkscreen, and then writes the second memory information into the storage space. When the CPU runs the application program, it obtains the second memory information from the storage space and records it in the log, which facilitates the operation and maintenance personnel to quickly locate the location of the faulty target memory for replacement, achieving precise positioning of the faulty memory, thereby reducing the system downtime.

[0078] In one embodiment, obtaining the memory address of the target memory that has had single-bit errors multiple times from the preset storage space includes: after receiving the interrupt notification sent by the CPU during the process of running the application program, obtaining the memory address of the target memory from the storage space, where the interrupt notification is sent by the CPU after writing the memory address of the target memory into the storage space during the process of running the application program.

[0079] Optionally, after the CPU determines the target memory with correctable memory errors exceeding the threshold during the process of running the application program, it writes the memory address of the target memory into the storage space, and then notifies the BIOS program by means of an interrupt. After receiving the interrupt notification sent by the CPU, the CPU obtains the memory address of the target memory written by the CPU during the process of running the application program from the storage space during the process of running the BIOS program. Optionally, the CPU can call the BIOS program to run by allocating time slices.

[0080] As an alternative implementation, the interrupt notification can also be sent by the CPU when it starts to write the memory address of the target memory into the storage space during the process of running the application program. After receiving the interrupt notification sent during the process of the CPU running the application program, after waiting for a preset duration, the CPU obtains the memory address of the target memory written by the CPU from the storage space during the process of running the BIOS program.

[0081] In this embodiment, when the CPU receives an interrupt notification sent during the execution of an application program while running the BIOS program, the CPU can timely obtain the memory address of the target memory from the storage space based on the interrupt notification during the execution of the BIOS program, and then convert the obtained memory address of the target memory into a physical address. During the execution of the kernel program, the CPU implements memory isolation for the target memory according to the physical address of the target memory, thereby improving the real-time response ability for handling faulty memories.

[0082] For the convenience of those skilled in the art, the following provides a detailed introduction to the memory isolation method provided in this application, as Figure 6 shown. The method may include:

[0083] S1. The Linux application of the operating system running on the CPU periodically searches for the register information of the MCA (Machine Check Architecture) of the target CPU platform.

[0084] S2. The Linux application determines the memory address of the target memory whose number of correctable memory errors exceeds a preset threshold, and writes the memory address of the target memory into the storage space.

[0085] The Linux application determines the memory addresses where memory correctable errors occur according to the obtained register information, and makes statistics. The memory whose number of correctable memory errors exceeds the preset threshold is determined as the target memory, and the memory address corresponding to the target memory is determined.

[0086] S3. The Linux application notifies the BIOS program through an interrupt.

[0087] S4. The BIOS program obtains the memory address of the target memory from the storage space.

[0088] S5. The BIOS program parses the memory address to obtain the register information related to the physical address.

[0089] S6. The BIOS program converts the memory address into a physical address according to the register information.

[0090] S7. The BIOS program writes the physical address into the storage space.

[0091] S8. The Linux application obtains the physical address of the target memory from the storage space and sends the physical address to the Page Offine interface of the Linux kernel program.

[0092] S9. The Linux kernel program performs memory isolation on the physical address through the Page Offine interface.

[0093] It should be noted that for the descriptions in S1 - S9 above, reference can be made to the relevant descriptions in the above embodiments, and the effects are similar. Therefore, they will not be elaborated in this embodiment.

[0094] The process provided in this application for converting the memory information of the CPU into the memory information of the motherboard silk screen, as Figure 7 shown, includes:

[0095] S1, the Linux application running on the CPU periodically searches for the MCA (Machine Check Architecture) register information of the target CPU platform.

[0096] S2, the Linux application determines the memory address of the target memory whose number of correctable memory errors exceeds a preset threshold, and writes the memory address of the target memory into the storage space.

[0097] S3, the Linux application notifies the BIOS program through an interrupt.

[0098] S4, the BIOS program obtains the memory address of the target memory from the storage space.

[0099] S5, the BIOS program parses the memory address to obtain the first memory information of the target memory.

[0100] The first memory information includes the first memory channel information and the first memory module information.

[0101] S6, the BIOS program obtains the conversion relationship between the memory channel information of the CPU and the memory channels of the motherboard silk screen.

[0102] S7, the BIOS program obtains the conversion relationship between the memory module information of the CPU and the memory module information of the motherboard silk screen.

[0103] S8, the BIOS program determines the second memory information of the target memory on the motherboard silk screen according to the first memory information and the conversion relationship.

[0104] S9, the BIOS program writes the second memory information into the storage space.

[0105] S10, the Linux application obtains the second memory information from the storage space and saves the second memory information to the log.

[0106] It should be noted that for the descriptions in S1 - S10 above, reference can be made to the relevant descriptions in the above embodiments, and the effects are similar. Therefore, they will not be elaborated in this embodiment.

[0107] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown according to the indications of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0108] Based on the same inventive concept, an embodiment of the present application also provides a memory isolation device for implementing the above-mentioned memory isolation method. The implementation solution provided by this device to solve the problem is similar to the implementation solution described in the above method. Therefore, the specific limitations in one or more embodiments of the memory isolation device provided below can refer to the limitations on the memory isolation method in the above text, and will not be repeated here.

[0109] In an exemplary embodiment, as Figure 8 shown, a memory isolation device is provided, including: an acquisition module 11, a determination module 12, and a generation module 13, where:

[0110] The acquisition module 11 is configured to acquire the memory address of the target memory that has had a single-bit error occur multiple times from a preset storage space; the storage space is a data space jointly accessed by the operating system and the basic input / output system BIOS;

[0111] The determination module 12 is configured to determine the physical address corresponding to the target memory based on the memory address and write the physical address into the storage space;

[0112] The generation module 13 is configured to generate indication information; the indication information is used to instruct the CPU to perform memory isolation on the target memory according to the physical address during the process of running the kernel program.

[0113] The memory isolation device provided in this embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, and will not be repeated here.

[0114] In one embodiment, the above determination module 12 is specifically configured to parse the memory address to obtain register information related to the physical address; and convert the memory address into a physical address according to the register information.

[0115] The memory isolation device provided in this embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, and will not be repeated here.

[0116] In one embodiment, as Figure 9 shown, the above device further includes a memory information acquisition module 14, a conversion relationship acquisition module 15, and a position determination module 16, where:

[0117] The memory information acquisition module 14 is configured to, after writing a physical address into a storage space, acquire first memory information of a target memory according to a memory address.

[0118] The conversion relationship acquisition module 15 is configured to acquire a conversion relationship between the memory information of the CPU and the memory information printed on the motherboard silkscreen.

[0119] The position determination module 16 is configured to determine second memory information printed on the motherboard silkscreen of the target memory according to the first memory information and the conversion relationship, and the second memory information is used to determine the actual position of the target memory.

[0120] The memory isolation device provided in this embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, which will not be elaborated here.

[0121] In one embodiment, the first memory information includes first memory channel information and first memory module information. The conversion relationship acquisition module 15 is specifically configured to acquire a conversion relationship between the memory channel information of the CPU and the memory channels printed on the motherboard silkscreen, and acquire a conversion relationship between the memory module information of the CPU and the memory modules printed on the motherboard silkscreen.

[0122] The memory isolation device provided in this embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, which will not be elaborated here.

[0123] In one embodiment, the above device further includes a writing module 17, and the writing module 17 is configured to write the second memory information into the storage space so that the CPU saves the second memory information to a log during the process of running an application program.

[0124] The memory isolation device provided in this embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, which will not be elaborated here.

[0125] In one embodiment, the above acquisition module 11 is specifically configured to, after receiving an interrupt notification sent by the CPU during the process of running an application program, acquire the memory address of the target memory from the storage space; the interrupt notification is sent by the CPU after writing the memory address of the target memory into the storage space during the process of running an application program.

[0126] The memory isolation device provided in this embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, which will not be elaborated here.

[0127] Each module in the above memory isolation device can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above modules can be embedded in the processor in the server in hardware form or be independent of the processor, or can be stored in the memory in the server in software form, so that the processor can call and execute the operations corresponding to each of the above modules.

[0128] In one embodiment, a server is provided, and its internal structure diagram can be as Figure 10 shown. The server includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O), and a communication interface. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the server is used to provide computing and control capabilities. The memory of the server includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the server is used to store memory addresses and memory information data. The input / output interface of the server is used to exchange information between the processor and external devices. The communication interface of the server is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it implements a memory isolation method.

[0129] Those skilled in the art can understand that Figure 10 the structure shown in

[0130] is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the server to which the solution of the present application is applied. The specific server may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0131] In one embodiment, when the processor executes the computer program, the following steps are implemented: parsing the memory address to obtain register information related to the physical address; converting the memory address to the physical address according to the register information.

[0132] In one embodiment, when the processor executes a computer program, the following steps are implemented: after writing a physical address into a storage space, obtain first memory information of a target memory according to a memory address; obtain a conversion relationship between the memory information of the CPU and the memory information of the motherboard silk screen; according to the first memory information and the conversion relationship, determine second memory information of the target memory on the motherboard silk screen, and the second memory information is used to determine the actual location of the target memory.

[0133] In one embodiment, the first memory information includes first memory channel information and first memory module information. When the processor executes a computer program, the following steps are implemented: obtain a conversion relationship between the memory channel information of the CPU and the memory channels of the motherboard silk screen, and obtain a conversion relationship between the memory module information of the CPU and the memory module information of the motherboard silk screen.

[0134] In one embodiment, when the processor executes a computer program, the following steps are implemented: write the second memory information into the storage space so that the CPU saves the second memory information to a log during the process of running an application program.

[0135] In one embodiment, when the processor executes a computer program, the following steps are implemented: after receiving an interrupt notification sent during the process of the CPU running an application program, obtain the memory address of the target memory from the storage space; the interrupt notification is sent after the CPU writes the memory address of the target memory into the storage space during the process of running an application program.

[0136] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: obtain the memory address of a target memory that has had a single-bit error occur multiple times from a preset storage space; the storage space is a data space jointly accessed by an operating system and a basic input / output system BIOS; determine the physical address corresponding to the target memory based on the memory address and write the physical address into the storage space; generate an indication information; the indication information is used to indicate that the CPU performs memory isolation on the target memory according to the physical address during the process of running a kernel program.

[0137] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: parse the memory address to obtain register information related to the physical address; convert the memory address into a physical address according to the register information.

[0138] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: after writing the physical address into the storage space, obtain the first memory information of the target memory according to the memory address; obtain the conversion relationship between the memory information of the CPU and the memory information of the motherboard silkscreen; according to the first memory information and the conversion relationship, determine the second memory information of the target memory in the motherboard silkscreen, and the second memory information is used to determine the actual location of the target memory.

[0139] In one embodiment, the first memory information includes the first memory channel information and the first memory module information. When the computer program is executed by a processor, the following steps are further implemented: obtain the conversion relationship between the memory channel information of the CPU and the memory channels of the motherboard silkscreen, and obtain the conversion relationship between the memory module information of the CPU and the memory module information of the motherboard silkscreen.

[0140] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: write the second memory information into the storage space so that the CPU saves the second memory information to the log during the process of running the application program.

[0141] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: after receiving the interrupt notification sent during the process of the CPU running the application program, obtain the memory address of the target memory from the storage space; the interrupt notification is sent after the CPU writes the memory address of the target memory into the storage space during the process of running the application program.

[0142] In one embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0143] Obtain the memory address of the target memory where single-bit errors occur multiple times from a preset storage space; the storage space is a data space jointly accessed by the operating system and the basic input / output system BIOS; determine the physical address corresponding to the target memory based on the memory address and write the physical address into the storage space; generate indication information; the indication information is used to indicate that the CPU performs memory isolation on the target memory according to the physical address during the process of running the kernel program.

[0144] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: parse the memory address to obtain register information related to the physical address; convert the memory address into a physical address according to the register information.

[0145] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: after writing a physical address into a storage space, obtain first memory information of a target memory according to a memory address; obtain a conversion relationship between memory information of a CPU and memory information of a motherboard silk screen; and determine second memory information of the target memory on the motherboard silk screen according to the first memory information and the conversion relationship, where the second memory information is used to determine an actual location of the target memory.

[0146] In one embodiment, the first memory information includes first memory channel information and first memory module information. When the computer program is executed by a processor, the following steps are further implemented: obtain a conversion relationship between memory channel information of a CPU and a memory channel of a motherboard silk screen, and obtain a conversion relationship between memory module information of a CPU and memory module information of a motherboard silk screen.

[0147] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: write the second memory information into the storage space so that the CPU saves the second memory information to a log during the process of running an application program.

[0148] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: after receiving an interrupt notification sent during the process of the CPU running an application program, obtain a memory address of the target memory from the storage space; the interrupt notification is sent after the CPU writes the memory address of the target memory into the storage space during the process of running the application program.

[0149] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with relevant regulations.

[0150] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memories can include read-only memory (ROM), magnetic tapes, floppy disks, flash memories, optical memories, high-density embedded non-volatile memories, resistive random access memories (ReRAM), magnetoresistive random access memories (MRAM), ferroelectric random access memories (FRAM), phase change memories (PCM), graphene memories, etc. Volatile memories can include random access memory (RAM) or external cache memories, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logics, data processing logics based on quantum computing, etc., without limitation.

[0151] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0152] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A memory isolation method, characterized in that, the method includes: Obtaining the memory address of a target memory that has had single-bit errors occur multiple times from a preset storage space; the storage space is a data space jointly accessed by the operating system and the Basic Input / Output System (BIOS); Determining the physical address corresponding to the target memory based on the memory address, and writing the physical address into the storage space; Generating indication information; the indication information is used to instruct the Central Processing Unit (CPU) to perform memory isolation on the target memory according to the physical address during the process of running the kernel program.

2. The method according to claim 1, characterized in that, the determining the physical address corresponding to the target memory based on the memory address includes: Parsing the memory address to obtain register information related to the physical address; Converting the memory address into the physical address according to the register information.

3. The method according to any one of claims 1 to 2, characterized in that, the method further includes: After writing the physical address into the storage space, obtaining first memory information of the target memory according to the memory address; Obtaining the conversion relationship between the memory information of the CPU and the memory information printed on the motherboard; Determining second memory information of the target memory printed on the motherboard according to the first memory information and the conversion relationship, and the second memory information is used to determine the actual location of the target memory.

4. The method according to claim 3, characterized in that, the first memory information includes first memory channel information and first memory module information, and the obtaining the conversion relationship between the memory information of the CPU and the memory information printed on the motherboard includes: Obtaining the conversion relationship between the memory channel information of the CPU and the memory channels printed on the motherboard, and obtaining the conversion relationship between the memory module information of the CPU and the memory modules printed on the motherboard.

5. The method according to claim 4, characterized in that, the method further includes: Writing the second memory information into the storage space so that the CPU saves the second memory information to the log during the process of running the application program.

6. The method according to claim 1, characterized in that, the obtaining the memory address of a target memory that has had single-bit errors occur multiple times from a preset storage space includes: After receiving an interrupt notification sent by the CPU during the process of running the application program, obtaining the memory address of the target memory from the storage space; the interrupt notification is sent after the CPU writes the memory address of the target memory into the storage space during the process of running the application program.

7. A memory isolation device, characterized in that, the device includes: An obtaining module, configured to obtain the memory address of a target memory that has had single-bit errors occur multiple times from a preset storage space; the storage space is a data space jointly accessed by the operating system and the Basic Input / Output System (BIOS); A determination module, configured to determine a physical address corresponding to the target memory based on the memory address, and write the physical address into the storage space; A generation module, configured to generate indication information; the indication information is used to instruct the CPU to perform memory isolation on the target memory according to the physical address during the running of the kernel program.

8. A server, including a memory and a processor, where the memory stores a computer program, characterized in that, when the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium, on which a computer program is stored, characterized in that, when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, including a computer program, characterized in that, when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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