Multi-request address merging method
By storing data in multiple blocks of RAM and processing requests in grouped, the problem of low efficiency of request address merging in parallel calculations is solved, and efficient data access and circuit performance improvement is achieved.
Patent Information
- Application Number
- CN202411948900.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-04-25
AI Technical Summary
In parallel computing, since the memory can only respond to a limited number of requests, it is necessary to merge a large number of request addresses and request storage in multiple cycles, which is less efficient.
By storing the data in k block RAM and grouping the original m data requests according to the result of the address modulo k, a request list corresponding to k RAM is obtained, requests are processed one by one, requests of the same address are merged, and the number of interactions is reduced.
It significantly improves data access efficiency, reduces circuit complexity, enables the circuit to operate at higher frequencies, improves the overall performance of the system, and reduces power consumption.
Smart Images
Figure CN119883969A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of computer technology, and in particular relates to a method for merging multiple request addresses. Background Art
[0002] Parallel computing is an algorithm that executes multiple instructions simultaneously. Its purpose is to increase computing speed and solve large and complex computational problems by expanding the scale of problem solving. Parallel computing can be categorized as temporal and spatial. Temporal parallelism refers to pipelining, while spatial parallelism involves the concurrent execution of computations by multiple processors. Spatial parallelism typically involves multiple processors simultaneously requesting large amounts of data. Storage systems, however, have a limited number of requests that can be processed simultaneously, necessitating address merging and storage requests over multiple cycles.
[0003] However, data that needs to be used repeatedly in large quantities in parallel computing is generally stored in on-chip RAM, but RAM only provides two read interfaces. Summary of the Invention
[0004] The purpose of the present invention is to provide a method for merging multiple request addresses in order to solve the above-mentioned problem.
[0005] The technical solution adopted by the present invention is as follows: a method for merging multiple request addresses, the method comprising the following steps:
[0006] S1: Store data in k blocks of RAM, where data whose address modulo k result is 0 is stored in RAM0, data whose address modulo k result is 1 is stored in RAM1, and so on;
[0007] S2: Group the original m data requests according to the result of address modulo k to obtain a request list corresponding to k RAMs;
[0008] S3: For each set of requests for each RAM, perform the following operations:
[0009] S3-1. Find the first valid address in the group (i.e., the valid bit corresponding to the address is 1);
[0010] S3-2. Issue a request to the address;
[0011] S3-3. Set all valid bits in the group that are the same as the address to 0.
[0012] S3-4. If the group has no valid address request, the group is processed;
[0013] S4: Repeat steps S2 and S3 until all address requests are sent;
[0014] S5: Provides a variety of pre-defined grouping strategies, such as polling, random, based on address distribution, etc. Users can choose the appropriate strategy based on the distribution characteristics of data requests. Provides a variety of pre-defined grouping strategies, users can choose the appropriate strategy based on the distribution characteristics of data requests.
[0015] S6: Design a circuit based on the above algorithm. The circuit design should take into account the circuit complexity and operating frequency to ensure the performance of the system.
[0016] S7: Test the designed circuit to verify its functionality and performance. Optimize based on the test results, such as adjusting grouping strategies and optimizing circuit design, to improve system efficiency and reliability.
[0017] S8: Apply this method to parallel computing scenarios, such as multi-core processors, GPUs, etc., to improve data access efficiency and computing speed.
[0018] S9: Continuously improve the grouping strategy and circuit design to adapt to new application scenarios and requirements, and then end the entire multi-request address merging process.
[0019] In a preferred embodiment, in step S1, the RAM selects k to be a power of 2, such as 2, 4, 8, etc., to facilitate subsequent modulo operations and improve the parallel processing capability of the circuit;
[0020] Create an address mapping table to record the data storage location corresponding to each address so as to quickly locate the RAM where the data is located.
[0021] In a preferred embodiment, in step S2, each data request includes two parts: an address and a valid bit. The address indicates the storage location of the requested data, and the valid bit indicates whether the request is valid.
[0022] The grouping strategy is to group m data requests according to the address modulo k, obtaining request lists corresponding to k RAMs. Each RAM's request list is then divided into n groups according to a predefined grouping strategy, with each group containing n requests.
[0023] Predefined grouping strategies include round-robin, random, and address-based distribution. Users can select the appropriate strategy based on the distribution characteristics of data requests.
[0024] Allows users to customize grouping strategies to meet specific needs and group data based on data access patterns or priorities.
[0025] In a preferred embodiment, in step S3, after obtaining n pending requests for all RAMs, two different valid addresses are selected to issue requests. If no valid address exists, the request corresponding to that RAM has been processed. If all valid addresses are the same, only one request is issued. If no valid address exists for any group, the data request processing is complete.
[0026] In a preferred embodiment, in step S4, during the loop processing, the grouping strategy and the request merging strategy can be adjusted according to actual conditions to improve the processing efficiency of data requests. During the loop processing, the grouping strategy and the request merging strategy can be adjusted according to actual conditions to improve the processing efficiency of data requests.
[0027] In a preferred embodiment, in step S5, the predefined grouping strategies include round-robin, random, and address-based distribution.
[0028] In a preferred embodiment, in step S6, module division: the entire circuit is divided into an address calculation module, a grouping module, a request processing module, etc., to improve the modularity and maintainability of the circuit.
[0029] Circuit optimization is performed based on circuit test results, such as adjusting circuit structure and optimizing circuit parameters, to improve circuit performance and reliability.
[0030] In a preferred embodiment, in step S7, testing the designed circuit includes functional testing;
[0031] Functional testing includes:
[0032] Verify the correctness of the address mapping table to ensure that each address is correctly mapped to the corresponding RAM. Verify the accuracy of the grouping module to ensure that each request is correctly assigned to the corresponding RAM and group. Verify the correctness of the request processing module to ensure that requests are issued in order of priority and that the valid bit is updated correctly. Verify the stability of the circuit to ensure that the circuit can remain stable under long-term operation.
[0033] Performance testing includes: evaluating the circuit's operating frequency to ensure it meets the system's performance requirements; evaluating the efficiency of data request processing to determine how many requests can be processed per cycle; and evaluating the circuit's power consumption to ensure it remains within acceptable limits.
[0034] In a preferred embodiment, in step S8, the method is applied to a multi-core processor, each core can independently issue a request, and the requests are merged and sent to the memory through the method.
[0035] When this method is applied to a GPU, multiple threads in the GPU can concurrently issue requests, and this method can be used to merge the requests and send them to the video memory.
[0036] When this method is applied to a memory controller, the memory controller can merge multiple requests and send them to the memory to improve memory access efficiency.
[0037] When this method is applied to a storage device, the storage device can merge multiple requests and send them to a hard disk or SSD, thereby improving the read and write efficiency of the storage device.
[0038] In a preferred embodiment, in the above step S9, a more efficient grouping strategy is studied. Through a grouping strategy based on machine learning, future request distribution can be predicted based on historical information of data requests, thereby selecting a more appropriate grouping strategy.
[0039] Research more efficient request merging strategies. Through request merging strategies based on compression algorithms, multiple requests can be compressed into one request, thereby reducing the number of requests and the amount of data transmitted.
[0040] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:
[0041] 1. In the present invention, by merging multiple data requests into a small number of requests, the number of interactions with the memory is effectively reduced, thereby significantly improving data access efficiency. At the same time, this method reduces the complexity of the circuit, making the circuit design simpler and easier to implement. The group address merging method enables the circuit to operate at a higher frequency, thereby improving the overall performance of the system. A programmable grouping strategy is adopted, and an appropriate grouping strategy can be selected according to the distribution characteristics of the data requests, thereby improving the flexibility of the method. This method can be applied to a variety of parallel computing scenarios, including multi-core processors, GPUs, memory controllers, storage devices, etc., and has a wide range of applicability.
[0042] 2. In the present invention, by reducing the number of interactions with the memory, the power consumption of the circuit can be reduced, thereby improving the energy efficiency of the system. This method can improve data access efficiency, reduce circuit complexity, increase circuit operating frequency, etc., thereby improving the overall performance of the system. In addition, this method can reduce system costs and improve the user experience. This multi-request address merging method has multiple beneficial effects, and can effectively improve data access efficiency, reduce circuit complexity, increase circuit operating frequency, improve flexibility, improve adaptability, reduce power consumption, improve system performance, reduce costs, and improve user experience. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] Figure 1 It is the overall flow chart of the present invention;
[0044] Figure 2 This is the data distribution diagram of the present invention;
[0045] Figure 3 A schematic diagram of the corresponding relationship between requests and RAM in the present invention;
[0046] Figure 4 Schematic diagram of data request grouping in the present invention. DETAILED DESCRIPTION
[0047] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.
[0048] Example:
[0049] Reference Figure 1-4 A method for merging multiple request addresses includes the following steps:
[0050] S1: Store data in k blocks of RAM, where data whose address modulo k result is 0 is stored in RAM0, data whose address modulo k result is 1 is stored in RAM1, and so on;
[0051] S2: Group the original m data requests according to the result of address modulo k to obtain a request list corresponding to k RAMs;
[0052] S3: For each set of requests for each RAM, perform the following operations:
[0053] S3-1. Find the first valid address in the group (i.e., the valid bit corresponding to the address is 1);
[0054] S3-2. Issue a request to the address;
[0055] S3-3. Set all valid bits in the group that are the same as the address to 0.
[0056] S3-4. If the group has no valid address request, the group is processed;
[0057] S4: Repeat steps S2 and S3 until all address requests are sent;
[0058] S5: Provides a variety of pre-defined grouping strategies, such as polling, random, based on address distribution, etc. Users can choose the appropriate strategy based on the distribution characteristics of data requests. Provides a variety of pre-defined grouping strategies, users can choose the appropriate strategy based on the distribution characteristics of data requests.
[0059] S6: Design a circuit based on the above algorithm. The circuit design should take into account the circuit complexity and operating frequency to ensure the performance of the system.
[0060] S7: Test the designed circuit to verify its functionality and performance. Optimize based on the test results, such as adjusting grouping strategies and optimizing circuit design, to improve system efficiency and reliability.
[0061] S8: Apply this method to parallel computing scenarios, such as multi-core processors, GPUs, etc., to improve data access efficiency and computing speed.
[0062] S9: Continuously improve the grouping strategy and circuit design to adapt to new application scenarios and requirements, and then end the entire multi-request address merging process.
[0063] In step S1, the RAM selects k to be a power of 2, such as 2, 4, 8, etc., to facilitate subsequent modulo operations and improve the parallel processing capability of the circuit;
[0064] Create an address mapping table to record the data storage location corresponding to each address so as to quickly locate the RAM where the data is located.
[0065] In step S2, each data request includes two parts: an address and a valid bit. The address indicates the storage location of the requested data, and the valid bit indicates whether the request is valid.
[0066] The grouping strategy is to group m data requests according to the address modulo k, obtaining request lists corresponding to k RAMs. Each RAM's request list is then divided into n groups according to a predefined grouping strategy, with each group containing n requests.
[0067] Predefined grouping strategies include round-robin, random, and address-based distribution. Users can select the appropriate strategy based on the distribution characteristics of data requests.
[0068] Allows users to customize grouping strategies to meet specific needs and group data based on data access patterns or priorities.
[0069] In step S3, after obtaining n pending requests for all RAMs, two different valid addresses are selected to issue requests. If no valid address exists, the request corresponding to that RAM is processed. If all valid addresses are the same, only one request is issued. If no valid address exists for any group, the data request is processed successfully.
[0070] In step S4, during the loop processing, the grouping strategy and request merging strategy can be adjusted according to actual conditions to improve the processing efficiency of data requests. During the loop processing, the grouping strategy and request merging strategy can be adjusted according to actual conditions to improve the processing efficiency of data requests.
[0071] In step S5, the predefined grouping strategies include round-robin, random, and address-based distribution.
[0072] In step S6, module division: the entire circuit is divided into an address calculation module, a grouping module, a request processing module, etc., to improve the modularity and maintainability of the circuit.
[0073] Circuit optimization is performed based on circuit test results, such as adjusting circuit structure and optimizing circuit parameters, to improve circuit performance and reliability.
[0074] In step S7, the designed circuit is tested including functional testing;
[0075] Functional testing includes:
[0076] Verify the correctness of the address mapping table to ensure that each address is correctly mapped to the corresponding RAM. Verify the accuracy of the grouping module to ensure that each request is correctly assigned to the corresponding RAM and group. Verify the correctness of the request processing module to ensure that requests are issued in order of priority and that the valid bit is updated correctly. Verify the stability of the circuit to ensure that the circuit can remain stable under long-term operation.
[0077] Performance testing includes: evaluating the circuit's operating frequency to ensure it meets the system's performance requirements; evaluating the efficiency of data request processing to determine how many requests can be processed per cycle; and evaluating the circuit's power consumption to ensure it remains within acceptable limits.
[0078] In step S8, the method is applied to a multi-core processor, each core can independently issue a request, and the requests are merged and sent to the memory through the method.
[0079] When this method is applied to a GPU, multiple threads in the GPU can concurrently issue requests, and this method can be used to merge the requests and send them to the video memory.
[0080] When this method is applied to a memory controller, the memory controller can merge multiple requests and send them to the memory to improve memory access efficiency.
[0081] When this method is applied to a storage device, the storage device can merge multiple requests and send them to a hard disk or SSD, thereby improving the read and write efficiency of the storage device.
[0082] In step S9, a more efficient grouping strategy is studied. Through a grouping strategy based on machine learning, the future request distribution can be predicted based on the historical information of data requests, so as to select a more appropriate grouping strategy.
[0083] Research more efficient request merging strategies. Through request merging strategies based on compression algorithms, multiple requests can be compressed into one request, thereby reducing the number of requests and the amount of data transmitted.
[0084] In the present invention, by merging multiple data requests into a small number of requests, the number of interactions with the memory is effectively reduced, thereby significantly improving data access efficiency. At the same time, this method reduces the complexity of the circuit, making the circuit design simpler and easier to implement. The group address merging method enables the circuit to operate at a higher frequency, thereby improving the overall performance of the system. A programmable grouping strategy is adopted, and the appropriate grouping strategy can be selected based on the distribution characteristics of the data requests, thereby increasing the flexibility of the method. This method can be applied to a variety of parallel computing scenarios, including multi-core processors, GPUs, memory controllers, storage devices, etc., and has a wide range of applicability.
[0085] In the present invention, by reducing the number of interactions with the memory, circuit power consumption can be reduced, thereby improving the system's energy efficiency. This method can improve data access efficiency, reduce circuit complexity, increase circuit operating frequency, and so on, thereby improving the overall performance of the system. In addition, this method can reduce system costs and improve the user experience. This multi-request address merging method has multiple beneficial effects, effectively improving data access efficiency, reducing circuit complexity, increasing circuit operating frequency, increasing flexibility, improving adaptability, reducing power consumption, improving system performance, reducing costs, and improving the user experience.
[0086] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.
[0087] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.
Claims
1. A method for merging multiple request addresses, characterized in that: The method comprises the following steps: S1: Store data in k blocks of RAM, where data whose address modulo k result is 0 is stored in RAM0, data whose address modulo k result is 1 is stored in RAM1, and so on; S2: Group the original m data requests according to the result of address modulo k to obtain a request list corresponding to k RAMs; S3: For each set of requests for each RAM, perform the following operations: S3-1. Find the first valid address in the group (i.e. the valid bit corresponding to the address is 1); S3-2. Issue a request to the address; S3-3. Set all valid positions in the group that are the same as the address to 0; S3-4. If there is no valid address request for the group, the group is processed; S4: Repeat steps S2 and S3 until all address requests are sent; S5: Provides a variety of pre-defined grouping strategies, such as polling, random, and address distribution. Users can choose the appropriate strategy based on the distribution characteristics of data requests. Provides a variety of pre-defined grouping strategies. Users can choose the appropriate strategy based on the distribution characteristics of data requests. S6: Design a circuit according to the above algorithm. The circuit design should take into account the circuit complexity and operating frequency to ensure the performance of the system; S7: Test the designed circuit to verify its function and performance; optimize according to the test results, such as adjusting the grouping strategy and optimizing the circuit design to improve the efficiency and reliability of the system; S8: Apply this method to parallel computing scenarios, such as multi-core processors and GPUs, to improve data access efficiency and computing speed; S9: Continuously improve the grouping strategy and circuit design to adapt to new application scenarios and requirements, and then end the entire multi-request address merging process.
2. A method for merging multiple request addresses as claimed in claim 1, characterized in that: In step S1, the RAM selects k to be a power of 2; Create an address mapping table to record the data storage location corresponding to each address, so as to quickly locate the RAM where the data is located.
3. A method for merging multiple request addresses as claimed in claim 1, characterized in that: In step S2, each data request includes two parts: an address and a valid bit; the address indicates the storage location of the requested data, and the valid bit indicates whether the request is valid; The grouping strategy is to group the m data requests according to the result of address modulo k to obtain the request lists corresponding to k RAMs; the request list of each RAM is then divided into n groups according to the predefined grouping strategy, and each group contains n requests; The predefined grouping strategies include round-robin, random, and address-based distribution. Users can select the appropriate strategy based on the distribution characteristics of data requests. Allow users to customize grouping strategies to meet specific needs and group data based on data access patterns or priorities.
4. A method for merging multiple request addresses as claimed in claim 1, characterized in that: In step S3, after obtaining n requests to be issued of all RAMs, two different valid addresses are selected to issue requests; if there is no valid address, the request corresponding to the RAM is processed; if all valid addresses are the same, only one request is issued; if all groups have no valid address, the data request processing is completed.
5. A method for merging multiple request addresses as claimed in claim 1, characterized in that: In step S4, during the loop processing, the grouping strategy and the request merging strategy are adjusted according to the actual situation to improve the processing efficiency of data requests. During the loop processing, the grouping strategy and the request merging strategy are adjusted according to the actual situation to improve the processing efficiency of data requests.
6. A method for merging multiple request addresses as claimed in claim 1, characterized in that: In step S5, the predefined grouping strategies include round-robin, random, and address-based distribution.
7. A method for merging multiple request addresses as claimed in claim 1, characterized in that: In the step S6, module division: the entire circuit is divided into an address calculation module, a grouping module, and a request processing module to improve the modularity and maintainability of the circuit; Circuit optimization is performed based on circuit test results, such as adjusting circuit structure and optimizing circuit parameters to improve circuit performance and reliability.
8. A method for merging multiple request addresses as claimed in claim 1, characterized in that: In the step S7, the designed circuit is tested including functional testing; Functional testing includes: Verify the correctness of the address mapping table to ensure that each address can be correctly mapped to the corresponding RAM; verify the accuracy of the grouping module to ensure that each request can be correctly assigned to the corresponding RAM and group; verify the correctness of the request processing module to ensure that requests can be issued in priority order and that the valid bits can be correctly updated; verify the stability of the circuit to ensure that the circuit can remain stable under long-term operation; Performance testing includes: evaluating the operating frequency of the circuit to ensure that the circuit can meet the performance requirements of the system; evaluating the processing efficiency of data requests, how many requests can be processed per cycle; and evaluating the power consumption of the circuit to ensure that the power consumption of the circuit is within an acceptable range.
9. A method for merging multiple request addresses as claimed in claim 1, characterized in that: In step S8, the method is applied to a multi-core processor, each core independently issues a request, and the requests are merged and sent to the memory through the method; The method is applied to a GPU, where multiple threads in the GPU concurrently issue requests, and the requests are merged and sent to the video memory through the method; This method is applied to the memory controller, which merges multiple requests and sends them to the memory; This method is applied to a storage device, and the storage device merges multiple requests and sends them to a hard disk or an SSD.
10. A method for merging multiple request addresses as claimed in claim 1, characterized in that: In the step S9, a more efficient grouping strategy is studied, and a grouping strategy based on machine learning is used to predict future request distribution according to historical information of data requests, so as to select a more appropriate grouping strategy; Research more efficient request merging strategies, and compress multiple requests into one request through request merging strategies based on compression algorithms, thereby reducing the number of requests and the amount of data transmitted.