Data reading and writing method and device, equipment and medium

Abstract

The invention discloses a data reading and writing method, device and equipment and a medium, relates to the technical field of storage, and is applied to a preset arbitration selection controller which is connected with four processor cores and a double-rate synchronous dynamic random access memory. The double-rate synchronous dynamic random access memory establishes connection with four memory particles, and comprises the following steps: determining a current read-write mode according to a target task demand, and starting a corresponding number of processor cores based on the current read-write mode; obtaining an enable signal and an address selection signal output by the double-rate synchronous dynamic random access memory, and determining a target processor core for executing current read-write operation from the started processor cores based on a first level state of the enable signal and a second level state of the address selection signal; and executing a read-write operation on the target storage group in the target memory particle through the target processor core. According to the invention, the number of memory particles is increased, and reading and writing of a plurality of processor cores are supported.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a data reading and writing method, device, equipment and medium. Background Art

[0002] The current architecture of DDR (Double Data Rate) controllers mounting DDR particles (referred to as memory particles) is shown below: Figure 1 as shown in .

[0003] In actual applications, the DDR controller and DDR particles are connected to complete the functions of DDR reading, writing and storing data. Among them, the number of DDR particles is mainly determined by the data bit width of the DDR controller and the DDR particles. Since the total capacity of DDR particles is fixed, the DDR particles cannot be expanded when the data bit width of the DDR controller and the DDR particles is also fixed. Therefore, the number of DDR particles that the CPU (central processing unit) reads and writes through the DDR controller is also fixed, and the current solution only supports a single CPU core to read and write two DDR particles at the same time.

[0004] In summary, how to expand the number of memory particles on the double-speed synchronous dynamic random access memory and support multiple processor cores to read and write the double-speed synchronous dynamic random access memory is a problem that needs to be solved at present. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a data reading and writing method, device, equipment and medium, which can expand the number of memory particles on the double-speed synchronous dynamic random access memory and support multiple processor cores to read and write the double-speed synchronous dynamic random access memory. The specific scheme is as follows:

[0006] In a first aspect, the present application discloses a data reading and writing method, which is applied to a preset arbitration selection controller, wherein the arbitration selection controller is connected to four processor cores and a double-rate synchronous dynamic random access memory respectively, and the double-rate synchronous dynamic random access memory is connected to four memory particles through a signal line, including:

[0007] Determine the current read / write mode according to the target task requirements, and start the corresponding number of processor cores based on the current read / write mode;

[0008] Acquire an enable signal and an address selection signal output by the double rate synchronous dynamic random access memory, and determine a target processor core for executing the current read and write operation from the started processor cores based on a first level state of the enable signal and a second level state of the address selection signal;

[0009] The target processor core performs read and write operations on the target storage group in the target memory particle; wherein the target memory particle is a memory particle determined based on the first level state of the enable signal, and the target storage group is a storage group determined based on the second level state of the address selection signal.

[0010] Optionally, the read-write mode includes a first read-write mode and a second read-write mode;

[0011] Accordingly, the corresponding number of processor cores are started based on the current read / write mode, including:

[0012] If the current read-write mode is the first read-write mode, four processor cores are started;

[0013] If the current read-write mode is the second read-write mode, a processor core is started.

[0014] Optionally, the four processor cores include a first processor core, a second processor core, a third processor core, and a fourth processor core arranged in a preset order;

[0015] Correspondingly, if the current read / write mode is the first read / write mode, determining a target processor core for executing the current read / write operation from the started processor cores based on the first level state of the enable signal and the second level state of the address selection signal includes:

[0016] If the first level state of the enable signal is a high level state and the second level state of the address selection signal is a low level state, the first processor core after startup is used as a target processor core for executing the current read and write operation;

[0017] If the first level state of the enable signal is a high level state and the second level state of the address selection signal is a high level state, the started second processor core is used as a target processor core for executing the current read and write operation;

[0018] If the first level state of the enable signal is a low level state and the second level state of the address selection signal is a low level state, the started third processor core is used as a target processor core for executing the current read and write operation;

[0019] If the first level state of the enable signal is a low level state and the second level state of the address selection signal is a high level state, the activated fourth processor core is used as the target processor core for executing the current read and write operation.

[0020] Optionally, if the current read / write mode is the second read / write mode, determining a target processor core for executing the current read / write operation from the started processor cores based on the first level state of the enable signal and the second level state of the address selection signal includes:

[0021] After determining the first level state of the enable signal and the second level state of the address selection signal, the activated processor core is used as a target processor core for executing the current read and write operation.

[0022] Optionally, the address selection signal includes a first storage group address selection signal and a second storage group address selection signal, and the four memory particles include a first memory particle, a second memory particle, a third memory particle and a fourth memory particle; wherein the first storage group address selection signal is connected to the first memory particle and the second memory particle, the second storage group address selection signal is connected to the third memory particle and the fourth memory particle, the enable signal is connected to the first memory particle and the second memory particle, and is connected to the third memory particle and the fourth memory particle through an inverter.

[0023] Optionally, determining a target memory chip based on a first level state of an enable signal includes:

[0024] If the first level state of the enable signal is a high level state, determining the first memory cell and the second memory cell as target memory cells;

[0025] If the first level state of the enable signal is a low level state, the third memory chip and the fourth memory chip are determined as target memory chips.

[0026] Optionally, each memory cell includes a first storage group and a second storage group;

[0027] Accordingly, determining the target storage group based on the second level state of the address selection signal includes:

[0028] If the second level state of the address selection signal is a low level state, determining the first storage group in the target memory cell as the target storage group;

[0029] If the second level state of the address selection signal is a high level state, the second storage group in the target memory cell is determined as the target storage group.

[0030] In a second aspect, the present application discloses a data reading and writing device, which is applied to a preset arbitration selection controller, wherein the arbitration selection controller is connected to four processor cores and a double-rate synchronous dynamic random access memory respectively, and the double-rate synchronous dynamic random access memory is connected to four memory particles through a signal line, and the device includes:

[0031] A mode determination module is used to determine the current read / write mode according to the target task requirements and start a corresponding number of processor cores based on the current read / write mode;

[0032] a core determination module, used for acquiring an enable signal and an address selection signal output by the double rate synchronous dynamic random access memory, and determining a target processor core for executing a current read / write operation from the started processor cores based on a first level state of the enable signal and a second level state of the address selection signal;

[0033] A read / write module is used to perform read / write operations on a target storage group in a target memory particle through a target processor core; wherein the target memory particle is a memory particle determined based on a first level state of an enable signal, and the target storage group is a storage group determined based on a second level state of an address selection signal.

[0034] In a third aspect, the present application discloses an electronic device, comprising:

[0035] Memory, used to store computer programs;

[0036] The processor is used to execute a computer program to implement the steps of the aforementioned disclosed data reading and writing method.

[0037] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the aforementioned disclosed data reading and writing method are implemented.

[0038] It can be seen that the method of the present application is applied to a preset arbitration selection controller, the arbitration selection controller is connected to four processor cores and a double-speed synchronous dynamic random access memory respectively, and the double-speed synchronous dynamic random access memory is connected to four memory particles through signal lines. First, the current read and write mode is determined according to the target task requirements, and a corresponding number of processor cores are started based on the current read and write mode; the enable signal and the address selection signal output by the double-speed synchronous dynamic random access memory are obtained, and the target processor core for performing the current read and write operation is determined from the started processor cores based on the first level state of the enable signal and the second level state of the address selection signal; the read and write operations are performed on the target storage group in the target memory particle through the target processor core; wherein the target memory particle is a memory particle determined based on the first level state of the enable signal, and the target storage group is a storage group determined based on the second level state of the address selection signal.

[0039] Beneficial effects: The present application expands the number of memory particles and the number of processor cores, and further adds a preset arbitration selection controller, wherein the arbitration selection controller is connected to four processor cores and a double-rate synchronous dynamic random access memory respectively, and the double-rate synchronous dynamic random access memory is connected to four memory particles through a signal line, and the arbitration selection controller supports different read and write modes. Under this architecture, the read and write operation process is specifically to first determine the current read and write mode according to the target task requirements, so as to start the corresponding number of processor cores based on the current read and write mode. Further, the arbitration selection controller needs to obtain the enable signal and address selection signal output by the double-rate synchronous dynamic random access memory, so as to determine the target processor core for performing the current read and write operation from the processor core after startup based on the first level state of the enable signal and the second level state of the address selection signal, so as to use the target processor core to perform read and write operations on the target storage group in the target memory particle. Among them, the target memory particle is a memory particle determined based on the first level state of the enable signal, and the target storage group is a storage group determined based on the second level state of the address selection signal. It can be seen that the present application changes the current situation where the number of memory particles can only be determined according to the data bit width of the double-rate synchronous dynamic random access memory and the memory particles by changing the action mode of the enable signal and the address selection signal based on the situation that the data bit width of the double-rate synchronous dynamic random access memory and the memory particles is certain, thereby increasing the number of mounted memory particles and further expanding the size of the mounted memory storage capacity. The number of memory particles that the processor core reads and writes through the double-rate synchronous dynamic random access memory also expands accordingly, and supports four processor cores to read and write at the same time. Since the memory particles are expanded, the read and write capacity required by the quad-core can also be met. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0041] Figure 1 This is an architecture diagram of mounting DDR particles on a traditional DDR controller disclosed in this application;

[0042] Figure 2 A flow chart of a data reading and writing method disclosed in this application;

[0043] Figure 3 This is an architectural diagram of mounting DDR particles on an improved DDR controller disclosed in this application;

[0044] Figure 4 This is a diagram of the internal structure of a DDR particle disclosed in this application;

[0045] Figure 5 This is a schematic diagram of the structure of a data reading and writing device disclosed in this application;

[0046] Figure 6 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0048] The current architecture diagram of DDR particles (referred to as memory particles) mounted on the DDR controller is as follows: Figure 1 As shown in . The DDR controller and DDR particles are connected to complete the DDR reading, writing and storing data functions. Among them, the number of DDR particles is mainly determined by the data bit width of the DDR controller and the DDR particles. Since the total capacity of the DDR particles is fixed, the DDR particles cannot be expanded when the data bit width of the DDR controller and the DDR particles is also fixed. Therefore, the number of DDR particles that the CPU reads and writes through the DDR controller is also fixed, and the current solution only supports a single CPU core to read and write two DDR particles at the same time.

[0049] To this end, the embodiments of the present application disclose a data reading and writing method, device, equipment and medium, which can expand the number of memory particles on the double-speed synchronous dynamic random access memory and support multiple processor cores to read and write the double-speed synchronous dynamic random access memory.

[0050] See also Figure 2 and Figure 3 As shown, the embodiment of the present application discloses a data reading and writing method, which is applied to a preset arbitration selection controller, the arbitration selection controller is connected to four processor cores and a double-speed synchronous dynamic random access memory respectively, and the double-speed synchronous dynamic random access memory is connected to four memory particles through a signal line. The method includes:

[0051] Step S11: Determine the current read / write mode according to the target task requirements, and start a corresponding number of processor cores based on the current read / write mode.

[0052] This embodiment expands the number of memory particles and the number of processor cores, and further adds a preset arbitration selection controller, wherein, Figure 3 As shown in the architecture diagram, the arbitration selection controller is connected to the four processor cores: CPU1, CPU2, CPU3 and CPU4, and to the double data rate synchronous dynamic random access memory (i.e., DDR controller). The double data rate synchronous dynamic random access memory is connected to four memory particles: DDR particle 1, DDR particle 2, DDR particle 3 and DDR particle 4 through signal lines, and the arbitration selection controller supports different read and write modes.

[0053] Under this architecture, the specific read and write operation process is to first determine the current read and write mode according to the target task requirements, and then start the corresponding number of processor cores based on the current read and write mode.

[0054] In a specific implementation, the read-write mode includes a first read-write mode and a second read-write mode; accordingly, a corresponding number of processor cores are started based on the current read-write mode, including: if the current read-write mode is the first read-write mode, four processor cores are started; if the current read-write mode is the second read-write mode, one processor core is started. That is, the present application supports two modes of reading and writing DDR, and the mode is selected through an arbitration selector. The first read-write mode starts four processor cores, CPU1, CPU2, CPU3, and CPU4, at the same time, and the second read-write mode only starts one of the processor cores among CPU1, CPU2, CPU3, and CPU4. The started CPU core reads and writes DDR particle 1, DDR particle 2, DDR particle 3, and DDR particle 4, which is suitable for scenarios with large-capacity read and write requirements.

[0055] In the second read-write mode, since only one processor core needs to be started, the method for selecting the processor core can be further set:

[0056] In the first specific implementation, it can be started based on task load balancing, that is, the system can monitor the load of each processor core in real time and give priority to the processor core with the lowest load. For example, at a certain moment, CPU1 processes a large number of complex computing tasks and has a high load, while CPU3 is idle or underloaded. At this time, CPU3 can be started, which can effectively avoid further burdening the high-load CPU, improve the overall operating efficiency of the system, and allow system resources to be more reasonably allocated.

[0057] In the second specific implementation, it can be started according to the task type. If there are different types of tasks in the system, the appropriate CPU will be selected for startup according to the characteristics of the task. For example, for a graphics processing task, a specific CPU with stronger graphics processing acceleration capabilities may be started first; for a data encryption task, a CPU with higher encryption algorithm execution efficiency is selected. This can give full play to the advantages of different CPUs and improve the speed and quality of task processing.

[0058] In the third specific implementation, the system can be started according to the preset priority, and the priority of each CPU can be set in advance in the system settings. In the second read-write mode, the CPU with the highest priority is selected according to the priority order. For example, in some key business systems, a high priority is set for the CPU core responsible for core business processing to ensure that the CPU core is started first in the second read-write mode to ensure the efficient and stable operation of key businesses.

[0059] Step S12: obtaining an enable signal and an address selection signal output by the double rate synchronous dynamic random access memory, and determining a target processor core for executing the current read and write operation from the started processor cores based on a first level state of the enable signal and a second level state of the address selection signal.

[0060] In this embodiment, the arbitration selection controller needs to obtain the enable signal and address selection signal output by the double-rate synchronous dynamic random access memory to determine the target processor core for executing the current read and write operation from the started processor cores based on the first level state of the enable signal and the second level state of the address selection signal.

[0061] First, the related signals in the DDR controller are explained. ADDR[17:0] is the address signal, CS is the DDR enable signal, BA[1:0] is the BANK address selection signal, DQ[31:0] is the data signal, and BG[0] and BG[1] are the BANK GROUP (and storage group) address selection signals. Since the data bit width of the DDR particle is only 16 bits, and the data bit width of the DDR controller is 32 bits, currently only two DDR particles are mounted on the DDR controller, such as Figure 1 As shown in the figure, the lower 16-bit data DQ[15:0] of the DDR controller is connected to the DQ[15:0] of DDR particle 1, the higher 16-bit data DQ[31:16] of the DDR controller is connected to the DQ[15:0] of DDR particle 2, and ADDR[17:0] and BA[1:0] are connected to two DDR particles at the same time.

[0062] However, the number of memory particles is expanded in this application. In a specific implementation, the address selection signal includes a first storage group address selection signal and a second storage group address selection signal, and the four memory particles include a first memory particle, a second memory particle, a third memory particle, and a fourth memory particle; wherein the first storage group address selection signal is connected to the first memory particle and the second memory particle, the second storage group address selection signal is connected to the third memory particle and the fourth memory particle, the enable signal is connected to the first memory particle and the second memory particle, and is connected to the third memory particle and the fourth memory particle through an inverter.

[0063] That is, the address selection signal includes the first storage group address selection signal BG[0] and the second storage group address selection signal BG[1], and the four memory particles include the first memory particle (DDR particle 1), the second memory particle (DDR particle 2), the third memory particle (DDR particle 3) and the fourth memory particle (DDR particle 4). While keeping the DDR controller signal unchanged, the BG[0] signal is connected to DDR particles 1 and DDR particles 2 at the same time, and the BG[1] signal is connected to DDR particles 3 and DDR particles 4 at the same time. The enable signal CS output by the DDR controller is directly connected to DDR particles 1 and DDR particles 2, and then connected to DDR particles 3 and DDR particles 4 through an inverter. In this way, when the data bit width of the DDR controller is 32 bits, 4 DDR particles can be carried, which doubles the original storage capacity. It supports CPU1, CPU2, CPU3, and CPU4 to read and write DDR. The expanded DDR particles meet the DDR read and write capacity required by the quad-core.

[0064] Specifically, the four processor cores include a first processor core (CPU1), a second processor core (CPU2), a third processor core (CPU3) and a fourth processor core (CPU4) arranged in a preset order; accordingly, if the current read-write mode is the first read-write mode, a target processor core for executing the current read-write operation is determined from the processor cores after startup based on the first level state of the enable signal and the second level state of the address selection signal, including: if the first level state of the enable signal is a high level state and the second level state of the address selection signal is a low level state, the first processor core after startup is used as the target processor core for executing the current read-write operation The target processor core is used as the starting processor core; if the first level state of the enable signal is a high level state and the second level state of the address selection signal is a high level state, the second processor core after startup is used as the target processor core for executing the current read and write operation; if the first level state of the enable signal is a low level state and the second level state of the address selection signal is a low level state, the third processor core after startup is used as the target processor core for executing the current read and write operation; if the first level state of the enable signal is a low level state and the second level state of the address selection signal is a high level state, the fourth processor core after startup is used as the target processor core for executing the current read and write operation.

[0065] In the first specific implementation, if the first level state corresponding to the enable signal CS is a high level state, the first memory chip (DDR chip 1) and the second memory chip (DDR chip 2) are in the enabled state, and the acquired address selection signal is the BG[0] signal. If the second level state corresponding to the address selection signal BG[0] is a low level state, the first processor core (CPU1) after startup is used as the target processor core for executing the current read and write operation. In this case, the lower 16-bit data DQ[15:0] of the DDR controller is connected to the DQ[15:0] of the DDR chip 1, the upper 16-bit data DQ[31:16] of the DDR controller is connected to the DQ[15:0] of the DDR chip 2, and ADDR[17:0] and BA[1:0] are connected to the DDR chip 1 and the DDR chip 2.

[0066] In the second specific implementation, if the first level state corresponding to the enable signal CS is a high level state, the first memory particle (DDR particle 1) and the second memory particle (DDR particle 2) are in the enabled state, and the acquired address selection signal is the BG[0] signal. If the second level state corresponding to the address selection signal BG[0] is a high level state, the second processor core (CPU2) after startup is used as the target processor core for executing the current read and write operation. In this case, the lower 16-bit data DQ[15:0] of the DDR controller is connected to the DQ[15:0] of the DDR particle 1, the upper 16-bit data DQ[31:16] of the DDR controller is connected to the DQ[15:0] of the DDR particle 2, and ADDR[17:0] and BA[1:0] are connected to the DDR particle 1 and the DDR particle 2.

[0067] In the third specific implementation, if the first level state corresponding to the enable signal CS is a low level state, the third memory particle (DDR particle 3) and the fourth memory particle (DDR particle 4) are in the enabled state, and the acquired address selection signal is the BG[1] signal. If the second level state of the address selection signal BG[1] is a low level state, the third processor core (CPU3) after startup is used as the target processor core for executing the current read and write operation. In this case, the lower 16-bit data DQ[15:0] of the DDR controller is connected to the DQ[15:0] of the DDR particle 3, the higher 16-bit data DQ[31:16] of the DDR controller is connected to the DQ[15:0] of the DDR particle 4, and ADDR[17:0] and BA[1:0] are connected to the DDR particles 3 and 4.

[0068] In the fourth specific implementation, if the first level state corresponding to the enable signal CS is a low level state, the third memory chip (DDR chip 3) and the fourth memory chip (DDR chip 4) are in the enabled state, and the acquired address selection signal is the BG[1] signal. If the second level state of the address selection signal BG[1] is a high level state, the fourth processor core (CPU4) after startup is used as the target processor core for executing the current read and write operation. In this case, the lower 16-bit data DQ[15:0] of the DDR controller is connected to the DQ[15:0] of the DDR chip 3, the upper 16-bit data DQ[31:16] of the DDR controller is connected to the DQ[15:0] of the DDR chip 4, and ADDR[17:0] and BA[1:0] are connected to the DDR chip 3 and the DDR chip 4.

[0069] In addition, the above method also includes: if the current read-write mode is the second read-write mode, based on the first level state of the enable signal and the second level state of the address selection signal, determining the target processor core for performing the current read-write operation from the activated processor core, including: after determining the first level state of the enable signal and the second level state of the address selection signal, using the activated processor core as the target processor core for performing the current read-write operation. It can be understood that, since only one processor core is activated in the second read-write mode, after determining the first level state of the enable signal and the second level state of the address selection signal, the activated processor core is used as the target processor core for performing the current read-write operation. Specifically, when the enable signal CS is at a high level, DDR particles 1 and DDR particles 2 are enabled, the started CPU core reads and writes DDR particles 1 and DDR particles 2, the low 16-bit data DQ[15:0] of the DDR controller is connected to the DQ[15:0] of the DDR particle 1, the high 16-bit data DQ[31:16] of the DDR controller is connected to the DQ[15:0] of the DDR particle 2, ADDR[17:0] and BA[1:0] are connected to the DDR particles 1 and DDR particles 2; when the enable signal CS is at a low level, DDR particles 3 and DDR particles 4 are enabled, the started CPU core reads and writes DDR particles 3 and DDR particles 4, the low 16-bit data DQ[15:0] of the DDR controller is connected to the DQ[15:0] of the DDR particle 3, the high 16-bit data DQ[31:16] of the DDR controller is connected to the DQ[15:0] of the DDR particle 4, ADDR[17:0] and BA[1:0] are connected to the DDR particles 3 and DDR particles 4.

[0070] Step S13: performing read and write operations on a target storage group in a target memory cell through a target processor core; wherein the target memory cell is a memory cell determined based on a first level state of an enable signal, and the target storage group is a storage group determined based on a second level state of an address selection signal.

[0071] In this embodiment, the target processor core is used to perform read and write operations on the target storage group in the target memory particle. Among them, the target memory particle is a memory particle determined based on the first level state of the enable signal, and the target storage group is a storage group determined based on the second level state of the address selection signal. It can be seen that the present application changes the current situation that the number of memory particles can only be determined according to the data bit width of the double-speed synchronous dynamic random access memory and the memory particle by changing the action mode of the enable signal and the address selection signal based on the situation that the data bit width of the double-speed synchronous dynamic random access memory and the memory particle is certain, increases the number of mounted memory particles, and then expands the size of the mounted memory storage capacity. The number of memory particles that the processor core reads and writes through the double-speed synchronous dynamic random access memory is also expanded, and four processor cores are supported to read and write at the same time. Since the memory particles are expanded, the read and write capacity required by the quad-core can also be met.

[0072] In a specific implementation, determining the target memory particle based on the first level state of the enable signal includes: if the first level state of the enable signal is a high level state, determining the first memory particle and the second memory particle as the target memory particle; if the first level state of the enable signal is a low level state, determining the third memory particle and the fourth memory particle as the target memory particle. In this embodiment, if the first level state corresponding to the enable signal CS is a high level state, the first memory particle (DDR particle 1) and the second memory particle (DDR particle 2) are in the enabled state, so the first memory particle and the second memory particle are determined as the target memory particles; if the first level state corresponding to the enable signal CS is a low level state, the third memory particle (DDR particle 3) and the fourth memory particle (DDR particle 4) are in the enabled state, so the third memory particle and the fourth memory particle are determined as the target memory particles.

[0073] Furthermore, each memory cell includes a first storage group and a second storage group; accordingly, the target storage group is determined based on the second level state of the address selection signal, including: if the second level state of the address selection signal is a low level state, the first storage group in the target memory cell is determined as the target storage group; if the second level state of the address selection signal is a high level state, the second storage group in the target memory cell is determined as the target storage group.

[0074] That is, if Figure 4 As shown, each memory cell includes two BANK GROUPs, namely the first storage group (BANK GROUP1) and the second storage group (BANK GROUP2). Figure 1In the architecture shown, the BG[0] and BG[1] signals are used to select the BANK GROUP addresses of the two DDR particles. When BG[0] is 1'b1, BANKGROUP1 in DDR particle 1 is selected, and when BG[0] is 1'b0, BANK GROUP2 in DDR particle 1 is selected; when BG[1] is 1'b1, BANK GROUP1 in DDR particle 2 is selected, and when BG[1] is 1'b0, BANK GROUP2 in DDR particle 2 is selected. In addition, in order to correctly read and write the DDR particles, the values ​​of BG[0] and BG[1] are set to the same, so that a single CPU core can read and write BANK GROUP1 and BANK GROUP2 of the two DDR particles at the same time.

[0075] And in Figure 3 In the architecture shown, the present application stipulates that if the second level state corresponding to the address selection signal is a low level state, the first storage group (BANK GROUP1) in the target memory particle is determined as the target storage group; if the second level state corresponding to the address selection signal is a high level state, the second storage group (BANKGROUP2) in the target memory particle is determined as the target storage group. In summary, in the first read-write mode, CPU1 reads and writes BANK GROUP0 of DDR particle 1 and DDR particle 2, CPU2 reads and writes BANK GROUP1 of DDR particle 1 and DDR particle 2, CPU3 reads and writes BANK GROUP0 of DDR particle 3 and DDR particle 4, and CPU3 reads and writes BANK GROUP1 of DDR particle 3 and DDR particle 4, and the CPU that reads and writes DDR at a certain moment is selected through the arbitration selector.

[0076] In this way, the present application is based on the situation that the data bit width of the DDR controller and DDR particles is certain. Under the condition of keeping the DDR controller unchanged, by changing the working mode of the BG signal and the CS signal, the current situation that the number of DDR particles can only be determined according to the data bit width of the DDR controller and the DDR particles is changed, the number of mounted DDR particles is increased, and then the size of the DDR storage capacity mounted by the DDR controller is expanded. The number of DDR particles that the CPU reads and writes through the DDR controller is also expanded accordingly, and four CPU cores are supported to read and write DDR at the same time. Since the DDR particles are expanded, the DDR read and write capacity required by the quad-core can also be met. This design scheme can be applied to scenarios with different data bit widths and supports different modes of starting quad-core or single-core.

[0077] It can be seen that the present application has expanded the number of memory particles and the number of processor cores, and further added a preset arbitration selection controller, wherein the arbitration selection controller is connected to the four processor cores and the double-speed synchronous dynamic random access memory respectively, and the double-speed synchronous dynamic random access memory is connected to the four memory particles through a signal line, and the arbitration selection controller supports different read and write modes. Under this architecture, the read and write operation process is specifically to first determine the current read and write mode according to the target task requirements, so as to start the corresponding number of processor cores based on the current read and write mode. Further, the arbitration selection controller needs to obtain the enable signal and address selection signal output by the double-speed synchronous dynamic random access memory, so as to determine the target processor core for performing the current read and write operation from the processor core after startup based on the first level state of the enable signal and the second level state of the address selection signal, so as to use the target processor core to perform read and write operations on the target storage group in the target memory particle. Among them, the target memory particle is a memory particle determined based on the first level state of the enable signal, and the target storage group is a storage group determined based on the second level state of the address selection signal. It can be seen that the present application changes the current situation where the number of memory particles can only be determined according to the data bit width of the double-rate synchronous dynamic random access memory and the memory particles by changing the action mode of the enable signal and the address selection signal based on the situation that the data bit width of the double-rate synchronous dynamic random access memory and the memory particles is certain, thereby increasing the number of mounted memory particles and further expanding the size of the mounted memory storage capacity. The number of memory particles that the processor core reads and writes through the double-rate synchronous dynamic random access memory also expands accordingly, and supports four processor cores to read and write at the same time. Since the memory particles are expanded, the read and write capacity required by the quad-core can also be met.

[0078] See also Figure 5 As shown, the embodiment of the present application discloses a data reading and writing device, which is applied to a preset arbitration selection controller, the arbitration selection controller is connected to four processor cores and a double-speed synchronous dynamic random access memory respectively, and the double-speed synchronous dynamic random access memory is connected to four memory particles through a signal line. The device includes:

[0079] A mode determination module 11 is used to determine the current read / write mode according to the target task requirements, and start a corresponding number of processor cores based on the current read / write mode;

[0080] The core determination module 12 is used to obtain the enable signal and the address selection signal output by the double rate synchronous dynamic random access memory, and determine the target processor core for executing the current read and write operation from the started processor cores based on the first level state of the enable signal and the second level state of the address selection signal;

[0081] The read / write module 13 is used to perform read / write operations on the target storage group in the target memory particle through the target processor core; wherein the target memory particle is a memory particle determined based on the first level state of the enable signal, and the target storage group is a storage group determined based on the second level state of the address selection signal.

[0082] It can be seen that the present application has expanded the number of memory particles and the number of processor cores, and further added a preset arbitration selection controller, wherein the arbitration selection controller is connected to the four processor cores and the double-speed synchronous dynamic random access memory respectively, and the double-speed synchronous dynamic random access memory is connected to the four memory particles through a signal line, and the arbitration selection controller supports different read and write modes. Under this architecture, the read and write operation process is specifically to first determine the current read and write mode according to the target task requirements, so as to start the corresponding number of processor cores based on the current read and write mode. Further, the arbitration selection controller needs to obtain the enable signal and address selection signal output by the double-speed synchronous dynamic random access memory, so as to determine the target processor core for performing the current read and write operation from the processor core after startup based on the first level state of the enable signal and the second level state of the address selection signal, so as to use the target processor core to perform read and write operations on the target storage group in the target memory particle. Among them, the target memory particle is a memory particle determined based on the first level state of the enable signal, and the target storage group is a storage group determined based on the second level state of the address selection signal. It can be seen that the present application changes the current situation where the number of memory particles can only be determined according to the data bit width of the double-rate synchronous dynamic random access memory and the memory particles by changing the action mode of the enable signal and the address selection signal based on the situation that the data bit width of the double-rate synchronous dynamic random access memory and the memory particles is certain, thereby increasing the number of mounted memory particles and further expanding the size of the mounted memory storage capacity. The number of memory particles that the processor core reads and writes through the double-rate synchronous dynamic random access memory also expands accordingly, and supports four processor cores to read and write at the same time. Since the memory particles are expanded, the read and write capacity required by the quad-core can also be met.

[0083] Since the embodiments of the device part correspond to the embodiments of the method part, the embodiments of the device part refer to the description of the embodiments of the method part, which will not be described here. And, it has the same beneficial effects as the above-mentioned data reading and writing method.

[0084] Figure 6A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the data reading and writing method performed by the electronic device disclosed in any of the aforementioned embodiments.

[0085] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0086] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0087] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system 221, a computer program 222 and data 223, etc. The storage method can be temporary storage or permanent storage.

[0088] Among them, the operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, so as to realize the operation and processing of the massive data 223 in the memory 22 by the processor 21, which can be Windows, Unix, Linux, etc. In addition to including a computer program that can be used to complete the data reading and writing method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks. In addition to data transmitted from an external device received by the electronic device, the data 223 can also include data collected by its own input and output interface 25, etc.

[0089] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium, in which a computer program is stored. When the computer program is loaded and executed by a processor, the steps of the data reading and writing method disclosed in any of the aforementioned embodiments are implemented.

[0090] Furthermore, an embodiment of the present application also discloses a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the data reading and writing method disclosed in any of the aforementioned embodiments.

[0091] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0092] Those skilled in the art may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0093] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.

[0094] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0095] The above is a detailed introduction to a data reading and writing method, device, equipment and storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A data reading and writing method, characterized in that: The method is applied to a preset arbitration selection controller, wherein the arbitration selection controller is connected to four processor cores and a double-speed synchronous dynamic random access memory respectively, and the double-speed synchronous dynamic random access memory is connected to four memory particles through a signal line. The method includes: Determine a current read / write mode according to target task requirements, and start a corresponding number of processor cores based on the current read / write mode; Acquire an enable signal and an address selection signal output by the double rate synchronous dynamic random access memory, and determine a target processor core for executing a current read / write operation from the started processor cores based on a first level state of the enable signal and a second level state of the address selection signal; The target processor core performs read and write operations on the target storage group in the target memory particle; wherein the target memory particle is a memory particle determined based on the first level state of the enable signal, and the target storage group is a storage group determined based on the second level state of the address selection signal.

2. The data reading and writing method according to claim 1, characterized in that: The read-write mode includes a first read-write mode and a second read-write mode; Correspondingly, starting a corresponding number of processor cores based on the current read / write mode includes: If the current read-write mode is the first read-write mode, starting four processor cores; If the current read-write mode is the second read-write mode, a processor core is started.

3. The data reading and writing method according to claim 2, characterized in that: The four processor cores include a first processor core, a second processor core, a third processor core and a fourth processor core arranged in a preset order; Correspondingly, if the current read / write mode is the first read / write mode, determining a target processor core for executing the current read / write operation from the started processor cores based on the first level state of the enable signal and the second level state of the address selection signal includes: If the first level state of the enable signal is a high level state and the second level state of the address selection signal is a low level state, the first processor core after startup is used as a target processor core for executing the current read and write operation; If the first level state of the enable signal is a high level state and the second level state of the address selection signal is a high level state, the second processor core after startup is used as a target processor core for executing the current read and write operation; If the first level state of the enable signal is a low level state and the second level state of the address selection signal is a low level state, the started third processor core is used as a target processor core for executing the current read and write operation; If the first level state of the enable signal is a low level state and the second level state of the address selection signal is a high level state, the activated fourth processor core is used as a target processor core for executing the current read and write operation.

4. The data reading and writing method according to claim 2, characterized in that: If the current read / write mode is the second read / write mode, determining a target processor core for executing the current read / write operation from the started processor cores based on the first level state of the enable signal and the second level state of the address selection signal includes: After determining the first level state of the enable signal and the second level state of the address selection signal, the started processor core is used as a target processor core for executing the current read and write operation.

5. The data reading and writing method according to claim 1, characterized in that: The address selection signal includes a first storage group address selection signal and a second storage group address selection signal, and the four memory particles include a first memory particle, a second memory particle, a third memory particle and a fourth memory particle; wherein, the first storage group address selection signal is connected to the first memory particle and the second memory particle, the second storage group address selection signal is connected to the third memory particle and the fourth memory particle, the enable signal is connected to the first memory particle and the second memory particle, and is connected to the third memory particle and the fourth memory particle through an inverter.

6. The data reading and writing method according to claim 5, characterized in that: Determining the target memory chip based on the first level state of the enable signal includes: If the first level state of the enable signal is a high level state, determining the first memory cell and the second memory cell as the target memory cells; If the first level state of the enable signal is a low level state, the third memory cell and the fourth memory cell are determined as the target memory cells.

7. The data reading and writing method according to claim 5, characterized in that: Each memory cell includes a first storage group and a second storage group; Correspondingly, determining the target storage group based on the second level state of the address selection signal includes: If the second level state of the address selection signal is a low level state, determining the first storage group in the target memory cell as the target storage group; If the second level state of the address selection signal is a high level state, the second storage group in the target memory cell is determined as the target storage group.

8. A data reading and writing device, characterized in that: The device is applied to a preset arbitration selection controller, wherein the arbitration selection controller is connected to four processor cores and a double-speed synchronous dynamic random access memory respectively, and the double-speed synchronous dynamic random access memory is connected to four memory particles through a signal line. The device includes: A mode determination module, used to determine a current read / write mode according to target task requirements, and start a corresponding number of processor cores based on the current read / write mode; a core determination module, configured to obtain an enable signal and an address selection signal output by the double rate synchronous dynamic random access memory, and determine a target processor core for executing a current read / write operation from the started processor cores based on a first level state of the enable signal and a second level state of the address selection signal; A read / write module is used to perform read / write operations on a target storage group in a target memory particle through the target processor core; wherein the target memory particle is a memory particle determined based on a first level state of the enable signal, and the target storage group is a storage group determined based on a second level state of the address selection signal.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the data reading and writing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein, when the computer program is executed by a processor, the steps of the data reading and writing method according to any one of claims 1 to 7 are implemented.

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