A single-wire serial communication chip and a single-wire serial communication method

Abstract

This invention provides a single-wire serial communication chip and a single-wire serial communication method. The single-wire serial communication chip includes a half-duplex interface module, a parallel-to-serial conversion module, a register, a counter, and a state machine. The state machine analyzes the current data transmission requirements based on the data storage state of the register and the external input signals received by the half-duplex interface module, and selects the corresponding operating mode to instruct other modules to output the data in the register, such as the initial chip data, to an external microcontroller. The connection between the half-duplex interface module and the external microcontroller is a single-wire connection, enabling communication between the single-wire serial communication chip and the external microcontroller. When implementing the single-wire serial communication chip of this embodiment on a PCB board, compared to chips based on I2C and SPI protocols, it occupies a smaller area and significantly reduces the number of pins.

Description

Technical Field

[0001] This invention relates to the field of communication control technology, and in particular to a single-wire serial communication chip and a single-wire serial communication method. Background Technology

[0002] With the development of integrated circuit technology, all kinds of electronic products have permeated every aspect of people's lives. Regardless of their function, these emerging electronic products almost all require a microcontroller or single-chip microcomputer as their core to call upon peripheral circuits. Therefore, choosing the appropriate communication method between different circuits and microcontrollers is particularly important.

[0003] Currently, commonly used communication methods include the I2C (Inter-Integrated Circuit) protocol and the SPI (Serial Peripheral Interface) protocol. The I2C protocol uses two lines: SDA (Serial Data Line) and SCL (Serial Clock Line). The SDA line handles data transmission, while the SCL line provides the clock signal to ensure synchronization between devices. Both lines are bidirectional, allowing data to flow in both directions. The SPI protocol uses four lines: MOSI (Master Input Slave Output), MOSO (Master Output Slave Input), SCLK (Serial Clock), and CS (Chip Select). The MOSI line transmits data from the master device to the slave device, while the MOSI line transmits data in the opposite direction. The master device controls the SCLK line to regulate communication, and uses the CS line to select the slave device to communicate with.

[0004] However, both of these communication methods require at least two or more lines to communicate, which results in a larger footprint and more pins on the PCB. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a single-wire serial communication chip and a single-wire serial communication method, which solves the problems of existing communication methods, such as the I2C protocol and the SPI protocol, having a large area occupied and a large number of pins when implemented on a PCB board.

[0006] According to an embodiment of the present invention, a first aspect provides a single-wire serial communication chip, including a half-duplex interface module, a parallel-to-serial conversion module, a register, a counter, and a state machine;

[0007] The state machine is connected to the register, the counter, and the half-duplex interface module. The register is also connected to the parallel-to-serial converter module. The parallel-to-serial converter module is also connected to the counter and the half-duplex interface module. The half-duplex interface module is connected to an external microcontroller.

[0008] The register is used to store the initial chip data in a parallel data format;

[0009] The counter counts based on the clock signal of the half-duplex interface module to generate a count value;

[0010] The parallel-to-serial module is used to convert the initial chip data into a serial data format to obtain the chip data to be used, and output the chip data to the half-duplex interface module according to the count value generated by the counter.

[0011] The half-duplex interface module includes a signal output branch and a signal input branch; both the signal input branch and the signal output branch are connected to an external microcontroller to receive external input signals from the external microcontroller and send the data of the chip to be used; the signal output branch is connected to the state machine and the parallel-to-serial conversion module to receive the count value generated by the parallel-to-serial conversion module, and the state machine detects the clock signal through the signal output branch;

[0012] The state machine is used to instruct the half-duplex interface module, the parallel-to-serial converter, and the counter to output the chip data to the external microcontroller based on the data storage state of the register and the external input signal received by the half-duplex interface module.

[0013] Optionally, the state machine, based on the data storage state of the register and the external input signal received by the half-duplex interface module, instructs the half-duplex interface module, the parallel-to-serial converter, and the counter to output the chip data to be used to an external microcontroller, including:

[0014] If the half-duplex interface module does not receive the external input signal, and the data storage status of the register indicates that there is target data to be updated to the external microcontroller, then the state machine enters the data update mode. The data update mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the target data into standby chip data and output it to the external microcontroller according to the first working sequence, thereby completing the data update.

[0015] If the half-duplex interface module receives the external input signal, and the external input signal is of a preset type, the state machine enters the forced read mode. The forced read mode is used to instruct the half-duplex interface module, the parallel-to-serial module, and the counter to convert the real-time data stored in the register into standby chip data and output it to the external microcontroller according to the second working sequence, thereby completing the forced data read.

[0016] Optionally, the state machine enters a data update mode, instructing the half-duplex interface module, the parallel-to-serial conversion module, and the counter to convert the target data into ready-to-use chip data according to a first working sequence and output it to an external microcontroller, including:

[0017] S11. The half-duplex interface module receives an update valid signal sent by the state machine. The update valid signal is generated when the half-duplex interface module has not received the external input signal and the data storage state of the register indicates that there is target data to be updated to the external microcontroller.

[0018] S12. Pull the port line high according to the updated valid signal and continue for the first time;

[0019] S13. Receive feedback level signal sent by external microcontroller, the feedback level signal including a first level signal generated by the external microcontroller pulling the port line low for a second time, and a second level signal generated by pulling the port line high for a third time after the second time.

[0020] S14. A clock signal is generated based on the second level signal, so that when the state machine detects the clock signal, it sends the clock signal to the counter, the counter starts counting, and sends the count value to the parallel-to-serial module; wherein, the parallel-to-serial module modifies the most significant bit of the target data according to the count value, so as to convert the target data into standby chip data for output by the half-duplex interface module;

[0021] S15. Output the data of the chip to be used for N system clock cycles. During the N system clock cycles, the external microcontroller samples the most significant bit and the least significant bit of the data of the chip to be used.

[0022] S17. Repeat S13 to S16 until, in S14, the clock signal detected by the state machine is greater than the fourth time, and reset the half-duplex interface module, the parallel-to-serial module, and the counter; wherein, if S13 to S16 are repeated N times, the external microcontroller obtains the most significant bit of N pending chip data and the least significant bit of N pending chip data, and completes the data update.

[0023] Optionally, the state machine enters a forced read mode, instructing the half-duplex interface module, the parallel-to-serial conversion module, and the counter to convert the real-time data stored in the register into ready-to-use chip data according to the second working sequence and output it to an external microcontroller, including:

[0024] S21. The half-duplex interface module blocks the update valid signal according to the forced read instruction, and at the same time pulls the port line high and continues for a first time according to the external input signal of the preset type; the forced read instruction is generated when the half-duplex interface module receives the external input signal and the external input signal is of the preset type.

[0025] S22. Receive feedback level signal sent by an external microcontroller. The feedback level signal includes a first level signal generated by the external microcontroller pulling the port line low for a second time, and a second level signal generated by pulling the port line high for a third time after the second time.

[0026] S23. A clock signal is generated based on the second level signal, so that when the state machine detects the clock signal, it sends the clock signal to the counter, the counter starts counting, and sends the count value to the parallel-to-serial module; wherein, the parallel-to-serial module modifies the most significant bit of the real-time data according to the count value, so as to convert the real-time data into standby chip data for output by the half-duplex interface module;

[0027] S24. Output the data of the chip to be used for N system clock cycles. During the N system clock cycles, the external microcontroller samples the most significant bit and the least significant bit of the data of the chip to be used.

[0028] S25. Repeat S22 to S225 until, in S23, the clock signal detected by the state machine is greater than the fourth time, and reset the half-duplex interface module, the parallel-to-serial module and the counter; wherein, if S13 to S16 are repeated N times, the external microcontroller obtains the most significant bit of N pending chip data and the least significant bit of N pending chip data, and completes the forced data reading.

[0029] Optionally, the signal output branch includes an electrostatic protection circuit, and the signal input branch includes a shaping and filtering circuit.

[0030] Optionally, the signal output branch includes a first resistor, a second resistor, a third resistor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor;

[0031] In this circuit, the first PMOS transistor and the first NMOS transistor form an inverter. The input of the inverter is connected to the output of the parallel-to-serial module, and the output of the inverter is connected to the positive terminal of the first resistor. The negative terminal of the first resistor is connected to the drain terminals of the second PMOS transistor and the second NMOS transistor. The gate of the second PMOS transistor is connected to the digital power supply through the second resistor. The source terminal and the substrate of the second PMOS transistor are also connected to the digital power supply. The gate of the second NMOS transistor is grounded through the third resistor, and the source terminal and the substrate of the second NMOS transistor are also grounded.

[0032] Optionally, the signal input branch includes a fourth resistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor constitute a Schmitt trigger. The input of the Schmitt trigger is connected to the negative terminal of the fourth resistor, the output of the Schmitt trigger is connected to the state machine, and the positive terminal of the fourth resistor is connected to an external microcontroller.

[0033] Optionally, when storing the initial chip data in a parallel data format, the register adds a header code and a tail code for the microcontroller to recognize.

[0034] A second aspect provides a single-wire serial communication method applied to a host and a slave device that have established a communication connection, wherein both the host and the slave device use the single-wire serial communication chip as described in any of the preceding claims, and the single-wire serial communication method includes:

[0035] The host detects the data storage status of the registers and the external input signals received by the half-duplex interface module, and instructs the half-duplex interface module, the parallel-to-serial converter, and the counter to output the chip data to the external microcontroller based on the data storage status of the registers and the external input signals received by the half-duplex interface module.

[0036] The parallel-to-serial module converts the initial chip data in the register into chip data to be used. The initial chip data is in parallel data format, and the chip data to be used is in serial data format.

[0037] Optionally, based on the data storage status of the registers and the external input signals received by the half-duplex interface module, the half-duplex interface module, the parallel-to-serial converter, and the counter are instructed to output the chip data to be used to the external microcontroller, including:

[0038] If the half-duplex interface module does not receive the external input signal, and the data storage status of the register indicates that there is target data to be updated to the external microcontroller, then the state machine enters the data update mode. The data update mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the target data into standby chip data and output it to the external microcontroller according to the first working sequence, thereby completing the data update.

[0039] If the half-duplex interface module receives the external input signal, and the external input signal is of a preset type, the state machine enters the forced read mode. The forced read mode is used to instruct the half-duplex interface module, the parallel-to-serial module, and the counter to convert the real-time data stored in the register into standby chip data and output it to the external microcontroller according to the second working sequence, thereby completing the forced data read.

[0040] Compared to existing technologies, this invention has the following advantages: The single-wire serial communication chip in this embodiment is used to establish a communication connection with an external microcontroller. The external microcontroller is the core for calling peripheral circuits; therefore, the external microcontroller needs to program the data for calling peripheral circuits. This data is stored in the registers of the single-wire serial communication chip, such as the initial chip data in this embodiment. The single-wire serial communication chip in this embodiment includes a half-duplex interface module, a parallel-to-serial conversion module, registers, a counter, and a state machine. The detailed working process is as follows: The state machine analyzes the current data transmission requirements based on the data storage status of the registers and the external input signals received by the half-duplex interface module, and then selects the corresponding working mode to instruct other modules to output the data in the registers, such as the initial chip data, to the external microcontroller. However, regardless of the data transmission requirements or the working mode used, the parallel-to-serial conversion module will convert the data in the registers into serial data format, such as converting the initial chip data into the ready-to-use chip data. Then, based on the count value generated by the counter, the ready-to-use chip data is output to the half-duplex interface module. Since the data to be used by the chip is serial data, a single-wire connection between the half-duplex interface module and the external microcontroller is sufficient to achieve communication between the single-wire serial communication chip and the external microcontroller. The half-duplex interface module outputs the aforementioned data to be used by the chip to the external microcontroller. When implementing the single-wire serial communication chip of this embodiment on the PCB board, compared with chips based on I2C and SPI protocols, it occupies a smaller area and can significantly reduce the number of pins. Attached Figure Description

[0041] Figure 1 This is a structural diagram of a single-wire serial communication chip according to an embodiment of the present invention;

[0042] Figure 2 This is a timing diagram of the data update mode in an embodiment of the present invention;

[0043] Figure 3 This is a timing diagram of the forced read mode in an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of the output format of the chip data to be used in an embodiment of the present invention;

[0045] Figure 5 for Figure 1 A schematic diagram of the circuit structure of the half-duplex interface module. Detailed Implementation

[0046] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0047] like Figure 1 As shown, this embodiment of the invention proposes a single-wire serial communication chip, including a half-duplex interface module 10, a parallel-to-serial conversion module 20, a register 30, a counter 40, and a state machine 50.

[0048] The connection relationships of the above structures are as follows:

[0049] State machine 50 is connected to register 30, counter 40, and half-duplex interface module 10. Register 30 is also connected to parallel-to-serial converter 20, which is further connected to counter 40 and half-duplex interface module 10. Half-duplex interface module 10 is connected to an external microcontroller (MCU). Therefore, according to... Figure 1 The half-duplex interface module 10 includes two connection ports, namely the signal output branch Data_OUT and the signal input branch Data_IN.

[0050] The functions of the above structures are as follows:

[0051] The register is used to store the initial chip data in a parallel data format;

[0052] The counter counts based on the clock signal of the half-duplex interface module to generate a count value;

[0053] The parallel-to-serial module is used to convert the initial chip data into a serial data format to obtain the chip data to be used, and output the chip data to the half-duplex interface module according to the count value generated by the counter.

[0054] The half-duplex interface module includes a signal output branch and a signal input branch; both the signal input branch and the signal output branch are connected to an external microcontroller to receive external input signals from the external microcontroller and send the data of the chip to be used; the signal output branch is connected to the state machine and the parallel-to-serial conversion module to receive the count value generated by the parallel-to-serial conversion module, and the state machine detects the clock signal through the signal output branch;

[0055] The state machine is used to instruct the half-duplex interface module, the parallel-to-serial converter, and the counter to output the chip data to the external microcontroller based on the data storage state of the register and the external input signal received by the half-duplex interface module.

[0056] It should be noted that the initial chip data is the data required by the external microcontroller. The single-wire serial communication chip will update the initial chip data to adapt to changes in the functionality of the external microcontroller.

[0057] The single-wire serial communication chip in this embodiment is used to establish a communication connection with an external microcontroller. The external microcontroller is the core for calling peripheral circuits; therefore, it needs to program the data for calling peripheral circuits. This data is stored in the registers of the single-wire serial communication chip, such as the initial chip data in this embodiment. The single-wire serial communication chip in this embodiment includes a half-duplex interface module, a parallel-to-serial conversion module, registers, a counter, and a state machine. The detailed working process is as follows: The state machine analyzes the current data transmission requirements based on the data storage status of the registers and the external input signals received by the half-duplex interface module, thereby selecting the corresponding working mode and instructing other modules to output the data in the registers, such as the initial chip data, to the external microcontroller. However, regardless of the data transmission requirements or the working mode used, the parallel-to-serial conversion module will convert the data in the registers into serial data format, such as converting the initial chip data into ready-to-use chip data. Then, based on the count value generated by the counter, the ready-to-use chip data is output to the half-duplex interface module. Since the data to be used by the chip is serial data, a single-wire connection between the half-duplex interface module and the external microcontroller is sufficient to achieve communication between the single-wire serial communication chip and the external microcontroller. The half-duplex interface module outputs the aforementioned data to be used by the chip to the external microcontroller. When implementing the single-wire serial communication chip of this embodiment on the PCB board, compared with chips based on I2C and SPI protocols, it occupies a smaller area and can significantly reduce the number of pins.

[0058] Another embodiment of the present invention illustrates two operating modes of the state machine based on the data storage state of the register and the external input signal received by the half-duplex interface module: a data update mode and a forced read mode, including:

[0059] If the half-duplex interface module does not receive the external input signal, and the data storage status of the register indicates that there is target data to be updated to the external microcontroller, then the state machine enters the data update mode. The data update mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the target data into standby chip data and output it to the external microcontroller according to the first working sequence, thereby completing the data update.

[0060] If the half-duplex interface module receives the external input signal, and the external input signal is of a preset type, the state machine enters the forced read mode. The forced read mode is used to instruct the half-duplex interface module, the parallel-to-serial module, and the counter to convert the real-time data stored in the register into standby chip data and output it to the external microcontroller according to the second working sequence, thereby completing the forced data read.

[0061] In one embodiment, the external input signal is of a preset type, meaning that the external input signal is a level signal that is pulled high for at least two system clock cycles after the external microcontroller receives the pull-high signal sent by the dual ports.

[0062] For the above data update mode, at the software instruction level, the state machine determines whether the initial chip data in the register has been updated to the target data to be updated to the external microcontroller; at the hardware level, it determines whether the external microcontroller has established communication with the single-wire serial communication chip, thereby aligning the data sampling period of the external microcontroller with the period of the half-duplex interface module outputting the chip data to be used, and arranging the working timing of other modules.

[0063] Based on this, for example, the aforementioned state machine enters a data update mode, instructing the half-duplex interface module, parallel-to-serial module, and counter to convert the target data into ready-to-use chip data according to a first working sequence and output it to an external microcontroller, including:

[0064] S11. The half-duplex interface module receives an update valid signal sent by the state machine. The update valid signal is generated when the half-duplex interface module has not received the external input signal and the data storage state of the register indicates that there is target data to be updated to the external microcontroller.

[0065] S12. Pull the port line high according to the updated valid signal and continue for a first time tS;

[0066] S13. Receive feedback level signal sent by external microcontroller. The feedback level signal includes a first level signal generated by the external microcontroller pulling the port line low for a second time tL, and a second level signal generated by pulling the port line high for a third time tH after the second time tL.

[0067] S14. A clock signal is generated based on the second level signal, so that when the state machine detects the clock signal, it sends the clock signal to the counter, the counter starts counting, and sends the count value to the parallel-to-serial module; wherein, the parallel-to-serial module modifies the most significant bit of the target data according to the count value, so as to convert the target data into standby chip data for output by the half-duplex interface module;

[0068] S15. Output the data of the chip to be used for N system clock cycles. During the N system clock cycles, the external microcontroller samples the most significant bit and the least significant bit of the data of the chip to be used.

[0069] S17. Repeat S13 to S16 until, in S14, the clock signal detected by the state machine is greater than the fourth time tW, and reset the half-duplex interface module, the parallel-to-serial module, and the counter; wherein, if S13 to S16 are repeated N times, the external microcontroller obtains the most significant bit of N pending chip data and the least significant bit of N pending chip data, and completes the data update.

[0070] like Figure 2 As shown, this embodiment of the invention also provides a timing diagram under the data update mode. Figure 2 In the diagram, the blue line represents the microcontroller driver, and the dashed line represents the single-wire serial communication chip driver.

[0071] In the aforementioned forced read mode, the state machine, at the software instruction level, causes the half-duplex interface module to mask the update validity signal. Even if the half-duplex interface module outputs an update validity signal, the external microcontroller does not process this signal. The state machine only determines, at the hardware level, whether the external microcontroller has established communication with the single-wire serial communication chip, allowing the external microcontroller to directly read the real-time data from the register.

[0072] It should be noted that the forced read mode is unaffected by whether the initial chip data in the register has been updated to the target data to be updated to the external microcontroller, or is being updated. If the initial chip data in the register has been updated to the target data to be updated to the external microcontroller, the external microcontroller directly reads the real-time data in the register as the target data; if the initial chip data in the register is being updated, but has not been fully updated to the target data to be updated to the external microcontroller, the external microcontroller directly reads the real-time data in the register as the initial chip data.

[0073] Based on this, for example, the aforementioned state machine enters a forced read mode, instructing the half-duplex interface module, the parallel-to-serial conversion module, and the counter to convert the real-time data stored in the register into ready-to-use chip data according to the second working sequence and output it to an external microcontroller, including:

[0074] S21. The half-duplex interface module blocks the update valid signal according to the forced read instruction, and at the same time pulls the port line high and continues for a first time tS according to the external input signal of the preset type; the forced read instruction is generated when the half-duplex interface module receives the external input signal and the external input signal is of the preset type.

[0075] S22. Receive feedback level signal sent by external microcontroller. The feedback level signal includes a first level signal generated by the external microcontroller pulling the port line low for a second time tL, and a second level signal generated by pulling the port line high for a third time tH after the second time tL.

[0076] S23. A clock signal is generated based on the second level signal, so that when the state machine detects the clock signal, it sends the clock signal to the counter, the counter starts counting, and sends the count value to the parallel-to-serial module; wherein, the parallel-to-serial module modifies the most significant bit of the real-time data according to the count value, so as to convert the real-time data into standby chip data for output by the half-duplex interface module;

[0077] S24. Output the data of the chip to be used for N system clock cycles. During the N system clock cycles, the external microcontroller samples the most significant bit and the least significant bit of the data of the chip to be used.

[0078] S25. Repeat S22 to S225 until, in S23, the clock signal detected by the state machine is greater than the fourth time tW, and reset the half-duplex interface module, the parallel-to-serial module, and the counter; wherein, if S13 to S16 are repeated N times, the external microcontroller obtains the most significant bit of N pending chip data and the least significant bit of N pending chip data, and completes the forced data reading.

[0079] like Figure 3 As shown, this embodiment of the invention also provides a timing diagram in forced read mode. Figure 3 In the diagram, the blue line represents the microcontroller driver, and the dashed line represents the single-wire serial communication chip driver.

[0080] In one embodiment, when the register stores the initial chip data in a parallel data format, it adds header and tail codes for the microcontroller to recognize. Based on this, the format of the standby chip data output by the half-duplex interface module also includes header and tail codes for the microcontroller to facilitate microcontroller recognition and avoid communication garbled characters. For example, the output format of the standby chip data consists of a 2-bit header code (10), N bits of data, and a 1-bit tail code (0). The header and tail codes can be defined according to design requirements. Figure 4As shown, taking 16-bit data as an example, after the microcontroller sends the first clock signal, the chip starts outputting the 18th bit, which is the header code 1; then it sends the second clock signal, and after the two header codes 10 are output, it starts outputting the most significant bit of the 16-bit data. After each bit of data is output, the microcontroller needs to send another clock signal before the chip can output the next bit; after outputting all 16 bits of data, it outputs the tail code 0, completing this data output; then it is pulled low for a time tW or tF to complete the reset and wait for the next communication. The time required from the start of the clock signal for the first bit of data to the output of the last bit of data is the data period TREP.

[0081] In another embodiment of the present invention, the circuit structure of the half-duplex interface module in the single-wire serial communication chip is optimized. For example, the signal output branch of the half-duplex interface module includes an electrostatic protection circuit, and the signal input branch of the half-duplex interface module includes a shaping and filtering circuit.

[0082] like Figure 5 As shown, the signal output branch Data_OUT includes a first resistor R0, a second resistor R1, a third resistor R2, a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2. The first PMOS transistor MP1 and the first NMOS transistor MN1 form an inverter. The input of the inverter is connected to the output of the parallel-to-serial converter module. The output of the inverter is connected to the positive terminal of the first resistor R0. The negative terminal of the first resistor R0 is connected to the drain terminals of the second PMOS transistor MP2 and the second NMOS transistor MN2. The gate of the second PMOS transistor MP2 is connected to the digital power supply through the second resistor R1. The source terminal and the substrate of the second PMOS transistor MP2 are also connected to the digital power supply. The gate of the second NMOS transistor MN2 is grounded through the third resistor R2. The source terminal and the substrate of the second NMOS transistor MN2 are also grounded.

[0083] The signal input branch Data_IN includes a fourth resistor R3, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6. The third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 constitute a Schmitt trigger. The input of the Schmitt trigger is connected to the negative terminal of the fourth resistor R3, the output of the Schmitt trigger is connected to the state machine, and the positive terminal of the fourth resistor R3 is connected to an external microcontroller.

[0084] In the signal output branch, R0, R1, R2, MP2, and MN2 provide electrostatic discharge (ESD) protection for the port, preventing damage from electrostatic discharge. The dimensions of R0, R1, R2, MP2, and MN2 determine the ESD protection capability of the port. Designers can set relevant parameters according to the chip's own requirements when designing this circuit; this embodiment of the invention does not impose any limitations on these parameters.

[0085] The signal input branch uses a Schmitt trigger to shape and filter the external input signal, facilitating subsequent signal identification and processing. Specific device dimensions can also be set by the designer according to circuit requirements; this embodiment of the invention does not impose limitations on these dimensions.

[0086] This invention also provides a single-wire serial communication method applied to a host and a slave device that have established a communication connection, wherein both the host and the slave device use the single-wire serial communication chip described in the above embodiments, and the single-wire serial communication method includes:

[0087] The host detects the data storage status of the registers and the external input signals received by the half-duplex interface module, and instructs the half-duplex interface module, the parallel-to-serial converter, and the counter to output the chip data to the external microcontroller based on the data storage status of the registers and the external input signals received by the half-duplex interface module.

[0088] The parallel-to-serial module converts the initial chip data in the register into chip data to be used. The initial chip data is in parallel data format, and the chip data to be used is in serial data format.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A single-wire serial communication chip, characterized in that, It includes a half-duplex interface module, a parallel-to-serial conversion module, registers, counters, and a state machine; The state machine is connected to the register, the counter, and the half-duplex interface module. The register is also connected to the parallel-to-serial converter module. The parallel-to-serial converter module is also connected to the counter and the half-duplex interface module. The half-duplex interface module is connected to an external microcontroller. The register is used to store the initial chip data in a parallel data format; The counter counts based on the clock signal of the half-duplex interface module to generate a count value; The parallel-to-serial module is used to convert the initial chip data into a serial data format to obtain the chip data to be used, and output the chip data to the half-duplex interface module according to the count value generated by the counter. The half-duplex interface module includes a signal output branch and a signal input branch; both the signal input branch and the signal output branch are connected to an external microcontroller to receive external input signals from the external microcontroller and send the data of the chip to be used; the signal output branch is connected to the state machine and the parallel-to-serial conversion module to receive the count value generated by the parallel-to-serial conversion module, and the state machine detects the clock signal through the signal output branch; The state machine is used to instruct the half-duplex interface module, the parallel-to-serial converter, and the counter to output the chip data to be used to an external microcontroller based on the data storage state of the register and the external input signal received by the half-duplex interface module, including: If the half-duplex interface module does not receive the external input signal, and the data storage status of the register indicates that there is target data to be updated to the external microcontroller, then the state machine enters the data update mode. The data update mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the target data into standby chip data and output it to the external microcontroller according to the first working sequence, thereby completing the data update. If the half-duplex interface module receives the external input signal and the external input signal is of a preset type, the state machine enters the forced read mode. The forced read mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the real-time data stored in the register into the chip data to be used and output it to the external microcontroller according to the second working sequence, thereby completing the forced data read. Specifically, the data update includes: S11. The half-duplex interface module receives an update valid signal sent by the state machine. The update valid signal is generated when the half-duplex interface module has not received the external input signal and the data storage state of the register indicates that there is target data to be updated to the external microcontroller. S12. Pull the port line high according to the updated valid signal and continue for the first time; S13. Receive feedback level signal sent by external microcontroller, the feedback level signal including a first level signal generated by the external microcontroller pulling the port line low for a second time, and a second level signal generated by pulling the port line high for a third time after the second time. S14. A clock signal is generated based on the second level signal, so that when the state machine detects the clock signal, it sends the clock signal to the counter, the counter starts counting, and sends the count value to the parallel-to-serial module. The parallel-to-serial module modifies the most significant bit of the target data according to the count value to convert the target data into standby chip data for output by the half-duplex interface module. S15. Output the data of the chip to be used for N system clock cycles. During the N system clock cycles, the external microcontroller samples the most significant bit and the least significant bit of the data of the chip to be used. S17. Repeat S13 to S16 until, in S14, the clock signal detected by the state machine is greater than the fourth time, and reset the half-duplex interface module, the parallel-to-serial module, and the counter; wherein, if S13 to S16 are repeated N times, the external microcontroller obtains the most significant bits of N pending chip data and the least significant bits of N pending chip data, and completes the data update; Specifically, the forced data reading includes: S21. The half-duplex interface module blocks the update valid signal according to the forced read instruction, and at the same time pulls the port line high and continues for a first time according to the external input signal of the preset type; the forced read instruction is generated when the half-duplex interface module receives the external input signal and the external input signal is of the preset type. S22. Receive feedback level signal sent by an external microcontroller. The feedback level signal includes a first level signal generated by the external microcontroller pulling the port line low for a second time, and a second level signal generated by pulling the port line high for a third time after the second time. S23. A clock signal is generated based on the second level signal, so that when the state machine detects the clock signal, it sends the clock signal to the counter, the counter starts counting, and sends the count value to the parallel-to-serial module; wherein, the parallel-to-serial module modifies the most significant bit of the real-time data according to the count value, so as to convert the real-time data into standby chip data for output by the half-duplex interface module; S24. Output the data of the chip to be used for N system clock cycles. During the N system clock cycles, the external microcontroller samples the most significant bit and the least significant bit of the data of the chip to be used. S25. Repeat S22 to S225 until, in S23, the clock signal detected by the state machine is greater than the fourth time, and reset the half-duplex interface module, the parallel-to-serial module and the counter; wherein, if S13 to S16 are repeated N times, the external microcontroller obtains the most significant bit of N pending chip data and the least significant bit of N pending chip data, and completes the forced data reading.

2. The single-wire serial communication chip as described in claim 1, characterized in that, The signal output branch includes an electrostatic protection circuit, and the signal input branch includes a shaping and filtering circuit.

3. The single-wire serial communication chip as described in claim 2, characterized in that, The signal output branch includes a first resistor, a second resistor, a third resistor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; In this circuit, the first PMOS transistor and the first NMOS transistor form an inverter. The input of the inverter is connected to the output of the parallel-to-serial module, and the output of the inverter is connected to the positive terminal of the first resistor. The negative terminal of the first resistor is connected to the drain terminals of the second PMOS transistor and the second NMOS transistor. The gate of the second PMOS transistor is connected to the digital power supply through the second resistor. The source terminal and the substrate of the second PMOS transistor are also connected to the digital power supply. The gate of the second NMOS transistor is grounded through the third resistor, and the source terminal and the substrate of the second NMOS transistor are also grounded.

4. The single-wire serial communication chip as described in claim 2, characterized in that, The signal input branch includes a fourth resistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor constitute a Schmitt trigger. The input of the Schmitt trigger is connected to the negative terminal of the fourth resistor, the output of the Schmitt trigger is connected to the state machine, and the positive terminal of the fourth resistor is connected to an external microcontroller.

5. The single-wire serial communication chip as described in claim 1, characterized in that, When storing the initial chip data in a parallel data format, the register adds header and tail codes for the microcontroller to recognize.

6. A single-wire serial communication method, characterized in that, The method is applied to a host and a slave device that have established a communication connection, wherein both the host and the slave device use the single-wire serial communication chip as described in any one of claims 1 to 5, and the single-wire serial communication method includes: The host detects the data storage status of the registers and the external input signals received by the half-duplex interface module, and instructs the half-duplex interface module, the parallel-to-serial converter, and the counter to output the chip data to the external microcontroller based on the data storage status of the registers and the external input signals received by the half-duplex interface module. The parallel-to-serial module converts the initial chip data in the register into chip data to be used. The initial chip data is in parallel data format, and the chip data to be used is in serial data format.

7. The single-wire serial communication method as described in claim 6, characterized in that, Based on the data storage status of the registers and the external input signals received by the half-duplex interface module, the half-duplex interface module, parallel-to-serial converter, and counter are instructed to output the ready-to-use chip data to the external microcontroller, including: If the half-duplex interface module does not receive the external input signal, and the data storage status of the register indicates that there is target data to be updated to the external microcontroller, then the state machine enters the data update mode. The data update mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the target data into standby chip data and output it to the external microcontroller according to the first working sequence, thereby completing the data update. If the half-duplex interface module receives the external input signal, and the external input signal is of a preset type, the state machine enters the forced read mode. The forced read mode is used to instruct the half-duplex interface module, the parallel-to-serial module, and the counter to convert the real-time data stored in the register into standby chip data and output it to the external microcontroller according to the second working sequence, thereby completing the forced data read.

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