Clock synchronization method within SMP multi-core processor

Abstract

The SMP multi-core processor intra-core clock synchronization method of the present invention comprises selecting a master core clock as a source clock and synchronizing slave core clocks with the master core clock; before synchronization starts, all cores enter a synchronization ready state; when synchronization starts, all cores atomically record core numbers and clock counter values ​​into a shared memory by competing to obtain spin locks; by effectively sampling and recording data, calculating the deviation value between each slave core and the master core clock and the error value caused by the sampled and recorded data; calculating the correction value between each core and the master core clock counter based on the deviation value and the error value, modifying the slave core clock with the correction value, and completing slave core clock synchronization. The method can effectively solve the problem of inconsistent timestamps of each core in the multi-core processor and has the advantages of simple implementation, high efficiency, small error, and low occupation of system resources.

Description

Technical Field

[0001] The present invention belongs to the technical field of embedded multi-core systems, and in particular relates to a clock synchronization method within an SMP multi-core processor core. Background Art

[0002] An SMP multi-core processor is a symmetric multiprocessor (SMP). Each processor has multiple cores, each with independent resources and equivalent capabilities. In an embedded SMP multi-core system, the core used for system initialization is generally called the master core, while the other cores, which are awakened by the master core for operation, are called slave cores. After the system boots up, tasks can run on any core and can be switched between them. When a task needs to read the clock counter value within a core during execution, the clock counter values ​​differ significantly between cores due to their different startup times. When a task is switched between cores, the asynchronous clocks of the cores can cause errors, making the software prone to errors during execution. Summary of the Invention

[0003] In view of this, the SMP multi-core processor intra-core clock synchronization method of the present invention solves the technical problem that the existing technical method causes software to easily report errors during operation.

[0004] A method for synchronizing clocks within an SMP multi-core processor is applicable to scenarios where an airborne embedded multi-core system is used. The airborne embedded multi-core system includes a CPU processor and a clock counter. Each core of the processor corresponds to a clock counter, and includes the following steps:

[0005] S1: Determine a synchronous clock source, wherein any core of the processor is selected as a master core and the rest are slave cores, the clock of the master core is used as the source clock, and the clocks of the slave cores are synchronized with the clock of the master core;

[0006] S2: Determine a synchronization timing for all cores of the processor, wherein all cores are in a synchronization ready state before synchronization starts;

[0007] S3: Sampling and recording the values ​​of all the clock counters, wherein each core atomically records the core number and the value of its clock counter into a shared memory by competing to obtain the spin lock. The shared memory can record the core numbers and clock counter values ​​of all cores. The core that obtains the spin lock records its own core number and the value of the corresponding clock counter into the shared memory.

[0008] S4: Calculate the deviation values ​​of the clock counters of all slave cores and the master core, wherein a sampling value of the master core is selected from the recorded sampling values ​​as a base point value, and the next slave core sampling point after the base point value is selected as the time point of the selected slave core. The clock counter difference between the selected slave core and the base point value is recorded as Δt1, and the sampling natural sequence number difference is recorded as Δn1;

[0009] S5: Calculate the error value of the clock counter of all slave cores and the master core, wherein the last sampling value and the first sampling value of the same core number in the sampling value are selected, and the clock counter difference between them is recorded as Δt2, and the sampling natural sequence number difference is recorded as Δn2, and the error value d=Δt2 / Δn2 is calculated;

[0010] S6: Calculate the correction values ​​of the clock counters of all slave cores and the master core, wherein the correction value c=Δt1-d*Δn1 of the clock counter between the selected slave core and the master core is calculated based on the deviation value and the error value;

[0011] S7: Correct the clock of the selected slave core, wherein the clock count value of the selected slave core at the current moment is read out, the difference between the clock count value at the current moment and the correction value is determined, and the difference is written into the clock count register of the selected slave core, thereby achieving clock synchronization.

[0012] The technical beneficial effects of the present invention are:

[0013] The master core clock is selected as the source clock, and the slave core clock is synchronized with the master core clock; before the synchronization starts, all cores enter the synchronization ready state; when the synchronization starts, all cores atomically record the core number and the clock counter value into the shared memory by competing to obtain the spin lock; by effectively sampling and recording data, the deviation value between each slave core and the master core clock and the error value caused by the sampled and recorded data are calculated; the correction value between each core and the master core clock counter is calculated from the deviation value and the error value; the slave core clock is modified with the correction value to complete the slave core clock synchronization, which can effectively solve the problem of inconsistent timestamps of each core in the multi-core processor, and has the advantages of simple implementation, high efficiency, small error, and low system resource occupation. It effectively solves the clock synchronization problem within the SMP multi-core processor core and ensures the reliability and stability of the system operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0015] Figure 1Flowchart of clock synchronization within an SMP multi-core processor. DETAILED DESCRIPTION

[0016] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0017] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0018] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0019] like Figure 1 The method for synchronizing clocks within an SMP multi-core processor is applicable to scenarios where an airborne embedded multi-core system is used. The airborne embedded multi-core system includes a CPU processor and a clock counter. Each core of the processor corresponds to a clock counter, and includes the following steps:

[0020] S1: Determine a synchronous clock source, wherein any core of the processor is selected as the master core, and the rest are slave cores. The clock of the master core is used as the source clock, and the clocks of the slave cores are synchronized with the clock of the master core, that is, the slave cores are synchronized with the master core clock;

[0021] Furthermore, the determination of the master core includes: the core that is started when the onboard embedded system is powered on is used as the master core (only one core is running after the onboard embedded system is powered on, and the other cores need to be awakened by the master core before they can run), waking up the other slave cores after completing the system-related initialization, and the clock of the master core is used as the system clock. After the system initialization is completed, it is determined that the clock counter value of the master core cannot be modified.

[0022] S2: Determine the synchronization timing of all cores of the processor, wherein the synchronization timing is such that all cores are in a synchronization ready state before synchronization begins, that is, all cores will not execute other tasks;

[0023] S3: Sampling and recording the values ​​of all clock counters. Each core atomically records its core number and the value of its clock counter into a shared memory by competing to acquire a spin lock. The shared memory can record the core numbers and clock counter values ​​of all cores. (Competition refers to all cores acquiring a resource. Since there is only one resource, only one core can acquire the resource at a time. The spin lock is the resource to be acquired). The core that acquires the spin lock records its own core number and the value of the corresponding clock counter into the shared memory.

[0024] S4: Calculate the deviation value of the clock counter of all slave cores and the master core, wherein, from the recorded sampling values, select a sampling value of the master core as the base point value, select the slave core sampling point next to the base point value as the time point of the selected slave core, record the clock counter difference between the selected slave core and the base point value as Δt1, and record the sampling natural sequence number difference as Δn1;

[0025] S5: Calculate the error values ​​of the clock counters of all slave cores and the master core, wherein the last sampling value and the first sampling value of the same core number in the sampling value are selected, and the clock counter difference between them is recorded as Δt2, and the sampling natural sequence number difference is recorded as Δn2, and the error value d=Δt2 / Δn2 is calculated; for example, there are slave cores 1, 2, and 3, and the error value between slave core 1 and the master core is calculated, then the first sampling value of slave core 1 should be selected as A (sampling value A includes the natural sequence number A1 of the sampling record, core number 1, and the clock counter value A2), and the last sampling value of slave core 1 should be B. Similarly, sampling value B includes the natural sequence number B1 of the sampling record, core number 1, and the clock counter value B2, Δt2=B2-A2, Δn2=B1-A1;

[0026] S6: Calculate the correction values ​​of the clock counters of all slave cores and the master core, wherein the correction value c = Δt1 - d * Δn1 of the clock counters between the selected slave core and the master core is calculated based on the deviation value and the error value, and the error value is the time consumed by the atomic process recorded in each sampling;

[0027] S7: Correct the clock of the selected slave core, wherein the clock count value of the selected slave core at the current moment is read out, the difference between the clock count value at the current moment and the correction value is determined, and the difference is written into the clock count register of the selected slave core, thereby achieving clock synchronization.

[0028] As a specific implementation method provided in this case, each core has its own clock, and the clock frequencies of all cores are the same, but the values ​​of the clock counters are different.

[0029] As a specific implementation method provided in this case, the synchronization timing in S2 is that during the system startup process, the master core wakes up all the slave cores and performs clock synchronization. The purpose is to determine the synchronization timing and when to perform synchronization to avoid interference or additional impact on the embedded system.

[0030] As a specific implementation method provided in this case, the sampling and recording process in S3 is an atomic process. The atomic process can only sample the clock counter value of one core at the same time, and record the sampled count value and core number to the designated storage location, that is, record them in sequence in the sampling order.

[0031] As a specific implementation method provided in this case, the storage medium used for recording in S3 is a shared resource that can be accessed by all cores, such as memory.

[0032] As a specific implementation method provided in this case, S3 also includes judging the validity of the sampling results. If each core has sampling data, it is considered as valid sampling. Otherwise, it is considered as invalid sampling. Invalid sampling cannot synchronize the clocks of all slave cores.

[0033] Examples

[0034] This type of system uses a symmetric multi-core processor with four cores. Each core has a clock frequency of 1 GHz, and the processor's clock counter register is 64 bits. In this example, the sampled data is recorded in memory, and the total number of samples for all cores is 20. The specific steps are as follows:

[0035] 1. When the operating system starts, only core 0 of the processor is running. Core 0 is used as the master core. After completing the operating system initialization and waking up all slave cores, master core 0 enters the synchronous ready state.

[0036] 2. Slave cores 1-3 are awakened by the master core, and after completing related initialization, they enter the synchronization ready state.

[0037] 3. After all four cores enter the synchronized ready state, they begin competing for the clock-synchronized spin lock. The core that obtains the clock-synchronized spin lock records its core number and clock counter value in memory and releases the lock. Cores that fail to obtain the clock-synchronized spin lock enter a contention-waiting state until other cores release the lock. The next round of competition begins, and sampling and recording begins only after a core obtains the lock. After all cores perform 20 sampling operations, the resulting data is shown in the following table. The sampling records show that all four cores have sampled values, indicating that the sampling is valid.

[0038]

[0039] 4. Using the sixth sampling natural sequence as the base point, the ninth sampling natural sequence as the time point of core 1, the seventh sampling natural sequence as the time point of core 2, and the eighth sampling natural sequence as the time point of core 3, the time deviations of each core are calculated as follows: the time deviation of core 1 is -104264, and the sampling natural sequence number difference is 3; the time deviation of core 2 is -105957, and the sampling natural sequence number difference is 1; the time deviation of core 3 is -102732, and the sampling natural sequence number difference is 2;

[0040] 5. The error value of kernel 1 is calculated using the 0th and 17th sample data, the error value of kernel 2 is calculated using the 3rd and 18th sample data, and the error value of kernel 3 is calculated using the 1st and 16th sample data. The error values ​​calculated for each kernel are: the error value of kernel 1 is 53, the error value of kernel 2 is 53, and the error value of kernel 3 is 52;

[0041] 6. According to the calculation, the correction value of core 1 is -104423, the correction value of core 2 is -106010, and the correction value of core 3 is -102836.

[0042] Overall, compared with traditional methods, the method of the present invention has the advantages of simple implementation, high efficiency, small error, and less system resource occupation. It can effectively solve the problem of inconsistent timestamps among cores of a multi-core processor and improve the reliability and stability of system operation.

[0043] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for synchronizing clocks within an SMP multi-core processor, suitable for use in airborne embedded multi-core systems. The airborne embedded multi-core system includes a CPU processor and a clock counter, wherein each core of the processor corresponds to a clock counter, and is characterized in that: The following steps are involved: S1: Determine a synchronous clock source, wherein any core of the processor is selected as a master core and the rest are slave cores, the clock of the master core is used as the source clock, and the clocks of the slave cores are synchronized with the clock of the master core; S2: Determine a synchronization timing for all cores of the processor, wherein all cores are in a synchronization ready state before synchronization starts; S3: Sampling and recording the values ​​of all the clock counters, wherein each core atomically records the core number and the value of its clock counter into a shared memory by competing to obtain the spin lock. The shared memory can record the core numbers and clock counter values ​​of all cores. The core that obtains the spin lock records its own core number and the value of the corresponding clock counter into the shared memory. S4: Calculate the deviation values ​​of the clock counters of all slave cores and the master core, wherein a sampling value of the master core is selected from the recorded sampling values ​​as a base point value, and the next slave core sampling point after the base point value is selected as the time point of the selected slave core. The clock counter difference between the selected slave core and the base point value is recorded as Δt1, and the sampling natural sequence number difference is recorded as Δn1; S5: Calculate the error value of the clock counter of all slave cores and the master core, wherein the last sampling value and the first sampling value of the same core number in the sampling value are selected, and the clock counter difference between them is recorded as Δt2, and the sampling natural sequence number difference is recorded as Δn2, and the error value d=Δt2 / Δn2 is calculated; S6: Calculate the correction values ​​of the clock counters of all slave cores and the master core, wherein the correction value c=Δt1-d*Δn1 of the clock counter between the selected slave core and the master core is calculated based on the deviation value and the error value; S7: Correct the clock of the selected slave core, wherein the clock count value of the selected slave core at the current moment is read out, the difference between the clock count value at the current moment and the correction value is determined, and the difference is written into the clock count register of the selected slave core, thereby achieving clock synchronization.

2. The method for synchronizing the clock within an SMP multi-core processor according to claim 1, wherein: Each of the cores has its own clock, and the clock frequency of all the cores is the same, and the value of the clock counter is different.

3. The method for synchronizing clocks within a SMP multi-core processor according to claim 1, wherein: The determination of the master core in S1 includes: the core that is started when the onboard embedded system is powered on is used as the master core, and other slave cores are awakened after completing system-related initialization. The clock of the master core is used as the system clock. After the system initialization is completed, it is determined that the clock counter value of the master core cannot be modified.

4. The method for synchronizing clocks within a SMP multi-core processor according to claim 1, wherein: The synchronization timing in S2 is that during the system startup process, the master core wakes up all the slave cores and performs clock synchronization.

5. The method for synchronizing clocks within a SMP multi-core processor according to claim 1, wherein: The sampling and recording process in S3 is an atomic process, which can only sample the clock counter value of one core at a time, and record the sampled count value and core number in a designated storage location.

6. The method for synchronizing clocks within a SMP multi-core processor according to claim 1, wherein: The storage medium used for recording in S3 is a shared resource that can be accessed by all cores.

7. The method for synchronizing clocks within a SMP multi-core processor according to claim 1, wherein: S3 also includes judging the validity of the sampling results. If each core has sampling data, it is considered as valid sampling. Otherwise, it is considered as invalid sampling. Invalid sampling cannot synchronize the clocks of all slave cores.

8. The method for synchronizing clocks within an SMP multi-core processor according to claim 1, wherein: The error value is the time consumed by the atomic process recorded in each sampling.

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