A data routing method for a multi-core processor and related devices

Abstract

The present invention discloses a data routing method for a multi-core processor and related devices, belonging to the field of computer technology. The method includes: when a first core needs to access a second core for data, if it is determined that these two cores are in different rows and columns of a matrix topology, the data access frequency of the first core to the second core is statistically obtained to get a target frequency; if the target frequency is greater than a preset frequency, based on the principle that data can be transmitted along any direction in routing, the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core are respectively determined; with the principle of the shortest communication delay, the final routing transmission path corresponding to the first core when accessing the second core is determined according to the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core. This method can improve the access efficiency when two cores in a multi-core processor perform data access, reduce the communication delay between the two cores, and enhance the overall performance of the multi-core processor.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and particularly to a data routing method, apparatus, device, medium and computer program product for a multi-core processor. Background Art

[0002] Multi-core processors have very wide applications in the field of computer applications. In most multi-core processors, generally a routing algorithm is adopted to implement data access between two cores in the multi-core processor. Although the hardware implementation logic of this method is relatively simple and reliable, the efficiency of this algorithm is relatively low. Especially when two cores in the multi-core processor are far apart, the access route of one core to another core is very long, resulting in a large communication delay when the two cores perform data access, and thus reducing the overall performance of the multi-core processor. At present, there is no relatively effective solution to this technical problem.

[0003] Therefore, it can be seen that how to improve the access efficiency when two cores in a multi-core processor perform data access, reduce the communication delay between the two cores, and improve the overall performance of the multi-core processor is a technical problem that those skilled in the art need to solve urgently. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a data routing method, apparatus, device, medium and computer program product for a multi-core processor, so as to solve the problems of low efficiency, long communication delay time and poor overall performance of the multi-core processor when two cores in the related multi-core processor use the routing algorithm for data access.

[0005] To solve the above technical problem, the present invention provides a data routing method for a multi-core processor, including: when a first core needs to perform data access on a second core, determining whether the first core and the second core are in different rows and columns of a matrix topology; the first core and the second core are two different cores in the multi-core processor, all cores in the multi-core processor form the matrix topology, and all cores are respectively connected to a router in a one-to-one correspondence; if so, counting the data access frequency of the first core to the second core to obtain a target frequency; if the target frequency is greater than a preset frequency, based on the principle that the router can transmit data in any direction, respectively determining the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core; taking the shortest communication delay as the principle, determining the final routing transmission path corresponding to the first core when accessing the second core according to the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core.

[0006] In a specific embodiment of the present application, after determining whether the first core and the second core are in different rows and columns of the matrix topology, the method further includes: if not, then according to the routing algorithm, determine the final routing transmission path corresponding to the first core when accessing the second core.

[0007] In a specific embodiment of the present application, after statistically obtaining the data access frequency of the first core to the second core and obtaining the target frequency, the method further includes: if the target frequency is less than or equal to the preset frequency, then continue to execute the step of determining the final routing transmission path corresponding to the first core when accessing the second core according to the routing algorithm.

[0008] In a specific embodiment of the present application, based on the principle that the routing can perform data transmission in any direction, the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core are respectively determined, including: establishing a rectangular coordinate system corresponding to the matrix topology, and respectively determining the coordinates of the routing corresponding to the first core and the second core in the rectangular coordinate system to obtain a first coordinate point and a second coordinate point; determining the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core according to the first coordinate point, the second coordinate point, the shortest routing mapping table, and the second shortest routing mapping table; the creation process of the shortest routing mapping table and the second shortest routing mapping table includes: randomly screening two cores from the multi-core processor to obtain a third core and a fourth core, and respectively determining the coordinates of the routing corresponding to the third core and the fourth core in the rectangular coordinate system to obtain a third coordinate point and a fourth coordinate point; the third core and the fourth core are in different rows and columns of the matrix topology; taking the principle of first performing data transmission along the routing in the diagonal direction of the third coordinate point and the fourth coordinate point, and then performing data transmission along the routing in the X-axis direction or the Y-axis direction, determining the shortest routing transmission path when the third core accesses the fourth core; determining the shortest routing transmission path corresponding to any two cores in different rows and columns of the matrix topology when performing data access according to the shortest routing transmission path when the third core accesses the fourth core, and creating the shortest routing mapping table according to the shortest routing transmission path corresponding to any two cores in different rows and columns of the matrix topology when performing data access; adding 1 to the abscissa or ordinate of the third coordinate point to obtain a fifth coordinate point, and taking the principle of first performing data transmission along the routing in the diagonal direction of the fifth coordinate point and the fourth coordinate point, and then performing data transmission along the routing in the X-axis direction or the Y-axis direction, determining the second shortest routing transmission path when the third core accesses the fourth core; determining the second shortest routing transmission path corresponding to any two cores in different rows and columns of the matrix topology when performing data access according to the second shortest routing transmission path when the third core accesses the fourth core, and creating the second shortest routing mapping table according to the second shortest routing transmission path corresponding to any two cores in different rows and columns of the matrix topology when performing data access.

[0009] In a specific embodiment of the present application, taking the principle of first performing data transmission along the routing in the diagonal direction of the third coordinate point and the fourth coordinate point, and then performing data transmission along the routing in the X-axis direction or the Y-axis direction, to determine the shortest routing transmission path when the third core accesses the fourth core, includes: determining whether the routings in the diagonal direction of the third coordinate point and the fourth coordinate point are all on the same straight line; if so, determining the routing transmission path in the diagonal direction of the third coordinate point and the fourth coordinate point as the shortest routing transmission path when the third core accesses the fourth core; if not, determining a coordinate point with the same abscissa as the fourth coordinate point in the diagonal direction of the third coordinate point and the fourth coordinate point to obtain a first intermediate coordinate point, and determining a coordinate point with the same ordinate as the fourth coordinate point in the diagonal direction of the third coordinate point and the fourth coordinate point to obtain a second intermediate coordinate point; taking the principle of first performing data transmission along the connection line between the third coordinate point and the first intermediate coordinate point to reach the first intermediate coordinate point, and then performing data transmission along the Y-axis direction to reach the fourth coordinate point, to determine the number of routing forwards passed by the third core when accessing the fourth core, obtaining a first value; taking the principle of first performing data transmission along the connection line between the third coordinate point and the second intermediate coordinate point to reach the second intermediate coordinate point, and then performing data transmission along the X-axis direction to reach the fourth coordinate point, to determine the number of routing forwards passed by the third core when accessing the fourth core, obtaining a second value; determining whether the first value is less than the second value; if so, determining the routing transmission path of first performing data transmission along the connection line between the third coordinate point and the first intermediate coordinate point to reach the first intermediate coordinate point, and then performing data transmission along the Y-axis direction to reach the fourth coordinate point as the shortest routing transmission path when the third core accesses the fourth core.

[0010] In a specific embodiment of the present application, after determining whether the first value is less than the second value, it further includes: if not, determining the routing transmission path of first performing data transmission along the connection line between the third coordinate point and the second intermediate coordinate point to reach the second intermediate coordinate point, and then performing data transmission along the X-axis direction to reach the fourth coordinate point as the shortest routing transmission path when the third core accesses the fourth core.

[0011] In a specific embodiment of the present application, taking the shortest communication delay as the principle, determining the final routing transmission path corresponding to the first core when accessing the second core according to the shortest routing transmission path and the second-shortest routing transmission path of the first core when accessing the second core includes: determining the final routing transmission path corresponding to the first core when accessing the second core according to the line congestion information on the shortest routing transmission path of the first core when accessing the second core and the line congestion information on the second-shortest routing transmission path of the first core when accessing the second core.

[0012] In a specific embodiment of the present application, determining the final routing transmission path corresponding to the first core when accessing the second core according to the line congestion information on the shortest routing transmission path of the first core when accessing the second core and the line congestion information on the second-shortest routing transmission path of the first core when accessing the second core includes: determining all the core groups in the multi-core processor that are performing data transmission at the current moment to obtain a first set; determining a second set according to the first set; wherein, for any element in the second set, the two cores corresponding to it are in different rows and columns of the matrix topology; determining the shortest routing transmission paths of the two cores corresponding to each element in the second set when performing data access to obtain a first path set; determining the other routes except the routes corresponding to the first core and the second core in the shortest routing transmission path of the first core when accessing the second core to obtain a first route set; calculating the total number of times that all the routes in the first route set appear in the shortest routing transmission paths corresponding to each element in the first path set to obtain a first number; determining the second-shortest routing transmission paths of the two cores corresponding to each element in the second set when performing data access to obtain a second path set; determining the other routes except the routes corresponding to the first core and the second core in the second-shortest routing transmission path of the first core when accessing the second core to obtain a second route set; determining the total number of times that all the routes in the second route set appear in the second-shortest routing transmission paths corresponding to each element in the second path set to obtain a second number; determining the final routing transmission path corresponding to the first core when accessing the second core according to the first number and the second number.

[0013] In a specific implementation manner of the present application, determining the final routing transmission path corresponding to the first core when accessing the second core according to the first number and the second number includes: determining whether the sum of the first number and a first preset threshold is less than the second number; if so, determining the shortest routing transmission path of the first core when accessing the second core as the final routing transmission path corresponding to the first core when accessing the second core; if not, determining the second shortest routing transmission path of the first core when accessing the second core as the final routing transmission path corresponding to the first core when accessing the second core.

[0014] In a specific implementation manner of the present application, it further includes: setting the first preset threshold on the principle of preferentially selecting the shortest routing transmission path of the first core when accessing the second core as the final routing transmission path corresponding to the first core when accessing the second core.

[0015] In a specific implementation manner of the present application, after obtaining the second number by determining the total number of occurrences of all the routes in the second routing set in the second shortest routing transmission paths corresponding to each element in the second path set, it further includes: determining a third set according to the first set; where any two cores corresponding to an element in the third set are in the same column or the same row of the matrix topology; determining the shortest routing transmission paths of the two cores corresponding to each element in the third set when performing data access to obtain a third path set; calculating the total number of occurrences of all the routes in the first routing set in the shortest routing transmission paths corresponding to each element in the third path set to obtain a third number; determining the second shortest routing transmission paths of the two cores corresponding to each element in the third set when performing data access to obtain a fourth path set; determining the total number of occurrences of all the routes in the second routing set in the second shortest routing transmission paths corresponding to each element in the fourth path set to obtain a fourth number; determining the final routing transmission path corresponding to the first core when accessing the second core according to the first number, the second number, the third number, the fourth number, a first weight value, a second weight value, a third weight value, and a fourth weight value.

[0016] In a specific embodiment of the present application, determining the final routing transmission path corresponding to the first core when accessing the second core according to the first number, the second number, the third number, the fourth number, the first weight value, the second weight value, the third weight value, and the fourth weight value includes: obtaining the product of the first number and the first weight value to obtain a first product value, and obtaining the product of the third number and the third weight value to obtain a third product value; adding the first product value and the third product value to obtain a first added value; obtaining the product of the second number and the second weight value to obtain a second product value, and obtaining the product of the fourth number and the fourth weight value to obtain a fourth product value; adding the second product value and the fourth product value to obtain a second added value; determining whether the sum of the first added value and a second preset threshold is less than the second added value; if so, determining the shortest routing transmission path of the first core when accessing the second core as the final routing transmission path corresponding to the first core when accessing the second core; if not, determining the second shortest routing transmission path of the first core when accessing the second core as the final routing transmission path corresponding to the first core when accessing the second core.

[0017] To solve the above technical problems, the present invention also provides a data routing device for a multi-core processor, including: a memory for storing a computer program; a processor for executing the computer program to implement the steps of a data routing method for a multi-core processor as disclosed above.

[0018] To solve the above technical problems, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of a data routing method for a multi-core processor as disclosed above are implemented.

[0019] To solve the above technical problems, the present invention also provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, the steps of a data routing method for a multi-core processor as disclosed above are implemented.

[0020] Beneficial effects: In the data routing method for a multi-core processor provided by the present invention, when the first core needs to access data from the second core, first, it is determined whether the first core and the second core are in different rows and columns of the matrix topology; the first core and the second core are two different cores in the multi-core processor, all cores in the multi-core processor form a matrix topology, and all cores are connected to a router one by one; if the first core and the second core are in different rows and columns of the matrix topology, it means using The routing transmission path calculated by the routing algorithm when the first core accesses the second core is not the shortest routing transmission path when the first core accesses the second core. At this time, it is necessary to count the frequency of the first core sending data to the second core to obtain the target frequency. If the target frequency is greater than the preset frequency, it means that the frequency of the first core sending data to the second core is relatively high. In this case, it is possible to not be limited to the original physical communication links in the multi-core processor, but to determine the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core based on the principle that the routing can transmit data in any direction. In this setting method, since the routing can transmit data in any direction, compared with the routing algorithm, the number of routing forwards required for data access between two cores in the multi-core processor can be relatively reduced.

[0021] Moreover, after determining the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core, the principle of the shortest communication delay is also followed, and the final routing transmission path corresponding to the first core when accessing the second core is determined according to the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core. In this way, the network congestion problem during data access between two cores in the multi-core processor is fully considered, and thus the communication delay during data access between two cores in the multi-core processor can be significantly reduced, and the overall performance of the multi-core processor can be greatly improved.

[0022] Correspondingly, a data routing device, device, medium and computer program product of a multi-core processor provided by the present invention also have the above beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 For the schematic diagram of the processor architecture.

[0025] Figure 2 It is the flowchart of a data routing method for a multi-core processor provided by an embodiment of the present invention.

[0026] Figure 3 It is the topology schematic diagram of a multi-core processor provided by an embodiment of the present invention.

[0027] Figure 4 For Figure 3Data forwarding schematic diagram of any one of the routers in the shown topological schematic diagram.

[0028] Figure 5 Hardware architecture diagram when two different cores in a multi-core processor perform data access provided by an embodiment of the present invention.

[0029] Figure 6 Structural diagram of a data routing device of a multi-core processor provided by an embodiment of the present invention.

[0030] Figure 7 Structural diagram of a data routing device of a multi-core processor provided by an embodiment of the present invention. Detailed implementation manners

[0031] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0032] The terms "include" and "have" in the specification of the present invention and the accompanying drawings above, as well as any variations related to "include" and "have", are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0033] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0034] The currently more common multi-core processor is a 16-core processor ( , the fifth-generation reduced instruction set computer), and in the architecture of the processor, a network is usually used for interconnection. Please refer to Figure 1 , Figure 1 which is the architecture schematic diagram of the processor. In the Figure 1 shown processor, there are a total of 16 cores, and each core is connected with a router one by one. From the perspective of the software application layer, these 16 cores are a processor ( , the central processing unit). That is to say, the operations of application software are usually performed by these 16 cores in the processor. The operations and processing of data are completed within the cores of the processor, and the routers connected to the cores are responsible for data forwarding. For example, when the program running on core 1 needs to access the result of the program running on core 15, core 1 will issue a command to access the corresponding cache on core 15 and retrieve the data from the corresponding cache on core 15, and then perform operations on core 1. Among them, how the instruction issued by core 1 finds core 15 is the function that the routing forwarding needs to achieve.

[0035] In the related art, the data access between two cores in a multi-core processor is usually implemented by a routing algorithm. Please refer to Figure 1 . If core 0 wants to access the data of core 15, the instruction issued by core 0 first needs to pass through routers 1, 2, and 3 along the X-axis direction. After reaching router 3, it then passes through routers 7, 11, and 15 along the Y-axis direction before core 0 can access the data in core 15. In this process, core 0 needs to pass through 6 routers when accessing the data of core 15, and the communication delay between processes is relatively large, which will greatly reduce the overall performance of the multi-core processor.

[0036] In the present invention, in order to solve the above technical problems, a new data routing method for a multi-core processor is provided. By using this method, the problems of low efficiency, long communication delay time, and poor overall performance of the multi-core processor when two cores in the multi-core processor use the algorithm for data access can be solved.

[0037] Please refer to Figure 2 . Figure 2 is a flowchart of a data routing method for a multi-core processor provided by an embodiment of the present invention. The method includes:

[0038] Step S11: When a first core wants to access the data of a second core, determine whether the first core and the second core are in different rows and columns of the matrix topology; the first core and the second core are two different cores in the multi-core processor, all the cores in the multi-core processor form a matrix topology, and all the cores are connected to a router one by one.

[0039] Step S12: If so, count the data access frequency of the first core to the second core to obtain a target frequency.

[0040] Step S13: If the target frequency is greater than a preset frequency, based on the principle that the router can transmit data in any direction, respectively determine the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core.

[0041] Step S14: Based on the principle of the shortest communication delay, determine the final routing transmission path corresponding to the first core when accessing the second core according to the shortest routing transmission path and the second shortest routing transmission path of the first core when accessing the second core.

[0042] A data routing method for a multi-core processor provided by the present invention is described with a process in the first core of the multi-core processor as the execution subject. Among them, multiple cores are provided in the multi-core processor, and these cores are usually arranged in a matrix array in the multi-core processor. In other words, all the cores in the multi-core processor form a matrix topology. And, a router is connected to each of all the cores in the multi-core processor one by one. The first core and the second core are two different cores in the multi-core processor.

[0043] When the first core needs to access data from the second core, first, it is judged whether the first core and the second core are in different rows and columns of the matrix topology. If the first core and the second core are in different rows and columns of the matrix topology, it means that the routing algorithm cannot find the shortest routing transmission path of the first core when accessing the second core. At this time, in order to reduce the resource overhead of the multi-core processor, it is also necessary to count the data access frequency of the first core to the second core to obtain the target frequency, and judge whether the target frequency is greater than the preset frequency.

[0044] If the target frequency is greater than the preset frequency, based on the principle that the routing can transmit data in any direction, determine the shortest routing transmission path and the second shortest routing transmission path of the first core when accessing the second core respectively. That is to say, when the data access frequency of the first core to the second core is greater than the preset frequency, the router on any core in the multi-core processor can transmit data not limited to the X-axis and Y-axis, but can transmit data in any direction.

[0045] Please refer to Figure 3 , Figure 3 which is a topology schematic diagram of a multi-core processor provided by an embodiment of the present invention. In the Figure 3 multi-core processor shown, there are 16 cores, and a router is connected to each core one by one. In the rectangular coordinate system established by the matrix topology of the multi-core processor, in addition to being able to transmit data along the X-axis and Y-axis directions, the router connected to each core can also transmit data along the router in the direction of its diagonal connection. For example: Figure 3 The router 0 in

[0046] Please refer to Figure 4 , Figure 4 is Figure 3The data forwarding schematic diagram of any one of the routers in the shown topological schematic diagram. From Figure 4 it can be seen that Figure 3 any one of the routers in

[0047] not only can forward and transmit data along the X-axis direction and the Y-axis direction, but also can forward and transmit data along its diagonal direction. Compared with the prior art, we can call the link for the router to transmit data along the X-axis direction and the Y-axis direction a conventional routing link, and call the link for transmitting data along its diagonal direction a special routing link. In the related art, in a multi-core processor, generally only a conventional routing link is set between two adjacent cores, and no special routing link is set.

[0048] Based on the principle that the router can transmit data in any direction, it is necessary to separately determine the shortest routing transmission path and the sub-shortest routing transmission path when the first core accesses the second core. In this setting mode, the shortest routing transmission path and the sub-shortest routing transmission path when the first core accesses the second core include some routing transmission paths at the diagonal positions. Compared with only using the routing transmission paths on the straight lines of the X-axis direction and the Y-axis direction, this can reduce the number of routing forwards when the first core accesses the second core, and thus improve the efficiency of the first core when accessing data from the second core.

[0049] In this setting mode, the network congestion problem when two cores in the multi-core processor access data is fully considered, which can significantly reduce the communication delay when two cores in the multi-core processor access data, and greatly improve the overall performance of the multi-core processor.

[0050] Based on the above embodiments, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation manner, after the above step: determining whether the first core and the second core are in different rows and columns of the matrix topology, it further includes: if not, then according to the routing algorithm to determine the final routing transmission path corresponding to the first core when accessing the second core.

[0051] In practical applications, if the first core and the second core are not in different rows and columns of the matrix topology, it means that the first core and the second core are in the same row or the same column of the matrix topology. In this case, the routing algorithm can be continued to determine the final routing transmission path corresponding to the first core when accessing the second core. That is, the first core can forward data along the routing in the X-axis or Y-axis direction of the rectangular coordinate system where the matrix topology is located, and the shortest routing transmission path for accessing the second core can be found.

[0052] As a preferred implementation manner, after the above step of statistically analyzing the data access frequency of the first core to the second core and obtaining the target frequency, it further includes: if the target frequency is less than or equal to the preset frequency, continue to execute the step of determining the final routing transmission path corresponding to the first core when accessing the second core according to the routing algorithm.

[0053] In this embodiment, if the data access frequency of the first core to the second core is less than or equal to the preset frequency, it means that the data access frequency of the first core to the second core is relatively low. Considering the resource overhead and power consumption required by the multi-core processor, it is not necessary to establish a routing communication link on the diagonal of the first core and the second core. At this time, continue to determine the final routing transmission path corresponding to the first core when accessing the second core according to the routing algorithm.

[0054] If the routing algorithm described in the present invention that can perform data transmission along any direction is called a special routing algorithm, then according to the technical solution provided in this embodiment, it is possible to achieve adaptive switching between the routing algorithm and the special routing algorithm under different trigger conditions, so that the shortest routing transmission path when the first core accesses the second core can be accurately determined in different application scenarios.

[0055] Based on the above embodiment, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation manner, the above step of respectively determining the shortest routing transmission path and the sub-shortest routing transmission path when the first core accesses the second core based on the principle that the routing can perform data transmission along any direction includes: establishing a plane rectangular coordinate system corresponding to the matrix topology, and respectively determining the coordinates of the routing corresponding to the first core and the second core in the plane rectangular coordinate system to obtain the first coordinate point and the second coordinate point; respectively determining the shortest routing transmission path and the sub-shortest routing transmission path when the first core accesses the second core according to the first coordinate point, the second coordinate point, the shortest routing mapping table, and the sub-shortest routing mapping table.

[0056] Among them, the creation process of the shortest routing mapping table and the second shortest routing mapping table includes: randomly selecting two cores from the multi-core processor to obtain the third core and the fourth core, and respectively determining the coordinates of the routes corresponding to the third core and the fourth core in the plane rectangular coordinate system to obtain the third coordinate point and the fourth coordinate point; the third core and the fourth core are in different rows and columns of the matrix topology; taking the principle of first transmitting data along the route in the diagonal direction of the third coordinate point and the fourth coordinate point, and then transmitting data along the route in the X-axis direction or the Y-axis direction, to determine the shortest routing transmission path when the third core accesses the fourth core; determining the shortest routing transmission paths corresponding to any two cores in different rows and columns of the matrix topology when accessing data according to the shortest routing transmission path when the third core accesses the fourth core, and creating the shortest routing mapping table according to the shortest routing transmission paths corresponding to any two cores in different rows and columns of the matrix topology when accessing data; adding 1 to the abscissa or ordinate of the third coordinate point to obtain the fifth coordinate point, and taking the principle of first transmitting data along the route in the diagonal direction of the fifth coordinate point and the fourth coordinate point, and then transmitting data along the route in the X-axis direction or the Y-axis direction, to determine the second shortest routing transmission path when the third core accesses the fourth core; determining the second shortest routing transmission paths corresponding to any two cores in different rows and columns of the matrix topology when accessing data according to the second shortest routing transmission path when the third core accesses the fourth core, and creating the second shortest routing mapping table according to the second shortest routing transmission paths corresponding to any two cores in different rows and columns of the matrix topology when accessing data.

[0057] In this embodiment, in order to determine the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core, it is necessary to pre-create the shortest routing mapping table and the second shortest routing mapping table. Among them, the shortest routing mapping table stores the shortest routing transmission paths corresponding to any two cores in different rows and columns of the matrix topology. That is to say, the shortest routing mapping table stores any two cores in different rows and columns of the matrix topology and their corresponding shortest routing transmission paths. The second shortest routing mapping table stores the second shortest routing transmission paths corresponding to any two cores in different rows and columns of the matrix topology. That is to say, the second shortest routing mapping table stores any two cores in different rows and columns of the matrix topology and their corresponding second shortest routing transmission paths.

[0058] Specifically, when creating the shortest route mapping table, first, two cores are randomly selected from the multi-core processor to obtain the third core and the fourth core, and the coordinates of the routes corresponding to the third core and the fourth core in the plane rectangular coordinate system are determined respectively to obtain the third coordinate point and the fourth coordinate point. Among them, the rectangular coordinate system is the plane rectangular coordinate system corresponding to the matrix topology. The third core and the fourth core are in different rows and columns of the matrix topology.

[0059] Since the third core and the fourth core are respectively located in different rows and columns of the matrix topology, therefore, the shortest route transmission path corresponding to the third core when accessing the fourth core must include a route transmission path on the diagonal. For example: in Figure 3 If core 0 wants to access core 15 for data, by observation, the shortest route transmission path corresponding to core 0 when accessing core 15 is: route 0 → route 5 → route 10 → route 15. If core 1 wants to access core 11 for data, by observation, the shortest route transmission path corresponding to core 1 when accessing core 11 is: route 1 → route 6 → route 11. If core 0 wants to access core 11 for data, by observation, the shortest route transmission path corresponding to core 0 when accessing core 11 is: route 0 → route 5 → route 10 → route 11.

[0060] In view of this situation, in order to find the shortest route transmission path when the third core accesses the fourth core, it can be based on the principle of first transmitting data along the route on the diagonal direction of the third coordinate point and the fourth coordinate point, and then transmitting data along the route in the X-axis direction or the Y-axis direction, to determine the shortest route transmission path when the third core accesses the fourth core.

[0061] When the shortest route transmission path when the third core accesses the fourth core is determined, it is equivalent to determining the shortest route transmission path between any group of cores in different rows and columns in the matrix topology. At this time, according to the same method, the shortest route transmission path corresponding to any two cores in different rows and columns in the matrix topology when accessing data can be determined. In this case, the shortest route mapping table can be created according to the shortest route transmission path corresponding to any two cores in different rows and columns in the matrix topology when accessing data.

[0062] When creating the sub-shortest route mapping table, first, 1 is added to the abscissa or ordinate of the third coordinate point to obtain the fifth coordinate point. Then, based on the principle of first transmitting data along the route on the diagonal direction of the fifth coordinate point and the fourth coordinate point, and then transmitting data along the route in the X-axis direction or the Y-axis direction, to determine the sub-shortest route transmission path when the third core accesses the fourth core.

[0063] It should be noted that in practical applications, in order to avoid routing access blockage or line congestion, when determining the sub-shortest routing transmission path for two adjacent cores to access other cores, the routing corresponding to the adjacent cores needs to be transmitted separately along the X-axis and Y-axis. For example: in Figure 3 if core 0 wants to access core 15, then the sub-shortest routing transmission path corresponding to core 0 when accessing core 15 is: routing 0 → routing 1 → routing 6 → routing 11 → routing 15. If core 1 wants to access core 11, then the sub-shortest routing transmission path corresponding to core 1 when accessing core 11 is: routing 1 → routing 5 → routing 10 → routing 11. In this setting method, when determining the sub-shortest routing transmission path for the third core to access the fourth core, it is actually set based on one more routing forwarding than the shortest routing transmission path for the third core to access the fourth core.

[0064] When the sub-shortest routing transmission path for the third core to access the fourth core is determined, it is equivalent to determining the sub-shortest routing transmission path between any group of cores in different rows and columns in the matrix topology. According to the same method, the sub-shortest routing transmission path corresponding to any two cores in different rows and columns in the matrix topology when accessing data can be determined. In this case, the sub-shortest routing mapping table can be created based on the sub-shortest routing transmission path corresponding to any two cores in different rows and columns in the matrix topology when accessing data.

[0065] After the shortest routing mapping table and the sub-shortest routing mapping table are created, it is possible to find any two cores in different rows and columns in the matrix topology and their corresponding shortest routing transmission paths from the shortest routing mapping table, and find any two cores in different rows and columns in the matrix topology and their corresponding sub-shortest routing transmission paths from the sub-shortest routing mapping table.

[0066] In this case, in order to determine the shortest routing transmission path and the sub-shortest routing transmission path for the first core to access the second core, it is only necessary to determine the coordinates of the routing corresponding to the first core and the second core in the plane rectangular coordinate system respectively to obtain the first coordinate point and the second coordinate point; then, according to the first coordinate point, the second coordinate point and the shortest routing mapping table, the shortest routing transmission path for the first core to access the second core can be determined; finally, according to the first coordinate point, the second coordinate point and the sub-shortest routing mapping table, the sub-shortest routing transmission path for the first core to access the second core can be determined.

[0067] Obviously, through the technical solution provided in this embodiment, the shortest routing transmission path and the sub-shortest routing transmission path for the first core to access the second core can be found more quickly from the shortest routing mapping table and the sub-shortest routing mapping table respectively.

[0068] As a preferred embodiment, the above steps: taking the principle of first performing data transmission along the route in the diagonal direction of the third coordinate point and the fourth coordinate point, and then performing data transmission along the route in the X-axis direction or the Y-axis direction, determine the shortest route transmission path when the third core accesses the fourth core, including: determining whether the routes in the diagonal direction of the third coordinate point and the fourth coordinate point are all on the same straight line; if so, determining the route transmission path in the diagonal direction of the third coordinate point and the fourth coordinate point as the shortest route transmission path when the third core accesses the fourth core; if not, determining a coordinate point with the same abscissa as the fourth coordinate point in the diagonal direction of the third coordinate point and the fourth coordinate point to obtain a first intermediate coordinate point, and determining a coordinate point with the same ordinate as the fourth coordinate point in the diagonal direction of the third coordinate point and the fourth coordinate point to obtain a second intermediate coordinate point; taking the principle of first performing data transmission along the connection line between the third coordinate point and the first intermediate coordinate point to reach the first intermediate coordinate point, and then performing data transmission along the Y-axis direction to reach the fourth coordinate point, determine the number of route forwards passed by the third core when accessing the fourth core to obtain a first value; taking the principle of first performing data transmission along the connection line between the third coordinate point and the second intermediate coordinate point to reach the second intermediate coordinate point, and then performing data transmission along the X-axis direction to reach the fourth coordinate point, determine the number of route forwards passed by the third core when accessing the fourth core to obtain a second value; determining whether the first value is less than the second value; if so, determining the route transmission path of first performing data transmission along the connection line between the third coordinate point and the first intermediate coordinate point to reach the first intermediate coordinate point, and then performing data transmission along the Y-axis direction to reach the fourth coordinate point as the shortest route transmission path when the third core accesses the fourth core; if not, determining the route transmission path of first performing data transmission along the connection line between the third coordinate point and the second intermediate coordinate point to reach the second intermediate coordinate point, and then performing data transmission along the X-axis direction to reach the fourth coordinate point as the shortest route transmission path when the third core accesses the fourth core.

[0069] In this embodiment, the process of determining the shortest route transmission path when the third core accesses the fourth core is specifically described. When determining the shortest route transmission path when the third core accesses the fourth core, first, it is determined whether the routes in the diagonal direction of the third coordinate point and the fourth coordinate point are all on the same straight line.

[0070] If the routes in the diagonal direction between the third coordinate point and the fourth coordinate point are all on the same straight line, it means that the third core can quickly access the fourth core with the shortest routing transmission path by only forwarding data through the routes in the diagonal direction between the third coordinate point and the fourth coordinate point. In this case, the routing transmission path in the diagonal direction between the third coordinate point and the fourth coordinate point can be determined as the shortest routing transmission path when the third core accesses the fourth core.

[0071] Please refer to Figure 3 , assuming that the coordinates of route 12 corresponding to core 12 are , if core 0 wants to access core 15 for data, then the coordinates of route 0 are , and the coordinates of route 15 are . The routes in the diagonal direction between route 0 and route 15 are all on the same straight line. At this time, route 0 → route 5 → route 10 → route 15 can be determined as the shortest routing transmission path when core 0 accesses core 15.

[0072] If the routes in the diagonal direction between the third coordinate point and the fourth coordinate point are not all on the same straight line, then it is necessary to first determine the coordinate point with the same abscissa as the fourth coordinate point in the diagonal direction between the third coordinate point and the fourth coordinate point to obtain the first intermediate coordinate point, and determine the coordinate point with the same ordinate as the fourth coordinate point in the diagonal direction between the third coordinate point and the fourth coordinate point to obtain the second intermediate coordinate point.

[0073] Then, based on the principle of first transmitting data along the connection line between the third coordinate point and the first intermediate coordinate point to reach the first intermediate coordinate point, and then transmitting data along the Y-axis direction to reach the fourth coordinate point, determine the number of route forwards passed by the third core when accessing the fourth core to obtain the first value; then, based on the principle of first transmitting data along the connection line between the third coordinate point and the second intermediate coordinate point to reach the second intermediate coordinate point, and then transmitting data along the X-axis direction to reach the fourth coordinate point, determine the number of route forwards passed by the third core when accessing the fourth core to obtain the second value.

[0074] Finally, it is determined again whether the first value is less than the second value; if the first value is less than the second value, the routing transmission path that first transmits data along the connection line between the third coordinate point and the first intermediate coordinate point to reach the first intermediate coordinate point, and then transmits data along the Y-axis direction to reach the fourth coordinate point is determined as the shortest routing transmission path when the third core accesses the fourth core. If the first value is greater than the second value, the routing transmission path that first transmits data along the connection line between the third coordinate point and the second intermediate coordinate point to reach the second intermediate coordinate point, and then transmits data along the X-axis direction to reach the fourth coordinate point is determined as the shortest routing transmission path when the third core accesses the fourth core.

[0075] Please refer to Figure 3 , assuming that the coordinates of the route 12 corresponding to the core 12 are , if core 0 wants to access data from core 11, then the coordinates of the route 0 corresponding to core 0 are , and the coordinates of the route 11 corresponding to core 11 are . Since the routes in the diagonal direction between route 0 and route 11 are not all on the same straight line, it is necessary to find the first intermediate point and the second intermediate point between route 0 and route 11 at this time. Among them, the coordinates of the first intermediate point between route 0 and route 11 are , and the coordinates of the second intermediate point are .

[0076] In this case, if first transmitting data along the connection line between route 0 and the first intermediate coordinate point to reach the first intermediate point , and then transmitting data along the Y-axis direction to reach route 11 , then the routing transmission path when core 0 accesses core 11 is: route 0 → route 5 → route 10 → route 15 → route 11, and the number of route forwards it passes through is 5, and the first value is 5 at this time.

[0077] If first transmitting data along the connection line between route 0 and the second intermediate coordinate point to reach the second intermediate point , and then transmitting data along the X-axis direction to reach route 11 , then the routing transmission path when core 0 accesses core 11 is: route 0 → route 5 → route 10 → route 11, and the number of route forwards it passes through is 4, and the second value is 4 at this time. Since the first value 5 is greater than the first value 4. At this time, the route 0 → route 5 → route 10 → route 11 can be determined as the shortest routing transmission path when core 0 accesses core 11.

[0078] When determining the sub-shortest routing transmission path for the third core to access the fourth core, it is necessary to first add 1 to the abscissa or ordinate of the third coordinate point to obtain the fifth coordinate point, and then the sub-shortest routing transmission path for the third core to access the fourth core can be determined according to the method of determining the shortest routing transmission path for the third core to access the fourth core as described above. The process will not be elaborated in detail here.

[0079] Obviously, through the technical solution provided in this embodiment, the shortest routing transmission path for the third core to access the fourth core can be accurately found.

[0080] Based on the above embodiment, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation manner, the above step: taking the shortest communication delay as the principle, determining the final routing transmission path corresponding to the first core when accessing the second core according to the shortest routing transmission path and the sub-shortest routing transmission path for the first core to access the second core, includes: determining the final routing transmission path corresponding to the first core when accessing the second core according to the line congestion information on the shortest routing transmission path for the first core to access the second core and the line congestion information on the sub-shortest routing transmission path for the first core to access the second core.

[0081] In this embodiment, when taking the shortest communication delay as the principle and determining the final routing transmission path corresponding to the first core when accessing the second core according to the shortest routing transmission path and the sub-shortest routing transmission path for the first core to access the second core, in fact, it is to determine the final routing transmission path corresponding to the first core when accessing the second core according to the line congestion information on the shortest routing transmission path for the first core to access the second core and the line congestion information on the sub-shortest routing transmission path for the first core to access the second core.

[0082] It is not difficult to think that during the process of a multi-core processor performing arithmetic processing on data, multiple groups of cores may simultaneously perform data access and transmission. In this case, there will surely be a phenomenon of line congestion on some routing transmission paths. If the first core and the second core perform data forwarding and transmission on the congested routing path, it will surely increase the communication delay time when the first core accesses the second core. Therefore, in this embodiment, the final routing transmission path corresponding to the first core when accessing the second core is determined according to the line congestion information on the shortest routing transmission path for the first core to access the second core and the line congestion information on the sub-shortest routing transmission path for the first core to access the second core.

[0083] Obviously, through the technical solution provided in this embodiment, the communication delay time when the first core accesses the second core can be reduced.

[0084] As a preferred embodiment, the above step of determining the final routing transmission path corresponding to the first core when accessing the second core according to the line congestion information on the shortest routing transmission path when the first core accesses the second core and the line congestion information on the sub-shortest routing transmission path when the first core accesses the second core includes: determining, at the current moment, all core groups in the multi-core processor that are performing data transmission to obtain a first set; determining a second set according to the first set; wherein, for any element in the second set, the two cores corresponding to it are in different rows and columns of the matrix topology; determining the shortest routing transmission paths of the two cores corresponding to each element in the second set when performing data access to obtain a first path set; determining the other routes except the routes corresponding to the first core and the second core in the shortest routing transmission path when the first core accesses the second core to obtain a first route set; calculating the total number of times all the routes in the first route set appear in the shortest routing transmission paths corresponding to each element in the first path set to obtain a first number; determining the sub-shortest routing transmission paths of the two cores corresponding to each element in the second set when performing data access to obtain a second path set; determining the other routes except the routes corresponding to the first core and the second core in the sub-shortest routing transmission path when the first core accesses the second core to obtain a second route set; determining the total number of times all the routes in the second route set appear in the sub-shortest routing transmission paths corresponding to each element in the second path set to obtain a second number; determining the final routing transmission path corresponding to the first core when accessing the second core according to the first number and the second number.

[0085] In this embodiment, when determining the final routing transmission path corresponding to the first core when accessing the second core according to the line congestion information on the shortest routing transmission path when the first core accesses the second core and the line congestion information on the sub-shortest routing transmission path when the first core accesses the second core, first, all core groups in the multi-core processor that are performing data transmission are determined at the current moment to obtain a first set.

[0086] In most application scenarios, the line congestion situation when the first core accesses the second core is determined based on the routing congestion situation on the special transmission path. Therefore, in this embodiment, in order to determine the line congestion situation when the first core accesses the second core, it is necessary to determine a second set according to the first set. Among them, for any element in the second set, the two cores corresponding to it are in different rows and columns of the matrix topology. By such an operation method, it is equivalent to screening out the core groups in the matrix topology that are in different rows and columns and are performing data access from the first set.

[0087] Then, determine the shortest routing transmission paths of the two cores corresponding to each element in the second set during data access to obtain a first path set, and determine the other routes in the shortest routing transmission path of the first core accessing the second core except for the routes corresponding to the first core and the second core to obtain a first route set; then, calculate the total number of times all the routes in the first route set appear in the shortest routing transmission paths corresponding to each element in the first path set to obtain a first count.

[0088] In the same way, it is possible to first determine the sub-shortest routing transmission paths of the two cores corresponding to each element in the second set during data access to obtain a second path set, and determine the other routes in the sub-shortest routing transmission path of the first core accessing the second core except for the routes corresponding to the first core and the second core to obtain a second route set; then, determine the total number of times all the routes in the second route set appear in the sub-shortest routing transmission paths corresponding to each element in the second path set to obtain a second count.

[0089] After obtaining the first count and the second count, it is equivalent to obtaining the line congestion information on the shortest routing transmission path and the sub-shortest routing transmission path for characterizing the first core accessing the second core respectively. At this time, the final routing transmission path corresponding to the first core accessing the second core can be determined according to the first count and the second count.

[0090] As a preferred implementation manner, the above step: determining the final routing transmission path corresponding to the first core accessing the second core according to the first count and the second count includes: judging whether the sum value of the first count and a first preset threshold is less than the second count; if so, determining the shortest routing transmission path of the first core accessing the second core as the final routing transmission path corresponding to the first core accessing the second core; if not, determining the sub-shortest routing transmission path of the first core accessing the second core as the final routing transmission path corresponding to the first core accessing the second core.

[0091] In this embodiment, when determining the final routing transmission path corresponding to the first core accessing the second core according to the first count and the second count, first, it is judged whether the sum value of the first count and the first preset threshold is less than the second count.

[0092] If the sum value of the first count and the first preset threshold is less than the second count, it means that the line congestion situation on the shortest routing transmission path of the first core accessing the second core is better than that on the sub-shortest routing transmission path of the first core accessing the second core. At this time, the shortest routing transmission path of the first core accessing the second core can be determined as the final routing transmission path corresponding to the first core accessing the second core.

[0093] If the sum of the first number and the first preset threshold is greater than or equal to the second number, it indicates that the line congestion situation on the sub-shortest routing transmission path when the first core accesses the second core is better than that on the shortest routing transmission path when the first core accesses the second core. At this time, the sub-shortest routing transmission path when the first core accesses the second core can be determined as the final routing transmission path corresponding to the first core when accessing the second core.

[0094] It should be noted that when setting the first preset threshold, it is based on the principle of preferentially selecting the shortest routing transmission path when the first core accesses the second core as the final routing transmission path corresponding to the first core when accessing the second core. That is, the purpose of setting the first preset threshold is to enable the multi-core processor to select the shortest routing transmission path when the first core accesses the second core with a greater probability as the final routing transmission path when the first core accesses the second core. Unless the load of routing forwarding on the shortest routing transmission path when the first core accesses the second core is too large and the delay time is too long, which will affect the overall performance of the multi-core processor, the sub-shortest routing transmission path when the first core accesses the second core will be determined as the final routing transmission path corresponding to the first core when accessing the second core.

[0095] A specific example is used to illustrate this here. Please refer to Figure 3 , when core 0 accesses core 15, its shortest routing transmission path is: route 0 → route 5 → route 10 → route 15, and the forwarding routes in its shortest routing transmission path are route 5 and route 10 (route 5 and route 10 are the elements in the first routing set). At the current moment, there are also the shortest routing transmission paths corresponding to the data access of two other core groups in the matrix topology, that is, route 2 → route 5 → route 8, and route 7 → route 10 → route 13 (route 2 → route 5 → route 8, and route 7 → route 10 → route 13 are the elements in the first path set). Then, in this case, the total number of times all the routes in the first routing set appear in the shortest routing transmission paths corresponding to each element in the first path set is 2 (the first number is 2).

[0096] When core 0 accesses core 15, its second shortest routing transmission path is: Routing 0 → Routing 1 → Routing 6 → Routing 11 → Routing 15. The forwarding routes in its second shortest routing transmission path are Routing 1, Routing 6, and Routing 11 (Routing 1, Routing 6, and Routing 11 are the elements in the second routing set). At the current moment, there are also two other core groups in the matrix topology corresponding to the second shortest routing transmission paths during data access, that is, Routing 3 → Routing 6 → Routing 9, and Routing 8 → Routing 5 → Routing 1 (Routing 3 → Routing 6 → Routing 9, and Routing 8 → Routing 5 → Routing 1 are the elements in the second path set). Then, the total number of times all the routes in the second routing set appear in the shortest routing transmission paths corresponding to each element in the second path set is 2 (the second number is 2).

[0097] Assume that the first preset threshold is 0. At this time, the first number 2 is equal to the sum of the second number 2 and the first preset threshold 0. At this time, the shortest routing transmission path Routing 0 → Routing 5 → Routing 10 → Routing 15 when core 0 accesses core 15 can be determined as the final routing transmission path corresponding to core 0 when accessing core 15.

[0098] Obviously, through the technical solution provided in this embodiment, the routing transmission path with the minimum communication delay time when the first core accesses the second core can be accurately determined.

[0099] As a preferred implementation manner, after the above step: determining the total number of times all the routes in the second routing set appear in the second shortest routing transmission paths corresponding to each element in the second path set to obtain the second number, it further includes: determining the third set according to the first set; where any two cores corresponding to an element in the third set are in the same column or the same row of the matrix topology; determining the shortest routing transmission paths when the two cores corresponding to each element in the third set access data to obtain the third path set; calculating the total number of times all the routes in the first routing set appear in the shortest routing transmission paths corresponding to each element in the third path set to obtain the third number; determining the second shortest routing transmission paths when the two cores corresponding to each element in the third set access data to obtain the fourth path set; determining the total number of times all the routes in the second routing set appear in the second shortest routing transmission paths corresponding to each element in the fourth path set to obtain the fourth number; determining the final routing transmission path corresponding to the first core when accessing the second core according to the first number, the second number, the third number, the fourth number, the first weight value, the second weight value, the third weight value, and the fourth weight value.

[0100] In this embodiment, in order to more accurately determine the final routing transmission path when the first core accesses the second core, the third set may also be determined according to the first set. Any two cores corresponding to an element in the third set are in the same column or the same row of the matrix topology. Then, the shortest routing transmission paths when the two cores corresponding to each element in the third set perform data access are determined to obtain the third path set, and the total number of times that all the routes in the first routing set appear in the shortest routing transmission paths corresponding to each element in the third path set is calculated to obtain the third number of times.

[0101] After that, the second-shortest routing transmission paths when the two cores corresponding to each element in the third set perform data access are determined to obtain the fourth path set, and the total number of times that all the routes in the second routing set appear in the second-shortest routing transmission paths corresponding to each element in the fourth path set is determined to obtain the fourth number of times.

[0102] Finally, the final routing transmission path corresponding to the first core when accessing the second core is determined according to the first number of times, the second number of times, the third number of times, the fourth number of times, the first weight value, the second weight value, the third weight value, and the fourth weight value.

[0103] As a preferred implementation manner, the above step: determining the final routing transmission path corresponding to the first core when accessing the second core according to the first number of times, the second number of times, the third number of times, the fourth number of times, the first weight value, the second weight value, the third weight value, and the fourth weight value includes: obtaining the product of the first number of times and the first weight value to obtain the first product value, and obtaining the product of the third number of times and the third weight value to obtain the third product value; adding the first product value and the third product value to obtain the first added value; obtaining the product of the second number of times and the second weight value to obtain the second product value, and obtaining the product of the fourth number of times and the fourth weight value to obtain the fourth product value; adding the second product value and the fourth product value to obtain the second added value; determining whether the sum value of the first added value and the second preset threshold is less than the second added value; if so, determining the shortest routing transmission path when the first core accesses the second core as the final routing transmission path corresponding to the first core when accessing the second core; if not, determining the second-shortest routing transmission path when the first core accesses the second core as the final routing transmission path corresponding to the first core when accessing the second core.

[0104] In this embodiment, when determining the final routing transmission path corresponding to the first core accessing the second core according to the first number, the second number, the third number, the fourth number, the first weight value, the second weight value, the third weight value, and the fourth weight value, first, the product of the first number and the first weight value is calculated to obtain a first product value, and the product of the third number and the third weight value is calculated to obtain a third product value; then, the first product value and the third product value are added together to obtain a first addition value. After that, the product of the second number and the second weight value is calculated to obtain a second product value, the product of the fourth number and the fourth weight value is calculated to obtain a fourth product value, and the second product value and the fourth product value are added together to obtain a second addition value.

[0105] Finally, it is further determined whether the sum of the first addition value and the second preset threshold is less than the second addition value. If the sum of the first addition value and the second preset threshold is less than the second addition value, the shortest routing transmission path when the first core accesses the second core is determined as the final routing transmission path corresponding to the first core accessing the second core. If the sum of the first addition value and the second preset threshold is greater than or equal to the second addition value, the second shortest routing transmission path when the first core accesses the second core is determined as the final routing transmission path corresponding to the first core accessing the second core.

[0106] A specific example is used for illustration here. Please refer to Figure 3 , when core 0 accesses core 15, its shortest routing transmission path is: route 0 → route 5 → route 10 → route 15, and the forwarding routes in its shortest routing transmission path are route 5 and route 10 (route 5 and route 10 are the elements in the first route set). At the current moment, there are also the shortest routing transmission paths corresponding to the data access of two other groups of cores in the matrix topology, that is, route 2 → route 5 → route 8, route 7 → route 10 → route 13 (route 2 → route 5 → route 8 and route 7 → route 10 → route 13 are the elements in the first path set), route 0 → route 1 → route 2 → route 3 (route 0 → route 1 → route 2 → route 3 is the element in the third path set). Then, in this case, the total number of times that all the routes in the first route set appear in the shortest routing transmission paths corresponding to the elements in the first path set is 2 (the first number is 2), and the total number of times that all the routes in the first route set appear in the shortest routing transmission paths corresponding to the elements in the third path set is 0 (the third number is 0).

[0107] When core 0 accesses core 15, its second shortest routing transmission path is: routing 0 → routing 1 → routing 6 → routing 11 → routing 15. The forwarding routes in its second shortest routing transmission path are routing 1, routing 6, and routing 11 (routing 1, routing 6, and routing 11 are the elements in the second routing set). At the current moment, there are also three other core groups in the matrix topology whose corresponding second shortest routing transmission paths when accessing data, that is, routing 3 → routing 6 → routing 9, routing 8 → routing 5 → routing 1 (routing 3 → routing 6 → routing 9, routing 8 → routing 5 → routing 1 are the elements in the second path set), and routing 1 → routing 2 → routing 3 (routing 1 → routing 2 → routing 3 is the element in the fourth path set). Then, the total number of times all the routes in the second routing set appear in the shortest routing transmission paths corresponding to each element in the second path set is 2 (the second number is 2), and the number of times all the routes in the second routing set appear in the second shortest routing transmission paths corresponding to each element in the fourth path set is 1 (the fourth number is 1).

[0108] Assume that the second preset threshold is 0 and the first weight value is and the second weight value is and the third weight value is and the fourth weight value is , since , at this time, the shortest routing transmission path of core 0 when accessing core 15: routing 0 → routing 5 → routing 10 → routing 15 can be determined as the final routing transmission path corresponding to core 0 when accessing core 15.

[0109] Obviously, through the technical solution provided by this embodiment, the final routing transmission path of the first core when accessing the second core can be accurately determined.

[0110] Based on the above embodiment, this embodiment further explains and optimizes the above technical solution. As a preferred implementation manner, after the above step: taking the shortest communication delay as the principle, determining the final routing transmission path corresponding to the first core when accessing the second core according to the shortest routing transmission path and the second shortest routing transmission path of the first core when accessing the second core, it further includes: monitoring the final routing transmission path corresponding to the first core when accessing the second core in real time, and determining whether the first core has completed the data access to the second core; if so, determining the routes connected by slashes in the final routing transmission path corresponding to the first core when accessing the second core, obtaining the diagonal routing transmission path, and turning off the physical link of the diagonal routing transmission path.

[0111] In this embodiment, after determining the final routing transmission path corresponding to the first core when accessing the second core, in order to reduce the power consumption of the multi-core processor, the final routing transmission path corresponding to the first core when accessing the second core can also be monitored in real time, and it is judged whether the first core has completed the data access to the second core. If the first core has completed the data access to the second core, the physical link between the first core and the second core is in an idle state. At this time, it is necessary to determine the routes connected by slashes in the final routing transmission path corresponding to the first core when accessing the second core, obtain the diagonal routing transmission path, and turn off the physical links on the diagonal routing transmission path.

[0112] Obviously, through the technical solution provided in this embodiment, the power consumption of the multi-core processor can be reduced.

[0113] Please refer to Figure 5 , Figure 5 , which is a hardware architecture diagram when two different cores in a multi-core processor provided in an embodiment of the present invention perform data access. Assume that the first core and the second core are two different cores in the multi-core processor. All cores in the multi-core processor form a matrix topology, and each core is connected to a router one by one. Among them, the first core and the second core are located in different rows and columns of the matrix topology.

[0114] When the first core in the multi-core processor accesses the second core, first, the access monitoring module is used to judge the data access frequency of the first core to the second core. If the data access frequency of the first core to the second core is less than or equal to the preset threshold, the XY routing module is called, and the routing algorithm is used to determine the final routing transmission path when the first core accesses the second core.

[0115] If the data access frequency of the first core to the second core is greater than the preset threshold, the multi-directional routing module is used based on the principle that the routing can transmit data in any direction, and its internal optimal route calculation unit and sub-optimal routing calculation unit are used to respectively determine the shortest routing transmission path and the sub-shortest routing transmission path when the first core accesses the second core; then, the congestion monitoring unit in the multi-directional routing module will take the shortest communication delay as the principle, and determine the final routing transmission path when the first core accesses the second core according to the shortest routing transmission path and the sub-shortest routing transmission path when the first core accesses the second core.

[0116] Finally, the link interface control module will monitor the final routing transmission path corresponding to the first core when accessing the second core in real time, and judge whether the first core has completed the data access to the second core. If the first core has completed the data access to the second core, the routing transmission path connected by slashes in the final routing transmission path corresponding to the first core when accessing the second core will be turned off to reduce the power consumption of the multi-core processor.

[0117] Through the technical solution provided by this embodiment, it is possible to solve the problems of low efficiency, long communication delay time, and poor overall performance of a multi-core processor when two cores in the multi-core processor use the routing algorithm for data access.

[0118] Please refer to Figure 6 , Figure 6 which is a structural diagram of a data routing device for a multi-core processor provided by an embodiment of the present invention. The device includes:

[0119] An access judgment module 21, configured to judge whether the first core and the second core are in different rows and columns of a matrix topology when the first core wants to perform data access on the second core; the first core and the second core are two different cores in the multi-core processor, all the cores in the multi-core processor form the matrix topology, and all the cores are respectively connected to a router in a one-to-one correspondence.

[0120] A frequency statistics module 22, configured to, when the determination result of the access judgment module is yes, count the data access frequency of the first core to the second core to obtain a target frequency.

[0121] A path calculation module 23, configured to, if the target frequency is greater than a preset frequency, respectively determine the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core based on the principle that the router can perform data transmission in any direction.

[0122] A routing determination module 24, configured to determine the final routing transmission path corresponding to the first core when accessing the second core according to the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core with the principle of the shortest communication delay.

[0123] In a specific implementation manner of the present application, it further includes: an XY routing module, configured to, when the determination result of the access judgment module is no, determine the final routing transmission path corresponding to the first core when accessing the second core according to the routing algorithm.

[0124] In a specific implementation manner of the present application, it further includes: a routing jump module, configured to, after counting the data access frequency of the first core to the second core to obtain a target frequency, if the target frequency is less than or equal to the preset frequency, continue to execute the step of determining the final routing transmission path corresponding to the first core when accessing the second core according to the routing algorithm.

[0125] In a specific embodiment of the present application, the path calculation module 23 includes: a coordinate system establishment sub-module, configured to establish a plane rectangular coordinate system corresponding to the matrix topology, and respectively determine the coordinates of the routes corresponding to the first core and the second core in the plane rectangular coordinate system to obtain a first coordinate point and a second coordinate point; a path determination sub-module, configured to respectively determine the shortest route transmission path and the sub-shortest route transmission path of the first core when accessing the second core according to the first coordinate point, the second coordinate point, the shortest route mapping table, and the sub-shortest route mapping table.

[0126] Among them, the shortest route mapping table and the sub-shortest route mapping table are established by the mapping table creation module. The mapping table creation module includes: a core screening sub-module, configured to randomly screen two cores from the multi-core processor to obtain a third core and a fourth core, and respectively determine the coordinates of the routes corresponding to the third core and the fourth core in the plane rectangular coordinate system to obtain a third coordinate point and a fourth coordinate point; the third core and the fourth core are in different rows and columns of the matrix topology; a shortest path determination sub-module, configured to determine the shortest route transmission path of the third core when accessing the fourth core on the principle of first performing data transmission along the routes in the diagonal direction of the third coordinate point and the fourth coordinate point, and then performing data transmission along the routes in the X-axis direction or the Y-axis direction; a first mapping table determination sub-module, configured to determine the shortest route transmission paths corresponding to any two cores in different rows and columns of the matrix topology when performing data access according to the shortest route transmission path of the third core when accessing the fourth core, and create the shortest route mapping table according to the shortest route transmission paths corresponding to any two cores in different rows and columns of the matrix topology when performing data access; a sub-shortest path determination sub-module, configured to add 1 to the abscissa or ordinate of the third coordinate point to obtain a fifth coordinate point, and determine the sub-shortest route transmission path of the third core when accessing the fourth core on the principle of first performing data transmission along the routes in the diagonal direction of the fifth coordinate point and the fourth coordinate point, and then performing data transmission along the routes in the X-axis direction or the Y-axis direction; a second mapping table determination sub-module, configured to determine the sub-shortest route transmission paths corresponding to any two cores in different rows and columns of the matrix topology when performing data access according to the sub-shortest route transmission path of the third core when accessing the fourth core, and create the sub-shortest route mapping table according to the sub-shortest route transmission paths corresponding to any two cores in different rows and columns of the matrix topology when performing data access.

[0127] In a specific embodiment of the present application, the shortest path determination sub-module includes: a routing judgment unit for judging whether the routes in the diagonal direction between the third coordinate point and the fourth coordinate point are all on the same straight line; a first determination unit for, when the determination result of the routing judgment unit is yes, determining the routing transmission path in the diagonal direction between the third coordinate point and the fourth coordinate point as the shortest routing transmission path when the third core accesses the fourth core; a second determination unit for, when the determination result of the routing judgment unit is no, determining a coordinate point with the same abscissa as the fourth coordinate point in the diagonal direction between the third coordinate point and the fourth coordinate point to obtain a first intermediate coordinate point, and determining a coordinate point with the same ordinate as the fourth coordinate point in the diagonal direction between the third coordinate point and the fourth coordinate point to obtain a second intermediate coordinate point; a first value determination unit for determining the number of routing forwards passed by the third core when accessing the fourth core in accordance with the principle of first transmitting data along the connection line between the third coordinate point and the first intermediate coordinate point to reach the first intermediate coordinate point, and then transmitting data along the Y-axis direction to reach the fourth coordinate point, to obtain a first value; a second value determination unit for determining the number of routing forwards passed by the third core when accessing the fourth core in accordance with the principle of first transmitting data along the connection line between the third coordinate point and the second intermediate coordinate point to reach the second intermediate coordinate point, and then transmitting data along the X-axis direction to reach the fourth coordinate point, to obtain a second value; a value judgment unit for judging whether the first value is less than the second value; a first path determination unit for, when the determination result of the value judgment unit is yes, determining the routing transmission path of first transmitting data along the connection line between the third coordinate point and the first intermediate coordinate point to reach the first intermediate coordinate point, and then transmitting data along the Y-axis direction to reach the fourth coordinate point as the shortest routing transmission path when the third core accesses the fourth core.

[0128] In a specific embodiment of the present application, it further includes: a second path judgment unit for, when the determination result of the value judgment unit is no, determining the routing transmission path of first transmitting data along the connection line between the third coordinate point and the second intermediate coordinate point to reach the second intermediate coordinate point, and then transmitting data along the X-axis direction to reach the fourth coordinate point as the shortest routing transmission path when the third core accesses the fourth core.

[0129] In a specific embodiment of the present application, the routing determination module 24 includes: a routing determination sub-module, configured to determine the final routing transmission path corresponding to the first core when accessing the second core according to the line congestion information on the shortest routing transmission path when the first core accesses the second core, and the line congestion information on the sub-shortest routing transmission path when the first core accesses the second core.

[0130] In a specific embodiment of the present application, the routing determination sub-module includes: a first set determination unit, configured to determine all core groups in the multi-core processor that are performing data transmission at the current moment to obtain a first set; a second set determination unit, configured to determine a second set according to the first set; wherein, the two cores corresponding to any element in the second set are in different rows and columns of the matrix topology; a first path set determination unit, configured to determine the shortest routing transmission paths of the two cores corresponding to each element in the second set when performing data access to obtain a first path set; a first routing set determination unit, configured to determine the other routes except the routes corresponding to the first core and the second core in the shortest routing transmission path when the first core accesses the second core to obtain a first routing set; a first number determination unit, configured to calculate the total number of times that all the routes in the first routing set appear in the shortest routing transmission paths corresponding to each element in the first path set to obtain a first number; a second path set determination unit, configured to determine the sub-shortest routing transmission paths of the two cores corresponding to each element in the second set when performing data access to obtain a second path set; a second routing set determination unit, configured to determine the other routes except the routes corresponding to the first core and the second core in the sub-shortest routing transmission path when the first core accesses the second core to obtain a second routing set; a second number determination unit, configured to determine the total number of times that all the routes in the second routing set appear in the sub-shortest routing transmission paths corresponding to each element in the second path set to obtain a second number; a path determination unit, configured to determine the final routing transmission path corresponding to the first core when accessing the second core according to the first number and the second number.

[0131] In a specific embodiment of the present application, the path determination unit includes: a sum value judgment sub-unit, configured to judge whether the sum value of the first number and a first preset threshold is less than the second number; a first path determination unit, configured to, when the determination result of the sum value judgment sub-unit is yes, determine the shortest routing transmission path when the first core accesses the second core as the final routing transmission path corresponding to the first core when accessing the second core; a second path determination unit, configured to, when the determination result of the sum value judgment sub-unit is no, determine the second shortest routing transmission path when the first core is at the second core as the final routing transmission path corresponding to the first core when accessing the second core.

[0132] In a specific embodiment of the present application, it further includes: a threshold setting unit, configured to set the first preset threshold on the principle of preferentially selecting the shortest routing transmission path when the first core accesses the second core as the final routing transmission path corresponding to the first core when accessing the second core.

[0133] In a specific embodiment of the present application, it further includes: a third set determination unit, configured to, after determining the total number of times that all the routes in the second routing set appear in the second shortest routing transmission paths corresponding to each element in the second path set to obtain the second number, determine a third set according to the first set; wherein, for any element in the third set, the two cores corresponding to it are in the same column or the same row of the matrix topology; a third path set determination unit, configured to determine the shortest routing transmission paths when the two cores corresponding to each element in the third set perform data access to obtain a third path set; a third number determination unit, configured to calculate the total number of times that all the routes in the first routing set appear in the shortest routing transmission paths corresponding to each element in the third path set to obtain a third number; a fourth path set determination unit, configured to determine the second shortest routing transmission paths when the two cores corresponding to each element in the third set perform data access to obtain a fourth path set; a fourth number determination unit, configured to determine the total number of times that all the routes in the second routing set appear in the second shortest routing transmission paths corresponding to each element in the fourth path set to obtain a fourth number; a transmission path determination unit, configured to determine the final routing transmission path corresponding to the first core when accessing the second core according to the first number, the second number, the third number, the fourth number, a first weight value, a second weight value, a third weight value, and a fourth weight value.

[0134] In a specific embodiment of the present application, the transmission path determination unit includes: a first multiplication subunit, configured to calculate the product of the first number and the first weight value to obtain a first product value, and calculate the product of the third number and the third weight value to obtain a third product value; a first addition subunit, configured to add the first product value and the third product value to obtain a first addition value; a second multiplication subunit, configured to calculate the product of the second number and the second weight value to obtain a second product value, and calculate the product of the fourth number and the fourth weight value to obtain a fourth product value; a second addition subunit, configured to add the second product value and the fourth product value to obtain a second addition value; an addition value judgment subunit, configured to judge whether the sum of the first addition value and a second preset threshold is less than the second addition value; a first routing determination subunit, configured to, when the determination result of the addition value judgment subunit is yes, determine the shortest routing transmission path when the first core accesses the second core as the final routing transmission path corresponding to the first core when accessing the second core; a second routing determination subunit, configured to, when the determination result of the addition value judgment subunit is no, determine the sub-shortest routing transmission path when the first core accesses the second core as the final routing transmission path corresponding to the first core when accessing the second core.

[0135] The data routing device of a multi-core processor provided by an embodiment of the present invention has the beneficial effects of the data routing method of a multi-core processor disclosed above.

[0136] Please refer to Figure 7 , Figure 7 FIG. is a structural diagram of a data routing device of a multi-core processor provided by an embodiment of the present invention. The device includes: a memory 31, configured to store a computer program; a processor 32, configured to execute the computer program to implement the steps of the data routing method of a multi-core processor disclosed above.

[0137] The data routing device of the multi-core processor provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, or a desktop computer, etc. Among them, the processor 32 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 32 may be implemented in at least one hardware form of digital signal processing , field programmable gate array , programmable logic array Among them. The processor 32 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake state, also called a central processing unit; the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 32 may be integrated with an image processor , Responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 32 may further include an artificial intelligence processor, which is used to process computational operations related to machine learning.

[0138] The memory 31 may include one or more computer-readable storage media, which may be non-transitory. The memory 31 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory 31 is at least used to store the following computer program 301. After the computer program is loaded and executed by the processor 32, it can implement the relevant steps of a data routing method for a multi-core processor disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 31 may also include an operating system 302 and data 303, etc., and the storage method may be transient storage or permanent storage. Among them, the operating system 302 may include , , , etc. The data 303 may include, but is not limited to, the data involved in the data routing method of the multi-core processor.

[0139] In some embodiments, the data routing device of the multi-core processor may further include a display screen 33, an input / output interface 34, a communication interface 35, a power supply 36, and a communication bus 37.

[0140] Those skilled in the art can understand that Figure 7 the structure shown in

[0141] does not constitute a limitation on the data routing device of the multi-core processor, and may include more or fewer components than those shown in the figure. , random access memory , electrically erasable programmable , registers, hard disks, removable disks,

[0142] A data routing device for a multi-core processor provided by an embodiment of the present invention has the beneficial effects of a data routing method for a multi-core processor disclosed above.

[0143] Correspondingly, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of a data routing method for a multi-core processor disclosed above are implemented.

[0144] A computer-readable storage medium provided by an embodiment of the present invention has the beneficial effects of a data routing method for a multi-core processor disclosed above.

[0145] Correspondingly, an embodiment of the present invention further provides a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of a data routing method for a multi-core processor disclosed above are implemented.

[0146] A computer program product provided by an embodiment of the present invention has the beneficial effects of a data routing method for a multi-core processor disclosed above.

[0147] The embodiments in the specification are described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method part.

[0148] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0149] The above has introduced in detail a data routing method, device, equipment, medium and computer program product of a multi-core processor provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art of this technology, without departing from the principle of the present invention, several improvements and modifications can still be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A data routing method for a multi-core processor, characterized in that: include: When the first core wants to access data from the second core, it is determined whether the first core and the second core are in different rows and columns of the matrix topology; the first core and the second core are two different cores in a multi-core processor, all cores in the multi-core processor form the matrix topology, and all cores are connected to a route in a one-to-one correspondence; If yes, then counting the data access frequency of the first core to the second core to obtain a target frequency; If the target frequency is greater than the preset frequency, based on the principle that routing can transmit data in any direction, respectively determining the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core; Based on the principle of shortest communication delay, a final routing transmission path corresponding to the first core when accessing the second core is determined according to the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core.

2. The data routing method of a multi-core processor according to claim 1, characterized in that: After determining whether the first core and the second core are in different rows and columns of the matrix topology, the method further includes: If not, then according to The routing algorithm determines a final routing transmission path corresponding to the first core when accessing the second core.

3. The data routing method of a multi-core processor according to claim 2, characterized in that: After counting the data access frequency of the first core to the second core to obtain the target frequency, the method further includes: If the target frequency is less than or equal to the preset frequency, continue to execute the The routing algorithm determines the final routing transmission path corresponding to the first core when accessing the second core.

4. The data routing method of a multi-core processor according to claim 1, characterized in that: The method of determining the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core based on the principle that routing can perform data transmission in any direction includes: Establishing a plane rectangular coordinate system corresponding to the matrix topology, and respectively determining the coordinates of the routes corresponding to the first core and the second core in the plane rectangular coordinate system to obtain a first coordinate point and a second coordinate point; Determine respectively the shortest route transmission path and the second shortest route transmission path when the first core accesses the second core according to the first coordinate point, the second coordinate point, the shortest route mapping table, and the second shortest route mapping table; The process of creating the shortest route mapping table and the second shortest route mapping table includes: Randomly selecting two cores from the multi-core processor to obtain a third core and a fourth core, and respectively determining the coordinates of the routes corresponding to the third core and the fourth core in the plane rectangular coordinate system to obtain a third coordinate point and a fourth coordinate point; the third core and the fourth core are in different rows and columns of the matrix topology; Determine the shortest route transmission path when the third core accesses the fourth core based on the principle of first transmitting data along the route in the diagonal direction of the third coordinate point and the fourth coordinate point and then transmitting data along the route in the X-axis direction or the Y-axis direction; Determining the shortest route transmission path corresponding to any two cores in different rows and columns in the matrix topology when performing data access according to the shortest route transmission path when the third core accesses the fourth core, and creating the shortest route mapping table according to the shortest route transmission path corresponding to any two cores in different rows and columns in the matrix topology when performing data access; Add 1 to the abscissa or ordinate of the third coordinate point to obtain a fifth coordinate point, and determine the second shortest routing transmission path when the third core accesses the fourth core based on the principle of first transmitting data along a route in a diagonal direction between the fifth coordinate point and the fourth coordinate point and then transmitting data along a route in an X-axis direction or a Y-axis direction; The second shortest route transmission path corresponding to any two cores in different rows and columns in the matrix topology when accessing data is determined according to the second shortest route transmission path when the third core accesses the fourth core, and the second shortest route mapping table is created according to the second shortest route transmission path corresponding to any two cores in different rows and columns in the matrix topology when accessing data.

5. The data routing method of a multi-core processor according to claim 4, characterized in that: The method of determining the shortest route transmission path when the third core accesses the fourth core based on the principle of first transmitting data along a route in a diagonal direction between the third coordinate point and the fourth coordinate point and then transmitting data along a route in an X-axis direction or a Y-axis direction includes: Determine whether the routes in the diagonal direction of the third coordinate point and the fourth coordinate point are both on the same straight line; If yes, determining the routing transmission path in the diagonal direction between the third coordinate point and the fourth coordinate point as the shortest routing transmission path when the third core accesses the fourth core; If not, a coordinate point having the same horizontal coordinate as the fourth coordinate point is determined in the diagonal direction between the third coordinate point and the fourth coordinate point to obtain a first intermediate coordinate point, and a coordinate point having the same vertical coordinate as the fourth coordinate point is determined in the diagonal direction between the third coordinate point and the fourth coordinate point to obtain a second intermediate coordinate point; Based on the principle of first transmitting data along the connection line between the third coordinate point and the first intermediate coordinate point to reach the first intermediate coordinate point, and then transmitting data along the Y-axis direction to reach the fourth coordinate point, determining the number of routing forwardings that the third core passes through when accessing the fourth core, and obtaining a first value; Based on the principle of first transmitting data along the connection line between the third coordinate point and the second intermediate coordinate point to reach the second intermediate coordinate point, and then transmitting data along the X-axis direction to reach the fourth coordinate point, the number of routing forwardings that the third core passes through when accessing the fourth core is determined to obtain a second value; Determine whether the first value is less than the second value; If so, the routing transmission path that first transmits data along the connecting line between the third coordinate point and the first intermediate coordinate point to reach the first intermediate coordinate point and then transmits data along the Y-axis direction to reach the fourth coordinate point will be determined as the shortest routing transmission path for the third core when accessing the fourth core.

6. The data routing method of a multi-core processor according to claim 5, characterized in that: After determining whether the first value is less than the second value, the method further includes: If not, the routing transmission path that first transmits data along the connecting line between the third coordinate point and the second intermediate coordinate point to reach the second intermediate coordinate point and then transmits data along the X-axis direction to reach the fourth coordinate point will be determined as the shortest routing transmission path for the third core when accessing the fourth core.

7. The data routing method of a multi-core processor according to claim 1, characterized in that: The method of determining the final routing transmission path corresponding to the first core when accessing the second core based on the shortest routing transmission path and the second shortest routing transmission path when the first core accesses the second core based on the principle of shortest communication delay includes: The final routing transmission path corresponding to the first core when accessing the second core is determined based on the line congestion information on the shortest routing transmission path when the first core accesses the second core, and the line congestion information on the second shortest routing transmission path when the first core accesses the second core.

8. The data routing method of a multi-core processor according to claim 7, characterized in that: The determining, according to the line congestion information on the shortest routing transmission path when the first core accesses the second core, and the line congestion information on the second shortest routing transmission path when the first core accesses the second core, a final routing transmission path corresponding to the first core when accessing the second core includes: At the current moment, all core groups in the multi-core processor that are performing data transmission are determined to obtain a first set; Determine a second set according to the first set; wherein two cores corresponding to any one element in the second set are in different rows and columns of the matrix topology; Determine the shortest routing transmission path between two cores corresponding to each element in the second set when accessing data, and obtain a first path set; Determine other routes except routes corresponding to the first core and the second core in the shortest route transmission path when the first core accesses the second core, and obtain a first route set; Calculate the total number of times all routes in the first route set appear in the shortest route transmission path corresponding to each element in the first path set to obtain the first number; Determine the second shortest routing transmission path when two cores corresponding to each element in the second set perform data access, and obtain a second path set; Determine other routes except the routes corresponding to the first core and the second core in the second shortest route transmission path when the first core accesses the second core, to obtain a second route set; Determine the total number of times all routes in the second route set appear in the second shortest route transmission path corresponding to each element in the second path set, and obtain a second number; A final routing transmission path corresponding to when the first core accesses the second core is determined according to the first number of times and the second number of times.

9. The data routing method of a multi-core processor according to claim 8, characterized in that: The determining, according to the first number of times and the second number of times, a final routing transmission path corresponding to when the first core accesses the second core includes: Determine whether the sum of the first number of times and a first preset threshold is less than the second number of times; If yes, then determining the shortest routing transmission path when the first core accesses the second core as the final routing transmission path corresponding to the first core when accessing the second core; If not, the second shortest routing transmission path of the first core when accessing the second core is determined as the final routing transmission path corresponding to the first core when accessing the second core.

10. The data routing method of a multi-core processor according to claim 9, characterized in that: Also includes: The first preset threshold is set based on the principle of preferentially selecting the shortest routing transmission path when the first core accesses the second core as the final routing transmission path corresponding to the first core when the first core accesses the second core.

11. The data routing method of a multi-core processor according to claim 8, characterized in that: The determining of the total number of times all routes in the second route set appear in the second shortest route transmission path corresponding to each element in the second path set, after obtaining the second number, further includes: Determine a third set according to the first set; wherein two cores corresponding to any one element in the third set are in the same column or the same row of the matrix topology; Determine the shortest routing transmission path between two cores corresponding to each element in the third set when accessing data, and obtain a third path set; Calculate the total number of times all routes in the first route set appear in the shortest route transmission path corresponding to each element in the third path set to obtain a third number; Determine the second shortest routing transmission path when two cores corresponding to each element in the third set perform data access, and obtain a fourth path set; Determine the total number of times that all routes in the second route set appear in the second shortest route transmission path corresponding to each element in the fourth path set, to obtain a fourth number; A final routing transmission path corresponding to the first core when accessing the second core is determined according to the first number, the second number, the third number, the fourth number, the first weight value, the second weight value, the third weight value and the fourth weight value.

12. The data routing method of a multi-core processor according to claim 11, characterized in that: The determining, according to the first number, the second number, the third number, the fourth number, the first weight value, the second weight value, the third weight value and the fourth weight value, a final routing transmission path corresponding to when the first core accesses the second core comprises: Calculate the product of the first number of times and the first weight value to obtain a first product value, and calculate the product of the third number of times and the third weight value to obtain a third product value; Adding the first product value and the third product value to obtain a first added value; Calculate the product of the second number of times and the second weight value to obtain a second product value, and calculate the product of the fourth number of times and the fourth weight value to obtain a fourth product value; Adding the second product value and the fourth product value to obtain a second added value; Determine whether the sum of the first added value and the second preset threshold is less than the second added value; If yes, then determining the shortest routing transmission path when the first core accesses the second core as the final routing transmission path corresponding to the first core when accessing the second core; If not, the second shortest routing transmission path when the first core accesses the second core is determined as the final routing transmission path corresponding to the first core when the first core accesses the second core.

13. A data routing device for a multi-core processor, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of a data routing method for a multi-core processor as claimed in any one of claims 1 to 12.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data routing method for a multi-core processor as claimed in any one of claims 1 to 12 are implemented.

15. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the data routing method for a multi-core processor as claimed in any one of claims 1 to 12 are implemented.

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