DRAM-PIM accelerator design method based on data similarity

Abstract

The invention relates to a DRAM-PIM accelerator design method based on data similarity. The method is applied to neural network calculation, the DRAM-PIM accelerator design method is applied to a storage and calculation integrated system, the storage and calculation integrated system comprises a storage array, a preprocessing unit and a calculation unit, and the method comprises the following steps: reading a plurality of pieces of data to be processed from the storage array to the preprocessing unit, determining reference data based on each piece of data to be processed, each piece of data to be processed is physically and continuously stored in the storage array; in the preprocessing unit, performing XOR processing on the reference data and the to-be-processed data to obtain multiple pieces of target data; and reading the reference data and the target data to a calculation unit to perform data calculation. By adopting the method, the energy efficiency of the storage and calculation integrated system can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of in-memory computing technology, and in particular to a DRAM-PIM accelerator design method based on data similarity. Background Art

[0002] With the widespread application of artificial intelligence, algorithm parameters are growing exponentially, resulting in large-scale data movement. It can be seen that the computing architecture has increasing requirements for storage bandwidth.

[0003] In the prior art, there has emerged a storage-computing integrated system. In the deep neural network processor of the storage-computing integrated system, weight data can directly participate in multiplication and addition operations without going through the traditional reading process, and the multiplication and addition results can be output instantly. This reduces the frequent bus interactions between the central processing unit and the memory circuit, and greatly reduces the total amount of data movement.

[0004] However, the ratio of actual computing power to actual power consumption in existing storage-computing integrated systems is low, that is, the energy efficiency of the storage-computing integrated systems is low. Summary of the invention

[0005] Based on this, it is necessary to provide a DRAM-PIM accelerator design method based on data similarity that can effectively improve the energy efficiency of the storage and computing integrated system in response to the above technical problems.

[0006] In a first aspect, the present application provides a DRAM-PIM accelerator design method based on data similarity, which is used in neural network calculations. The DRAM-PIM accelerator design method is used in a storage-computing integrated system, which includes a storage array, a preprocessing unit, and a computing unit, including:

[0007] Reading a plurality of to-be-processed data from a storage array to a pre-processing unit, and determining a reference data based on each to-be-processed data, wherein each to-be-processed data is physically and continuously stored in the storage array;

[0008] In the preprocessing unit, the reference data and each data to be processed are subjected to XOR processing to obtain a plurality of target data;

[0009] The reference data and each target data are read into the calculation unit to perform data calculation.

[0010] In one embodiment, the multiple data to be processed are input image data, and the data calculation includes multiplication and addition operations on the reference data and the weight data corresponding to the reference data, and multiplication and addition operations on each target data and the weight data corresponding to each target data, and each weight data is stored in a storage array.

[0011] In one embodiment, the storage array is a dynamic random access memory array, and a plurality of to-be-processed data are read from the storage array to the pre-processing unit, and the benchmark data is determined based on each to-be-processed data, including:

[0012] A complete row of data to be processed in the storage array is read to the preprocessing unit through multiple read cycles; the data to be processed read in the first read cycle among the data to be processed is determined as the reference data, and the amount of data to be processed read in the first read cycle is related to the output bit width of the storage array.

[0013] In one embodiment, a complete row of to-be-processed data in a storage array is read to a pre-processing unit through multiple read cycles, including:

[0014] A complete row of data to be processed in the storage array is read into the row cache; and the data to be processed is read from the row cache to the pre-processing unit through multiple read cycles according to the selection unit.

[0015] In one embodiment, the reference data and each target data are read into a calculation unit to perform data calculation, including:

[0016] Determine the calculation results of the benchmark data and each target data; and add the calculation results of the benchmark data to the calculation results of each target data to obtain the data processing results of each data to be processed.

[0017] In a second aspect, the present application further provides a storage-computing integrated system for use in neural network calculations, the storage-computing integrated system comprising:

[0018] A storage array, the storage array is used to store a plurality of data to be processed, each of which is physically and continuously stored in the storage array;

[0019] A preprocessing unit, the preprocessing unit is used to read each to-be-processed data from the storage array, determine the reference data based on each to-be-processed data, perform XOR processing on the reference data and each to-be-processed data to obtain a plurality of target data, and read the reference data and each target data into the calculation unit;

[0020] The calculation unit is used to perform data calculation according to the reference data and each target data.

[0021] In one of the embodiments, when the storage-computing integrated system reads binary data, if the binary data is '1', a short circuit path exists in the storage-computing integrated system, which generates additional reading power consumption.

[0022] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, any of the methods described in the first aspect is implemented.

[0023] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the methods described in the first aspect above.

[0024] In a fifth aspect, the present application further provides a computer program product, including a computer program, which, when executed by a processor, implements any of the methods described in the first aspect above.

[0025] The above-mentioned DRAM-PIM accelerator design method based on data similarity is to read multiple data to be processed from the storage array to the preprocessing unit, and determine the benchmark data based on each of the data to be processed, and each of the data to be processed is physically stored continuously in the storage array; then, in the preprocessing unit, the benchmark data and each of the data to be processed are XORed to obtain multiple target data; finally, the benchmark data and each of the target data are read to the computing unit for data calculation. In this way, by obtaining the benchmark data from the data to be processed and XORing the benchmark data and the data to be processed respectively, the target data with higher sparsity can be obtained. Compared with directly reading and calculating the data to be processed, reading the target data with higher sparsity and calculating the target data can effectively reduce power consumption and improve the energy efficiency of the storage and computing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 This is a diagram of the integrated storage and computing architecture based on HBM-DRAM;

[0028] Figure 2 This is a diagram of the storage-computing integrated architecture based on HMC;

[0029] Figure 3 A schematic diagram of the structure of a storage-in-one system in one embodiment;

[0030] Figure 4 A schematic diagram of a flow chart of a DRAM-PIM accelerator design method in one embodiment;

[0031] Figure 5 A schematic diagram of data reading of a storage-computing integrated system in one embodiment;

[0032] Figure 6 A schematic diagram of a flow chart of a step of determining benchmark data in one embodiment;

[0033] Figure 7 It is a schematic diagram of a flow chart of reading the data to be processed into the pre-processing unit in one embodiment;

[0034] Figure 8 It is a structural schematic diagram of a storage-in-one system in another embodiment;

[0035] Fig. 9 A schematic diagram of a flow chart of a data calculation step in an embodiment;

[0036] Fig.10 A schematic diagram of a flow chart of a DRAM-PIM accelerator design method in another embodiment;

[0037] Fig.11 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0039] With the widespread application of artificial intelligence, algorithm parameters have shown an exponential growth, resulting in large-scale data movement. It can be seen that the computing architecture has an increasing demand for storage bandwidth. In the traditional deep neural network processor based on the von Neumann architecture, the data processing flow involves two key steps: first, both input data (i.e. activation data) and weight data need to be stored in the corresponding memory unit in advance; then, these data are transmitted to the digital operation unit through the bus to perform multiply-accumulate (MAC) operations. However, due to the limitation of the number of memory read interfaces, the read bandwidth of weight data is relatively low, that is, the number of weights that can be read in a unit cycle is limited, which directly restricts the rate of MAC operations, thereby significantly affecting the throughput of the entire system.

[0040] In the prior art, a storage-computing integrated system has emerged that can overcome this limitation of the von Neumann architecture. The architecture not only maintains the basic storage and read-write functions of the storage circuit, but also integrates logical or multiplication-addition computing capabilities. This design significantly reduces the frequent bus interactions between the central processing unit and the memory circuit, greatly reduces the total amount of data migration, and thus significantly improves the energy efficiency of the system. In the deep neural network processor of the storage-computing integrated system, the weight data can directly participate in the multiplication-addition operation without going through the traditional reading process, and the multiplication-addition results can be output instantly. In this way, the frequent bus interactions between the central processing unit and the memory circuit are reduced, and the total amount of data movement is greatly reduced.

[0041] Since analog domain computing circuits have low calculation accuracy and are easily affected by working conditions such as process temperature and voltage, digital logic is often used to complete the corresponding calculations. The digital domain calculation method has the high precision characteristics of traditional digital circuit design. The calculation results are not affected by process, voltage, and temperature (PVT), and there is no need to introduce digital-to-analog conversion units. In the digital computing mode, the data in the entire bank is read out to the computing unit through the local bus, and the calculation of storage data and input data is completed inside the dynamic random access memory (DRAM) unit, avoiding the long-distance data movement of reading the storage data out of DRAM. In 2021, Samsung proposed a storage-computing integrated architecture (High Bandwidth Memory-Processing-In-Memory, HBM-PIM) based on a 3D stacking process for high-performance dynamic random access memory (High Bandwidth Memory DRAM, HBM-DRAM) at the top integrated circuit conference ISSCC. This is also the first storage-computing integrated architecture based on HBM-DRAM, such as Figure 1 As shown in the figure below, HBM-PIM utilizes the multi-layer structure of HBM-DRAM. The left side of the figure below shows the basic structure of HBM-PIM. Two entire banks share a set of sense amplifier structures (Sense Amplifier, SA). HBM-PIM embeds computing units in each layer of DRAM, such as Figure 1 As shown on the right side of the diagram, every two banks share one computing unit. The data inside the bank is read out to the computing unit through the local bus, and the calculation of the stored data and the input data is completed internally, avoiding the long-distance data movement of reading the stored data out of DRAM.

[0042] like Figure 2As shown in the figure, iPIM, an integrated storage and computing architecture based on HMC, is jointly proposed by UCSB and Alibaba. iPIM proposes a lightweight programmable near memory architecture. It can support large-scale parallel computing by using the 3D integrated architecture of HMC, and provides complete instructions and compilation systems to support flexible mapping of different tasks.

[0043] However, Figure 1 In the integrated storage and computing architecture shown in the figure, HBM-PIM embeds the computing unit between two banks, which needs to be implemented using DRAM technology. Since DRAM technology is relatively backward compared to complementary metal oxide semiconductor (CMOS) technology, only three layers of metal can be used for layout. This results in a large area overhead. Therefore, the high-computing DRAM integrated storage and computing architecture exchanges computing unit design at the expense of storage capacity. Figure 2 In the integrated storage and computing architecture shown in , the flexible instruction design introduces a large area and power consumption overhead, reducing the energy efficiency of the system. That is, the ratio of actual computing power to actual power consumption in the existing integrated storage and computing system is low, and the energy efficiency of the integrated storage and computing system is low.

[0044] In view of this, it is necessary to propose a DRAM-PIM accelerator design method based on data similarity that can effectively improve the energy efficiency of the storage-computing integrated system. The DRAM-PIM accelerator design method provided in the embodiment of the present application is used in neural network calculations and can be applied to Figure 3 The storage and computing integrated system 30 shown. The storage and computing integrated system includes a storage array 31, a preprocessing unit 32 and a computing unit 33. The storage array 31 is used to store a plurality of data to be processed, and each data to be processed is physically stored continuously in the storage array 31; the preprocessing unit 32 is used to read each data to be processed from the storage array 31, determine the reference data based on each data to be processed, and perform XOR processing on the reference data and each data to be processed to obtain a plurality of target data, and read the reference data and each target data into the computing unit 33; the computing unit 33 is used to perform data calculation according to the reference data and each target data.

[0045] Alternatively, DRAM-PIM (Dynamic Random Access Memory-Processing-In-Memory) can optimize data processing speed and efficiency by integrating processing functions directly in dynamic random access memory (DRAM) chips.

[0046] In an exemplary embodiment, Figure 4As shown in FIG. 1 , a DRAM-PIM accelerator design method based on data similarity is provided for neural network computing. The method is applied to Figure 3 The storage and computing integrated system in FIG. 1 is taken as an example to illustrate, including the following steps 401 to 403. Among them:

[0047] S401, reading a plurality of to-be-processed data from a storage array to a pre-processing unit, and determining reference data based on each to-be-processed data.

[0048] The data to be processed are physically stored continuously in the storage array.

[0049] Optionally, the multiple data to be processed may be stored in a storage array in the form of rows and columns, and the multiple data to be processed may be input data for neural network calculation.

[0050] Optionally, the storage array may be a DRAM array, which may be composed of a plurality of storage cells, which are organized in rows and columns to facilitate fast access and writing of data. The processor may access a specific storage cell in the DRAM array by sending a row address and a column address.

[0051] Optionally, a pre-processing unit may be added at the periphery of the storage array, so that a plurality of to-be-processed data may be read from the storage array to the pre-processing unit.

[0052] Optionally, multiple data to be processed may be read from the storage array to the preprocessing unit separately and in sequence, or a whole row of data may be read from the storage array to the preprocessing unit in the form of rows until all the data to be processed in the storage array are read to the preprocessing unit, or a whole column of data may be read from the storage array to the preprocessing unit in the form of columns until all the data to be processed in the storage array are read to the preprocessing unit. The embodiments of the present application do not limit the manner in which the data to be processed is read from the storage array to the preprocessing unit.

[0053] Optionally, starting data among multiple data to be processed may be used as reference data. The reference data may be one or more, which is not limited in the embodiments of the present application.

[0054] S402, in a pre-processing unit, performing XOR processing on the reference data and each data to be processed to obtain a plurality of target data.

[0055] Optional, such as Figure 5 As shown in the figure, it is a schematic diagram of data reading of the storage and computing integrated system. In the process of data reading, when reading binary '0', there is a path 1, that is, there is an output drive unit through the resistor R C1When the output driver unit reaches the capacitor path Cc, it will charge the capacitor. When the binary value is '1', there is path 2, passing through R T , R C2 , R C1 and NMOS tube, NMOS tube is turned on, R T , R C2 , R C1 The resistance is very small, and there is a short-circuit path from the buffer to the output driver unit GND. At this time, a large current will be introduced, generating additional reading power consumption. According to experimental statistics, reading '1' consumes 37% more energy than reading '0'.

[0056] Optionally, after the data to be processed are read into the preprocessing unit, the reference data and each data to be processed may be XOR processed in the preprocessing unit to obtain a plurality of target data corresponding one-to-one to each data to be processed.

[0057] Optionally, the data to be processed may be data from two adjacent images input into a neural network calculation, or data from adjacent areas of the same image. The similarity between the data to be processed satisfies a preset similarity threshold, and the similarity is very high. If the data to be processed are all read directly from the DRAM, relatively similar and redundant data will appear in the data reading path. Therefore, the similarity between the low-bit width data of the data to be processed may be utilized to increase the sparsity of the data in the reading path, that is, the number of bits 0 in the data, and to reduce the reading power consumption by reading as many '0's as possible.

[0058] Optionally, since the benchmark data is one or more of the processed data, it can be understood that the multiple target data may include the target data after the benchmark data is XORed with itself (that is, all are 0), or may not include the target data corresponding to the benchmark data. That is to say, when XORing is performed in the preprocessing unit, the benchmark data may be XORed with itself, or may skip and be XORed directly with the remaining data to be processed that is read later. The embodiments of the present application are not limited to this.

[0059] Taking the data to be processed including 0x795A8058, 0x795A7196, and 0x795A3023 as an example, the method in the above step 402 is explained. The starting data 0x795A8058 can be used as the reference data. After the remaining data to be processed is XORed with the reference data, the target data 0x0000F1CE and 0X0000B07B can be obtained. Compared with the data to be processed, the reading power consumption is greatly saved when reading the target data.

[0060] Optionally, the above-mentioned XOR process is described, the hexadecimal data to be processed is converted into binary data, and then bitwise XOR is performed. The binary data corresponding to the benchmark data is 0111 1001 0101 1010 1000 0000 01011000, and the binary data corresponding to the data to be processed 0x795A7196 is 0111 1001 0101 1010 0111 0001 10010110. After XOR, 0000 0000 0000 0000 1111 0001 1100 1110 is obtained. After converting the data into hexadecimal, it is 0x0000F1CE.

[0061] S403, reading the reference data and each target data into a calculation unit to perform data calculation.

[0062] Optionally, the reference data and each target data may be read into a calculation unit, and data calculation may be performed in the calculation unit.

[0063] Optionally, since the DRAM-PIM accelerator design method based on data similarity is used in neural network calculations, the benchmark data and each target data and the corresponding weight data can be calculated in the calculation unit, and the multiplication and addition operation is the core calculation process of the neural network calculation. It can be understood that the data calculation in the calculation unit can include multiplication and addition operations on the benchmark data and each target data and the corresponding weight data, and then the data processing results of each data to be processed can be obtained according to the calculation results.

[0064] Optionally, the multiple data to be processed are input image data, and the data calculation includes multiplication and addition operations on the benchmark data and the weight data corresponding to the benchmark data, and multiplication and addition operations on each target data and the weight data corresponding to each target data, and each weight data is stored in a storage array.

[0065] In the above DRAM-PIM accelerator design method, multiple data to be processed are read from the storage array to the preprocessing unit, and the benchmark data is determined based on each data to be processed, and each data to be processed is physically stored continuously in the storage array; then, in the preprocessing unit, the benchmark data and each data to be processed are XORed to obtain multiple target data; finally, the benchmark data and each target data are read to the computing unit for data calculation. In this way, by obtaining the benchmark data from the data to be processed and XORing the benchmark data and the data to be processed respectively, the target data with higher sparsity can be obtained. Compared with directly reading and calculating the data to be processed, reading the target data with higher sparsity and calculating the target data can effectively reduce power consumption and improve the energy efficiency of the storage and computing system.

[0066] In an exemplary embodiment, Figure 6 As shown, optionally, the storage array is a dynamic random access memory array, multiple to-be-processed data are read from the storage array to the pre-processing unit, and the benchmark data is determined based on each to-be-processed data, including the following steps 601 to 602. Among them:

[0067] S601, reading a complete row of to-be-processed data in a storage array to a pre-processing unit through multiple reading cycles.

[0068] Optionally, when reading the data to be processed from the storage array to the pre-processing unit, the data to be processed may be read from the storage array to the pre-processing unit in the form of rows, i.e., a whole row of data.

[0069] Optionally, due to the limited number of output ports of the storage array, a whole row of data cannot be read into the preprocessing unit at the same time. Therefore, a complete row of data to be processed needs to be read into the preprocessing unit through multiple read cycles, and part of the data is selected from the complete row of data to be processed for output in each read cycle. For example, the output bit width of the storage array (i.e., the number of output ports) is 64 bits, and a complete row of data to be processed is 1024 bits. Therefore, this complete row of data to be processed can be read into the preprocessing unit through multiple read cycles. It can be understood that the above reading method is used for each row of data to be processed in the storage array.

[0070] Optionally, a selection unit can be used to select partial data output from a complete row of data to be processed. The selection unit can be a selector. For example, when the number of output ports of the storage array is 64 bits and a complete row of data to be processed is 1024 bits, 64 16-to-1 selectors can be used to select 64 bits for output each time for 16 consecutive read cycles. Alternatively, 32 32-to-1 selectors can be used to select 32 bits for output each time for 32 consecutive read cycles. The embodiment of the present application does not limit the number of output ports of the storage array, the form of the selector, and the read cycle, and can be set according to actual usage.

[0071] S602: Determine the data to be processed read in the first reading cycle among the data to be processed as the reference data.

[0072] The amount of to-be-processed data read in the first read cycle is related to the output bit width of the storage array.

[0073] Optionally, the benchmark data can be the benchmark data of a complete row of data to be processed, or the benchmark data of all data to be processed. It can be understood that when the benchmark data is the benchmark data of all data to be processed, the data to be processed read in the first reading cycle of the first row of data to be processed is used as the benchmark data; when the benchmark data is the benchmark data of a complete row of data to be processed, each row of data to be processed has its corresponding benchmark data. After reading a complete row of data to be processed, the benchmark data is updated, and the data to be processed read in the first reading cycle of the next complete row of data to be processed is used as the benchmark data. At the same time, the number of benchmark data in each row is determined by the number of selectors. In this way, the similarity between the data to be processed stored in the same row is higher. Based on the data to be processed read in the first reading cycle of each row as the benchmark data, each row corresponds to different benchmark data. When performing XOR, the sparsity of the target data can be further improved, and the power consumption of data reading can be reduced, thereby improving the energy efficiency of the storage and computing integrated system.

[0074] In an exemplary embodiment, Figure 7 As shown, optionally, a complete row of to-be-processed data in the storage array is read to the pre-processing unit through multiple read cycles, including the following steps 701 to 702. Among them:

[0075] S701, reading a complete row of data to be processed in the storage array into a row cache.

[0076] Optionally, the row cache can be a storage structure for temporarily storing data to be processed, and the data to be processed can be quickly read from the row cache. The design of the row cache can be implemented based on the reading speed of the data to be processed and the size of the data to be processed to ensure that the data to be processed can be quickly stored and retrieved, and at the same time, data will not be lost or overwritten due to insufficient cache capacity.

[0077] S702 , reading the to-be-processed data from the row cache to the pre-processing unit through a plurality of read cycles according to the selection unit.

[0078] Optional, such as Figure 8 As shown, a complete row of data to be processed in the storage array 801 can be read into the row cache 802 at the same time, and then the complete row of data to be processed can be read from the row cache 802 to the pre-processing unit 803 through multiple read cycles. In this way, it is possible to avoid the selection unit from reading the data to be processed from the storage array multiple times, thereby reducing the reading pressure of the storage array. At the same time, reading the data to be processed from the row cache can increase the data reading speed. When reading the data to be processed into the pre-processing unit 803, it can be based on the burst transmission (Brust) technology. Through the Brust transmission technology, it can be a continuous data reading operation in one data reading, which can reduce the overhead of bus transmission and improve data transmission efficiency.

[0079] Optionally, after the first reading cycle ends, the preprocessing unit uses the data to be processed read in the reading cycle as the reference data, and then after reading the data to be processed in the second reading cycle, the data to be processed read in the second reading cycle is XORed with the reference data to obtain the target data corresponding to the data to be processed in the second reading cycle. The preprocessing unit preprocesses the data to be processed read in other reading cycles in the same manner.

[0080] Optionally, after reading the data to be processed in the row cache, the next complete row of data to be processed is read into the row cache, and then the above step 702 is repeated. It can be understood that whether the benchmark data needs to be updated is determined according to the method of determining the benchmark data. For example, if the benchmark data is the benchmark data of a complete row of data to be processed, the benchmark number needs to be updated when the next row of data to be processed is read into the preprocessing unit. If the benchmark data is the benchmark data of all data to be processed, no update is required.

[0081] The above method reads a complete row of to-be-processed data in the storage array into the row cache, and reads the to-be-processed data from the row cache to the pre-processing unit through multiple read cycles according to the selection unit, which can reduce the reading pressure of the storage array and improve the data reading speed.

[0082] In an exemplary embodiment, Fig. 9 As shown, optionally, the reference data and each target data are read into a calculation unit to perform data calculation, including the following steps 901 to 902. Among them:

[0083] S901, determining calculation results of benchmark data and target data.

[0084] Optionally, after the preprocessing unit performs XOR on the read data to be processed according to the benchmark data to obtain the target data, the benchmark data and each target data are read into the calculation unit, and the calculation results of the benchmark data and the calculation results of each target data are calculated respectively.

[0085] Optionally, each target data may include target data corresponding to the reference data, that is, target data obtained by XORing the reference data with itself (all 0s), and the calculation result thereof is also 0.

[0086] Optionally, weight data can be obtained from a storage array, and in a calculation unit, the benchmark data and corresponding weight data are multiplied and added, and each target data and corresponding weight data are multiplied and added to obtain calculation results of the benchmark data and calculation results of each target data.

[0087] S902, respectively adding the calculation results of the reference data to the calculation results of each target data to obtain the data processing results of each data to be processed.

[0088] Optionally, after the calculation result of the benchmark data is obtained, the data processing result of any data to be processed is the sum of the calculation result of the target data corresponding to the data to be processed and the calculation result of the benchmark data.

[0089] The above-mentioned calculation results of the benchmark data and each target data are determined, and the calculation results of the benchmark data are respectively added to the calculation results of each target data to obtain the data processing results of each data to be processed. Since the target data has a high sparsity, on the one hand, the power consumption of data reading can be reduced. On the other hand, when the calculation unit determines the calculation result, compared with directly calculating based on the data to be processed, calculating based on the target data can increase the calculation speed, reduce the calculation power consumption, and further improve the performance of the storage and computing integrated system.

[0090] As an optional implementation, Fig.10 As shown, the DRAM-PIM accelerator design method provided in the embodiment of the present application may include the following specific steps:

[0091] S1001, reading a complete row of data to be processed in the storage array into a row cache.

[0092] The storage array is a dynamic random access memory array.

[0093] S1002 , reading the to-be-processed data from the row cache to the pre-processing unit through a plurality of read cycles according to the selection unit.

[0094] S1003, determining the data to be processed read in the first reading cycle among the data to be processed as the reference data.

[0095] The amount of to-be-processed data read in the first read cycle is related to the output bit width of the storage array.

[0096] S1004, in a pre-processing unit, performing XOR processing on the reference data and each data to be processed to obtain a plurality of target data.

[0097] S1005, reading the reference data and each target data into the calculation unit.

[0098] S1006, determining calculation results of the benchmark data and each target data.

[0099] S1007, respectively adding the calculation results of the reference data to the calculation results of each target data to obtain the data processing results of each data to be processed.

[0100] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0101] Based on the same inventive concept, the embodiment of the present application also provides a storage-computing integrated system for implementing the DRAM-PIM accelerator design method involved above. The implementation scheme for solving the problem provided by the system is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more storage-computing integrated system embodiments provided below can refer to the limitations of the DRAM-PIM accelerator design method above, and will not be repeated here.

[0102] In an exemplary embodiment, Figure 3 As shown, a storage-computing integrated system 30 is provided for use in neural network calculations. The storage-computing integrated system 30 includes:

[0103] A storage array 31, the storage array 31 is used to store a plurality of data to be processed, each of which is physically and continuously stored in the storage array 31;

[0104] A preprocessing unit 32, the preprocessing unit 32 is used to read each to-be-processed data from the storage array 31, determine the reference data based on each to-be-processed data, perform XOR processing on the reference data and each to-be-processed data to obtain a plurality of target data, and read the reference data and each target data to the calculation unit 33;

[0105] The calculation unit 33 is used to perform data calculation according to the reference data and each target data.

[0106] In an exemplary embodiment, optionally, when the storage-computing integrated system reads binary data, if the binary data is '1', a short circuit path exists in the storage-computing integrated system, which generates additional reading power consumption.

[0107] Optionally, the storage and computing integrated system is used to implement the steps described in any of the above method embodiments.

[0108] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Fig.11 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a DRAM-PIM accelerator design method is implemented.

[0109] Those skilled in the art will understand that Fig.11 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0110] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0111] Reading a plurality of to-be-processed data from a storage array to a pre-processing unit, and determining a reference data based on each to-be-processed data, wherein each to-be-processed data is physically and continuously stored in the storage array;

[0112] In the preprocessing unit, the reference data and each data to be processed are subjected to XOR processing to obtain a plurality of target data;

[0113] The reference data and each target data are read into the calculation unit to perform data calculation.

[0114] In one embodiment, the multiple data to be processed are input image data, and the data calculation includes multiplication and addition operations on the reference data and the weight data corresponding to the reference data, and multiplication and addition operations on each target data and the weight data corresponding to each target data, and each weight data is stored in a storage array.

[0115] In one embodiment, the storage array is a dynamic random access memory array, and the processor further implements the following steps when executing the computer program:

[0116] A complete row of data to be processed in the storage array is read to the preprocessing unit through multiple read cycles; the data to be processed read in the first read cycle among the data to be processed is determined as the reference data, and the amount of data to be processed read in the first read cycle is related to the output bit width of the storage array.

[0117] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0118] A complete row of data to be processed in the storage array is read into the row cache; and the data to be processed is read from the row cache to the pre-processing unit through multiple read cycles according to the selection unit.

[0119] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0120] Determine the calculation results of the benchmark data and each target data; and add the calculation results of the benchmark data to the calculation results of each target data to obtain the data processing results of each data to be processed.

[0121] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0122] Reading a plurality of to-be-processed data from a storage array to a pre-processing unit, and determining a reference data based on each to-be-processed data, wherein each to-be-processed data is physically and continuously stored in the storage array;

[0123] In the preprocessing unit, the reference data and each data to be processed are subjected to XOR processing to obtain a plurality of target data;

[0124] The reference data and each target data are read into the calculation unit to perform data calculation.

[0125] In one embodiment, the multiple data to be processed are input image data, and the data calculation includes multiplication and addition operations on the reference data and the weight data corresponding to the reference data, and multiplication and addition operations on each target data and the weight data corresponding to each target data, and each weight data is stored in a storage array.

[0126] In one embodiment, the storage array is a dynamic random access memory array, and the computer program, when executed by the processor, further implements the following steps:

[0127] A complete row of data to be processed in the storage array is read to the preprocessing unit through multiple read cycles; the data to be processed read in the first read cycle among the data to be processed is determined as the reference data, and the amount of data to be processed read in the first read cycle is related to the output bit width of the storage array.

[0128] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0129] A complete row of data to be processed in the storage array is read into the row cache; and the data to be processed is read from the row cache to the pre-processing unit through multiple read cycles according to the selection unit.

[0130] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0131] Determine the calculation results of the benchmark data and each target data; and add the calculation results of the benchmark data to the calculation results of each target data to obtain the data processing results of each data to be processed.

[0132] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0133] Reading a plurality of to-be-processed data from a storage array to a pre-processing unit, and determining a reference data based on each to-be-processed data, wherein each to-be-processed data is physically and continuously stored in the storage array;

[0134] In the preprocessing unit, the reference data and each data to be processed are subjected to XOR processing to obtain a plurality of target data;

[0135] The reference data and each target data are read into the calculation unit to perform data calculation.

[0136] In one embodiment, the multiple data to be processed are input image data, and the data calculation includes multiplication and addition operations on the reference data and the weight data corresponding to the reference data, and multiplication and addition operations on each target data and the weight data corresponding to each target data, and each weight data is stored in a storage array.

[0137] In one embodiment, the storage array is a dynamic random access memory array, and the computer program, when executed by the processor, further implements the following steps:

[0138] A complete row of data to be processed in the storage array is read to the preprocessing unit through multiple read cycles; the data to be processed read in the first read cycle among the data to be processed is determined as the reference data, and the amount of data to be processed read in the first read cycle is related to the output bit width of the storage array.

[0139] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0140] A complete row of data to be processed in the storage array is read into the row cache; and the data to be processed is read from the row cache to the pre-processing unit through multiple read cycles according to the selection unit.

[0141] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0142] Determine the calculation results of the benchmark data and each target data; and add the calculation results of the benchmark data to the calculation results of each target data to obtain the data processing results of each data to be processed.

[0143] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0144] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0145] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A DRAM-PIM accelerator design method based on data similarity, characterized in that: For neural network computing, the DRAM-PIM accelerator design method is applied to a storage-computing integrated system, which includes a storage array, a preprocessing unit and a computing unit, including: Reading a plurality of to-be-processed data from the storage array to a pre-processing unit, and determining reference data based on each of the to-be-processed data, wherein each of the to-be-processed data is physically and continuously stored in the storage array; In the preprocessing unit, the reference data and each of the to-be-processed data are subjected to XOR processing to obtain a plurality of target data; The reference data and each target data are read into a calculation unit to perform data calculation.

2. The method according to claim 1, characterized in that The multiple data to be processed are input image data, and the data calculation includes multiplying and adding the reference data and the weight data corresponding to the reference data, and multiplying and adding each target data and the weight data corresponding to each target data, and each weight data is stored in a storage array.

3. The method according to claim 1, characterized in that The storage array is a dynamic random access memory array, and the plurality of to-be-processed data are read from the storage array to a pre-processing unit, and the benchmark data is determined based on each of the to-be-processed data, including: Reading a complete row of to-be-processed data in the storage array to a pre-processing unit through multiple reading cycles; The data to be processed read in the first read cycle among the data to be processed is determined as the reference data, and the amount of the data to be processed read in the first read cycle is related to the output bit width of the storage array.

4. The method according to claim 3, characterized in that The step of reading a complete row of to-be-processed data in the storage array to a pre-processing unit through multiple read cycles includes: Reading a complete row of data to be processed in the storage array into a row cache; The selection unit reads the to-be-processed data from the row cache to the pre-processing unit through a plurality of read cycles.

5. The method according to claim 2, characterized in that: The step of reading the reference data and each target data into a calculation unit to perform data calculation includes: Determine the calculation results of the benchmark data and each of the target data; The calculation results of the reference data are respectively added to the calculation results of each target data to obtain the data processing results of each data to be processed.

6. A storage and computing integrated system, characterized in that: Used in neural network calculations, the storage and computing integrated system includes: A storage array, the storage array is used to store a plurality of data to be processed, each of the data to be processed is physically and continuously stored in the storage array; A preprocessing unit, the preprocessing unit is used to read each of the to-be-processed data from the storage array, determine reference data based on each of the to-be-processed data, perform XOR processing on the reference data and each of the to-be-processed data to obtain a plurality of target data, and read the reference data and each of the target data into a computing unit; A calculation unit, wherein the calculation unit is used to perform data calculation according to the reference data and each target data.

7. The system according to claim 6, characterized in that When the storage-computing integrated system reads binary data, if the binary data is '1', a short circuit path exists in the storage-computing integrated system, which generates additional reading power consumption.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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