Microprocessor

Abstract

The invention discloses a microprocessor, which comprises a program counter, an instruction fetching unit, a memory management unit, a configuration and state register module, an instruction decoding unit and an instruction execution unit, when the memory management unit is started, a specific bit of a configuration page table represents an instruction set architecture to which a corresponding code belongs; a first check rule is stored in the configuration and state register module: when the memory management unit is enabled, an instruction set architecture to which an instruction stored in the first physical address belongs is determined through a specific bit, and the physical address checker determines the instruction set architecture to which the instruction stored in the first physical address belongs based on the first check rule; the configuration and state register module configures instruction set environment information based on the determination information, the instruction decode unit translates the instruction into a general purpose microinstruction based on the instruction set environment information, and the instruction execution unit executes the general purpose microinstruction based on the instruction set environment information. According to the application, the compatibility of the application program of the cross-instruction-set architecture on the single-instruction-set processor is realized.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor chip design, and in particular to a microprocessor. Background Art

[0002] The hardware platform design of modern general-purpose processors is basically designed according to only one instruction set architecture. When you need to run a target program that does not conform to the instruction set architecture of the current processor, there are several solutions:

[0003] (1) Recompile the application using the compilation tool chain for the instruction set architecture of the current processor.

[0004] (2) Use binary translation technology.

[0005] (3) Multi-core heterogeneous architecture, integrating multiple processors using different instruction set architectures on a single chip.

[0006] However, the above solutions have the following technical problems:

[0007] Solution (1) has high requirements for application code. Compilation tools for different instruction set architectures may not be able to complete the compilation of the same program in one go, which places a heavy burden on software porting personnel.

[0008] Solution (2) will incur conversion overhead and the performance of the target application will be severely affected.

[0009] Solution (3) will greatly increase hardware overhead.

[0010] Therefore, it is necessary to provide a new solution to solve the technical problems existing in the above solutions. Summary of the invention

[0011] The embodiment of the present application provides a microprocessor that achieves compatibility of applications across instruction set architectures on a single instruction set processor, eliminating the need for software porting and recompilation, and eliminating the need to use a multi-core heterogeneous architecture.

[0012] In view of this, an embodiment of the present application provides a microprocessor, including: a program counter, an instruction fetch unit, a memory management unit, a configuration and status register module, an instruction decoding unit and an instruction execution unit. When the memory management unit is turned on, a specific bit in the address attribute of the configuration page table indicates the instruction set architecture to which the corresponding code belongs. When the memory management unit is enabled, the memory management unit converts the virtual address into a first physical address based on the page table. A first check rule is stored in the configuration and status register module. The first check rule is: when the memory management unit is enabled, the first physical address is determined by the specific bit. The instruction set architecture to which the stored instruction belongs, the instruction fetch unit includes a physical address checker, the physical address checker determines the instruction set architecture to which the instruction stored at the first physical address belongs based on the first checking rule, after the physical address checker determines the instruction set architecture to which the instruction stored at the physical address belongs, the configuration and status register module configures the instruction set environment information based on the information, the instruction decoding unit translates the instruction from the instruction fetch unit into general microinstructions based on the instruction set environment information in the configuration and status register module, and the instruction execution unit executes the general microinstructions based on the instruction set environment information and outputs the execution result.

[0013] Optionally, configured in the configuration and status register module: a plurality of address ranges and an instruction set architecture to which the instructions stored in each of the address ranges belong;

[0014] A second checking rule is configured in the configuration and status register module, wherein the second checking rule is: when the memory management unit is not enabled, determining the instruction set architecture to which the instruction stored at the second physical address obtained by the instruction fetch unit from the program counter belongs based on the instruction set architecture to which the instructions stored in each of the address ranges belong;

[0015] The physical address checker determines the instruction set architecture to which the instruction stored at the second physical address belongs based on the second checking rule.

[0016] Optionally, several address range registers of the configuration and status register module are used to define several address ranges and identify instruction set attributes corresponding to each address range.

[0017] Optionally, the instruction set architecture includes an ARM instruction set architecture and a RISC-V instruction set architecture.

[0018] Optionally, the instruction execution unit is connected to the configuration and status register module, and the instruction execution unit receives the instruction set environment information from the configuration and status register module and performs adaptation according to the instruction set environment information.

[0019] Optionally, the microprocessor includes a memory access subsystem, which is respectively connected to the program counter, the configuration and status register module and the instruction execution unit, and the memory access subsystem is adapted based on the instruction set environment information in the configuration and status register module.

[0020] Optionally, the microprocessor includes a general register group, which is respectively connected to the configuration and status register module and the instruction execution unit, and the general register group is adapted according to the instruction set environment information in the configuration and status register module.

[0021] Optionally, when the microprocessor is powered on or reset, an initialization operation is performed, the configuration and status register module is reset, and the microprocessor is in an initial instruction set environment.

[0022] Optionally, the configuration and status register module is reset such that the entire address space is marked as an instruction set attribute.

[0023] Optionally, when the memory management unit is enabled, the marking of the instruction set attribute by the configuration and status register module is invalid.

[0024] In an embodiment of the present application, when the memory management unit is turned on, a specific bit in the address attribute of the configuration page table indicates the instruction set architecture to which the corresponding code belongs. When the memory management unit is enabled, the memory management unit converts the virtual address into a first physical address based on the page table. A first check rule is stored in the configuration and status register module. The first check rule is: when the memory management unit is enabled, the instruction set architecture to which the instruction stored at the first physical address belongs is determined by a specific bit. The instruction fetch unit includes a physical address checker. The physical address checker determines the instruction set architecture to which the instruction stored at the first physical address belongs based on the first check rule. The configuration and status register module After the physical address checker determines the instruction set architecture to which the instruction stored at the physical address belongs, the instruction set environment information is configured based on the information, and the microprocessor can then perform corresponding adaptation, so that the present application can distinguish the instruction set architecture to which the instruction stored at the physical address belongs when the memory management unit is enabled, so that the microprocessor can implement mixed execution of instructions from different instruction sets, and target programs compiled by compilation tools from different instruction sets can call each other, and are fully compatible with ecological software of different instruction sets, eliminating the work of software porting and recompilation, and there is no need to use a multi-core heterogeneous architecture, thus achieving compatibility of applications across instruction set architectures on a single instruction set processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the microprocessor related structure of the embodiment of the present application.

[0026] Figure 2It is a schematic diagram of the basic structure of the microprocessor pipeline according to an embodiment of the present application.

[0027] Figure 3 It is a schematic diagram of an instruction fetch unit, etc. according to an embodiment of the present application.

[0028] Figure 4 It is a schematic diagram of the register page of the embodiment of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] See also Figure 1 and Figure 2 The embodiment of the present application discloses a microprocessor, including: a program counter 1 (Program Counter, PC), an instruction fetch unit 2, a memory management unit (Memory Management Unit, MMU) 3, a configuration and status register module 4, an instruction decoding unit 5 and an instruction execution unit 6.

[0031] Program Counter 1 is used to store the address of the next instruction to be executed. Program Counter 1 is continuously updated during the execution of instructions to ensure that instructions are executed in sequence.

[0032] The instruction fetch unit 2 is used to obtain the instruction address from the program counter 1. When the memory management unit 3 is enabled, the instruction address obtained is a virtual address, and when the memory management unit 3 is not enabled, the instruction address obtained is a physical address.

[0033] The memory management unit 3 is used to translate the aforementioned virtual address into a physical address, specifically, to translate the virtual address into a physical address based on a page table.

[0034] When the memory management unit 3 is turned on, a specific bit of the address attribute of the configuration page table indicates the instruction set architecture to which the corresponding code belongs. When the memory management unit 3 is enabled, the memory management unit 3 converts the virtual address into the first physical address based on the page table. The instruction set architecture to which it belongs can be one of the ARM instruction set architecture and the RISC-V instruction set architecture. For example, when the value of the specific bit is 1, it indicates that the instruction stored at the first physical address belongs to the ARM instruction set architecture. When the value of the specific bit is 0, it indicates that the instruction stored at the first physical address belongs to the RISC-V instruction set architecture.

[0035] The configuration and status register module 4 stores a first checking rule, which is: when the memory management unit 3 is enabled, the instruction set architecture to which the instruction stored at the first physical address belongs is determined through a specific bit.

[0036] Specifically, a register unit specifically used for storing the first checking rule may be configured in the configuration and status register module 4 .

[0037] In order to perform checks based on checking rules, the instruction fetch unit 2 includes a physical address checker 21, which determines the instruction set architecture to which the instruction stored at the first physical address belongs based on the first checking rule, that is, determines the instruction set architecture to which the instruction stored at the first physical address belongs through the instruction set architecture represented by a specific bit.

[0038] After the physical address checker 21 determines the instruction set architecture to which the instruction stored at the physical address (not limited to the first physical address) belongs, the configuration and status register module 4 configures the instruction set environment information based on the information. That is, the configuration and status register module 4 will configure the instruction set environment information based on the instruction set architecture to which the instruction stored at the physical address belongs, and the microprocessor can perform overall adaptation based on the instruction set environment information so that the microprocessor can work in the corresponding instruction set environment. Specifically, when the instruction set architecture to which the instruction stored at the current physical address belongs is different from the instruction set architecture to which the instruction stored at the previous physical address belongs, the instruction set environment information will change to different identification information, and the microprocessor will adapt based on the current instruction set environment information.

[0039] Specifically, the configuration and status register module 4 includes a dedicated instruction set environment register unit for configuring and updating instruction set environment information.

[0040] The instruction decoding unit 5 translates the instructions from the instruction fetch unit 2 into general microinstructions based on the instruction set environment information in the configuration and status register module 4 .

[0041] Specifically, the instruction decoding unit 5 can translate ARM instruction set instructions and RISC-V instruction set instructions, and translate the ARM instruction set instructions and RISC-V instruction set instructions into general microinstructions that are different from the ARM instruction set instructions and RISC-V instruction set instructions.

[0042] The instruction execution unit 6 executes the general microinstructions based on the instruction set environment information and outputs the execution results.

[0043] In order to enable the instruction execution unit 6 to smoothly execute the general microinstructions translated from the current instruction, the microprocessor can perform corresponding adaptation based on the instruction set environment information, so that the instruction execution unit 6 can execute the general microinstructions based on the instruction set environment information, so as to smoothly execute the general microinstructions and output the correct execution results.

[0044] In the embodiment of the present application, when the memory management unit 3 is turned on, a specific bit in the address attribute of the configuration page table indicates the instruction set architecture to which the corresponding code belongs. When the memory management unit 3 is enabled, the memory management unit 3 converts the virtual address into a first physical address based on the page table. A first check rule is stored in the configuration and status register module 4. The first check rule is: when the memory management unit 3 is enabled, the instruction set architecture to which the instruction stored at the first physical address belongs is determined by a specific bit. The instruction fetch unit 2 includes a physical address checker 21. The physical address checker 21 determines the instruction set architecture to which the instruction stored at the first physical address belongs based on the first check rule. The configuration and status register After the physical address checker 21 determines the instruction set architecture to which the instruction stored at the physical address belongs, module 4 configures the instruction set environment information based on the information, and then the microprocessor can perform corresponding adaptation, so that the present application can distinguish the instruction set architecture to which the instruction stored at the physical address belongs when the memory management unit 3 is enabled, so that the microprocessor can realize mixed execution of instructions of different instruction sets, and target programs compiled by compilation tools from different instruction sets can call each other, and are fully compatible with ecological software of different instruction sets, eliminating the work of software porting and recompilation, and there is no need to use a multi-core heterogeneous architecture, thus realizing the compatibility of cross-instruction set architecture applications on a single instruction set processor.

[0045] In some embodiments, configured in the configuration and status register module 4 are: a number of address ranges and the instruction set architecture to which the instructions stored in each address range belong.

[0046] The second check rule is configured in the configuration and status register module 4, and the second check rule is: when the memory management unit 3 is not enabled, the instruction set architecture to which the instruction stored at the second physical address obtained by the instruction fetch unit 2 from the program counter 1 belongs is determined based on the instruction set architecture to which the instructions stored in each address range belong. That is, after determining which address range the second physical address belongs to, the instruction set architecture corresponding to the second physical address can be determined based on the instruction set architecture corresponding to the address range. It should be noted that when the memory management unit 3 is not enabled, the physical address obtained from the program counter 1 is defined as the second physical address.

[0047] The physical address checker 21 determines the instruction set architecture to which the instruction stored at the second physical address belongs based on the second checking rule.

[0048] Next, after the physical address checker 21 determines the instruction set architecture to which the instruction stored at the second physical address belongs, the configuration and status register module 4 configures the instruction set environment information based on the information, the instruction decoding unit 5 translates the instructions from the instruction fetch unit 2 into general microinstructions based on the instruction set environment information in the configuration and status register module 4, and the instruction execution unit 6 executes the general microinstructions based on the instruction set environment information and outputs the execution result.

[0049] By configuring several address ranges and the instruction set architecture to which the instructions stored in each address range belong in the configuration and status register module 4, and configuring a second checking rule in the configuration and status register module 4, the physical address checker 21 determines the instruction set architecture to which the instruction stored at the second physical address belongs based on the second checking rule, so that the present application can distinguish the instruction set architecture to which the instruction stored at the physical address belongs when the memory management unit 3 is enabled, so that the microprocessor can realize mixed execution of instructions of different instruction sets, and can also distinguish the instruction set architecture to which the instruction stored at the physical address belongs when the memory management unit 3 is not enabled, so that the microprocessor can realize mixed execution of instructions of different instruction sets.

[0050] Specifically, when the instruction set architecture includes the ARM instruction set architecture and the RISC-V instruction set architecture, the instruction set architecture to which the instructions stored in each address range belong is partly the ARM instruction set architecture and partly the RISC-V instruction set architecture.

[0051] Specifically, several address ranges are defined and the instruction set attributes corresponding to each address range are identified by using several address range registers of the configuration and status register module 4. The address range register may include two registers, one for defining the starting address of the address range and the other for defining the ending address or length of the address range, thereby defining the address range.

[0052] Specifically, the instruction execution unit 6 is connected to the configuration and status register module 4, and the instruction execution unit 6 receives the instruction set environment information from the configuration and status register module 4 and adapts according to the instruction set environment information, that is, adapts to the corresponding instruction set architecture or environment. For example, when the instruction set environment changes from the ARM instruction set environment to the RISC-V instruction set environment, the instruction execution unit 6 needs to adapt to the RISC-V instruction set environment in order to smoothly execute the general microinstructions translated from the corresponding ARM instruction set instructions.

[0053] Specifically, the microprocessor includes a memory access subsystem 7, which is respectively connected to the program counter 1, the configuration and status register module 4 and the instruction execution unit 6. The memory access subsystem 7 is adapted based on the instruction set environment information in the configuration and status register module 4, that is, adapted to the corresponding instruction set architecture or environment.

[0054] Specifically, the microprocessor includes a general register group 8, which is respectively connected to the configuration and status register module 4 and the instruction execution unit 6. The general register group 8 is adapted according to the instruction set environment information in the configuration and status register module 4, that is, adapted to the corresponding instruction set architecture or environment.

[0055] See also Figure 3 , which displays the register page, which shows the registers specific to the ARM instruction set architecture, the registers specific to the RISC-V instruction set architecture (none), and the registers common to both.

[0056] It can be understood that, for the shared computing resources, the sharing of the general register group 8 is guaranteed by hardware, and the sharing and conflicts of the remaining resources such as CPU, storage, and peripherals need to be resolved by software.

[0057] Specifically, when the microprocessor is powered on or reset, an initialization operation is performed, the configuration and status register module 4 is reset, and the microprocessor is in an initial instruction set environment, that is, in one of the instruction set environments, or in other words, the microprocessor executes instructions based on its own instruction set architecture.

[0058] The initial instruction set environment can be one of the ARM instruction set environment and the RISC-V instruction set environment. During the initialization operation, registers of the ARM instruction set architecture, registers of the RISC-V instruction set architecture and other general registers are initialized.

[0059] Specifically, the configuration and status register module 4 is reset so that the entire address space is marked as an instruction set attribute, which can be an ARM instruction set attribute or a RISC-V instruction set attribute.

[0060] When the microprocessor is in the initial instruction set environment, the memory management unit 3 can be enabled based on different instructions. During the enabling process, the memory management unit 3 performs corresponding configuration, or the configuration and status register module 4 can be configured to facilitate subsequent physical address checker 21 to perform inspection.

[0061] Specifically, when the memory management unit 3 is enabled, the marking of the instruction set attribute by the configuration and status register module 4 is invalid, so that the physical address is checked based on the first checking rule.

[0062] Combine the following Figure 4The instruction fetch unit 2 and the like are briefly described. After the instruction fetch unit 2 fetches the instruction address from the program counter 1 (address translation is performed when the memory management unit 3 is enabled), the physical address checker 21 of the instruction fetch unit 2 determines the instruction set architecture to which the instruction stored at the physical address belongs based on the corresponding check rules in the configuration and status register module 4 and feeds back the determination information to the configuration and status register module 4. The configuration and status register module 4 configures the instruction set environment information based on the determination information. After the instruction fetch unit 2 fetches the instruction, the memory access subsystem 7 performs a simple decoding of the instruction based on the instruction set environment information. Thereafter, based on the simply decoded instruction, the program counter 1 performs an address update, and performs branch prediction and branch prediction check based on the simply decoded instruction and the instruction set environment information, and based on the result, the program counter 1 performs an address update, and after performing branch prediction and branch prediction check, the instruction decoding unit 5 is used to perform instruction translation.

[0063] The above disclosure is only a preferred example of the present application and cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are all within the scope covered by the present application.

Claims

1. A microprocessor, characterized in that: include: A program counter, an instruction fetch unit, a memory management unit, a configuration and status register module, an instruction decoding unit and an instruction execution unit. When the memory management unit is turned on, a specific bit in the address attribute of the configuration page table indicates the instruction set architecture to which the corresponding code belongs. When the memory management unit is enabled, the memory management unit converts the virtual address into a first physical address based on the page table. A first checking rule is stored in the configuration and status register module. The first checking rule is: when the memory management unit is enabled, the instruction set architecture to which the instruction stored at the first physical address belongs is determined by the specific bit. The instruction fetch unit includes a physical address checker. The physical address checker determines the instruction set architecture to which the instruction stored at the first physical address belongs based on the first checking rule. After the physical address checker determines the instruction set architecture to which the instruction stored at the physical address belongs, the configuration and status register module configures instruction set environment information based on the information. The instruction decoding unit translates the instruction from the instruction fetch unit into a general microinstruction based on the instruction set environment information in the configuration and status register module. The instruction execution unit executes the general microinstruction based on the instruction set environment information and outputs the execution result.

2. The microprocessor according to claim 1, characterized in that: Configuring in the configuration and status register module: a plurality of address ranges and an instruction set architecture to which instructions stored in each of the address ranges belong; A second checking rule is configured in the configuration and status register module, wherein the second checking rule is: when the memory management unit is not enabled, determining the instruction set architecture to which the instruction stored at the second physical address obtained by the instruction fetch unit from the program counter belongs based on the instruction set architecture to which the instructions stored in each of the address ranges belong; The physical address checker determines the instruction set architecture to which the instruction stored at the second physical address belongs based on the second checking rule.

3. The microprocessor according to claim 2, characterized in that: Several address range registers of the configuration and status register module are used to define several address ranges and identify instruction set attributes corresponding to each address range.

4. The microprocessor according to claim 1, characterized in that: The instruction set architecture includes the ARM instruction set architecture and the RISC-V instruction set architecture.

5. The microprocessor according to claim 1, characterized in that: The instruction execution unit is connected to the configuration and status register module, and the instruction execution unit receives the instruction set environment information from the configuration and status register module and performs adaptation according to the instruction set environment information.

6. The microprocessor according to claim 5, characterized in that: The microprocessor comprises a memory access subsystem, which is respectively connected to the program counter, the configuration and status register module and the instruction execution unit, and the memory access subsystem is adapted based on the instruction set environment information in the configuration and status register module.

7. The microprocessor according to claim 6, characterized in that: The microprocessor comprises a general register group, which is respectively connected to the configuration and status register module and the instruction execution unit, and the general register group is adapted according to the instruction set environment information in the configuration and status register module.

8. The microprocessor according to claim 1, characterized in that: When the microprocessor is powered on or reset, an initialization operation is performed, the configuration and status register module is reset, and the microprocessor is in an initial instruction set environment.

9. The microprocessor according to claim 8, characterized in that: The configuration and status register module reset causes the entire address space to be marked as an instruction set attribute.

10. The microprocessor according to claim 9, characterized in that: When the memory management unit is enabled, the marking of the instruction set attribute by the configuration and status register module is invalid.

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