Method for generating controllable clock based on UVM
By writing a clock virtual interface file and declaring it to the top level of the UVM verification platform, the problem of cumbersome clock frequency settings and changes in chip verification is solved, and clock signals of various frequencies are generated efficiently and quickly, improving the speed and comprehensiveness of verification, and ensuring the accuracy of verification results.
Patent Information
- Application Number
- CN202411884226.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-04-25
AI Technical Summary
During the chip verification process, the setting and change of clock frequency is complicated, and the multi-clock interface is likely to cause confusion, the top-level file is too long and some frequency divisions may be missed, resulting in incomplete verification and insufficient accuracy.
By obtaining the clock parameter information and port information of the design to be tested, writing a clock virtual interface file, and declaring it to the top level of the UVM verification platform, using the UVM parameter transmission mechanism to generate and transmit the required clock signal, and directly input the clock port of the design to be tested.
It is possible to generate clock signals of various frequencies without modifying the top-level files of the UVM verification platform, which improves verification speed and comprehensiveness and ensures the accuracy of verification results.
Smart Images
Figure CN119885985A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of digital circuit verification, and more particularly to a method for generating a controllable clock based on UVM. Background Art
[0002] Nowadays, the development of electronic products is changing with each passing day, and consumers have higher and higher requirements on chip performance. Smooth operation without lag is an important indicator. Therefore, the data transmission rate inside the chip needs to be faster and faster, which makes the requirements on clock frequency more and more stringent. Therefore, the verification of clocks of different frequencies becomes very important when verifying the chip.
[0003] In the daily chip verification process, the clock connected to the design to be tested is very fixed. Most of the time, the clock frequency is set directly in the top-level file of the UVM verification platform, and then directly connected to the port of the design to be tested. In the process of connecting the clock, after the clock frequency is set, if it needs to be changed, it is also necessary to change the top-level file of the UVM verification platform, which is very cumbersome; and if there is more than one clock interface of the design to be tested, it is easy to confuse the correspondence between each clock and interface; in addition, the clock frequency can also be selected through macro definition, but it is necessary to list various frequency division situations in the top-level file of the verification environment, which makes the top-level file too long, and there may be incomplete listings, resulting in incomplete verification of the design to be tested and insufficient accuracy of the verification results.
[0004] Therefore, it is necessary to provide an improved method for generating a controllable clock based on UVM to overcome the above-mentioned defects. Summary of the invention
[0005] The purpose of the invention is to provide a method for generating a controllable clock based on UVM. The method for generating a controllable clock based on UVM of the invention can efficiently and quickly generate clocks of various frequencies required in a verification process without modifying a UVM verification platform top-level file, covers clock signals of various frequencies required in a verification process of a design to be tested, speeds up verification, makes the verification process more comprehensive, and makes a verification result more accurate.
[0006] To achieve the above-mentioned purpose, the present invention provides a method for generating a controllable clock based on UVM, which comprises the following steps: a. acquiring parameter information and clock port information of each clock of a design to be tested; b. compiling a clock virtual interface file according to the information of each clock port of the design to be tested; c. declaring the clock virtual interface file to the top layer of a UVM verification platform; d. generating a corresponding clock signal according to the clock virtual interface file at the top layer of the UVM verification platform and the parameter information of each clock of the design to be tested; and e. inputting the generated clock signal to the corresponding clock port of the design to be tested according to the clock virtual interface file.
[0007] Preferably, each clock of the design to be tested corresponds to its clock port one by one.
[0008] Preferably, the clock virtual interface file defines the correspondence between the clock port of the design to be tested and the virtual interface of the top layer of the UVM verification platform.
[0009] Preferably, in step c, the top layer of the UVM verification platform sends the declared clock virtual interface file to the clock generation module, and connects the clock virtual interface of the top layer of the UVM verification platform to the clock port of the design to be tested according to the clock virtual interface file.
[0010] Preferably, in step c, the top layer of the UVM verification platform sends the declared clock virtual interface file to the clock generation module through the parameter transmission mechanism of UVM.
[0011] Preferably, in step d, the test case transmits parameter information of each clock of the design to be tested to a clock generation module, and the clock generation module generates a clock of corresponding frequency according to the received parameter information of each clock.
[0012] Preferably, in the step d, the clock generation module sends the generated clock signal to the top layer of the UVM verification platform through the parameter transmission mechanism of UVM.
[0013] Preferably, in step e, the top layer of the UVM verification platform transmits the received clock signal to the clock port corresponding to the design under test through the virtual interface according to the clock virtual interface file.
[0014] Compared with the prior art, the method for generating a controllable clock based on UVM of the present invention defines a clock virtual interface file for defining a corresponding relationship between a clock port of a design to be tested and a virtual interface of a top layer of a UVM verification platform, and the clock virtual interface file is not arranged at the top layer of the UVM verification platform, and after the clock virtual interface file is declared to the top layer of the UVM verification platform, the top layer of the UVM verification platform can identify and use the clock virtual interface file, so that various clock signals required by the design to be tested can be generated without modifying the top layer file of the UVM verification platform, so that the generation of the clock signal required by the design to be tested is more efficient and faster; at the same time, the clock virtual interface file is not arranged at the top layer of the UVM verification platform, so that the space of the top layer file is not required, and the memory is not affected, and the situations of various clocks can all be included, covering the clock signals of various frequencies required in the verification process of the design to be tested, so that the verification process is more comprehensive and the verification result is more accurate; in addition, the clock generation module obtains the clock parameter information of the design to be tested through a test case, and does not need to be directly obtained from the design to be tested, so that the interference to the design to be tested in the verification process is reduced, and the accuracy of the verification result is guaranteed.
[0015] The present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, which are used to illustrate embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 The present invention is a flow chart of a method for generating a controllable clock based on UVM. DETAILED DESCRIPTION
[0017] Embodiments of the present invention are now described with reference to the accompanying drawings, in which similar element numbers represent similar elements. As described above, the present invention provides a method for generating a controllable clock based on UVM, and the method of the present invention can efficiently and quickly generate clocks of various frequencies required in the verification process without modifying the UVM verification platform top-level file, thereby accelerating the speed of verification, making the verification process more comprehensive, and the verification result more accurate.
[0018] Please refer to Figure 1 , Figure 1 Be the flow chart of the method for generating controllable clock based on UVM of the present invention, as shown in the figure, the method for generating controllable clock based on UVM of the present invention comprises the steps:
[0019] Step S100, obtaining parameter information and clock port information of each clock of the design to be tested; in this step, before the design to be tested is verified, the verification staff needs to obtain various parameters of the design to be tested in advance, and write test cases according to the obtained parameters, and then perform various verifications on the design to be tested through the test cases, wherein the parameter information and clock port information of each clock of the design to be tested can also be obtained in this process, so as to facilitate use in subsequent steps; wherein, each clock of the design to be tested corresponds to a clock port one by one, that is, one clock of the design to be tested corresponds to one of its clock ports for transmission, and the parameter information of the clock is matched with the clock port information, thereby ensuring a one-to-one correspondence between the clock signal and the clock port without confusion.
[0020] Step S200, compiles and forms a clock virtual interface file according to each clock port information of the design to be tested; In this step, the corresponding relationship between the clock port of the design to be tested and the virtual interface of the top layer of the UVM verification platform is defined in the clock virtual interface file, so that the clock port of the design to be tested and the virtual interface of the top layer of the UVM verification platform are in one-to-one correspondence; As mentioned above, each clock port of the design to be tested and its each clock signal are in one-to-one correspondence, therefore, each clock signal of the design to be tested is also in one-to-one correspondence with the virtual interface of the top layer of the UVM verification platform through the clock virtual interface file.
[0021] Step S300, declare the clock virtual interface file to the top layer of the UVM verification platform; in this step, the clock virtual interface file written in step S200 cannot be directly recognized and used by the top layer of the UVM verification platform, so that the top layer of the UVM verification platform can recognize the clock virtual interface file through the declaration operation, and then the virtual interface of the top layer of the UVM verification platform can be connected to the clock port of the design to be tested according to the clock virtual interface file, so as to establish a communication channel between the top layer of the UVM verification platform and the design to be tested; in addition, in this step, the top layer of the UVM verification platform sends the declared clock virtual interface file to the clock generation module through the parameter transmission mechanism of UVM, so as to provide the corresponding relationship of the clock port for the subsequent generation of the clock signal by the clock generation module.
[0022] Step S400, generating a corresponding clock signal according to the clock virtual interface file at the top level of the UVM verification platform and the parameter information of each clock of the design to be tested; in this step, as described above, the test case contains various parameter information of the design to be tested, and naturally also contains the clock parameter information of the design to be tested, therefore, the parameter information of each clock of the design to be tested is transmitted to the clock generating module through the test case, and the clock generating module does not need to be directly connected to the design to be tested to obtain the required clock parameter information, and generates a corresponding clock according to the received parameter information of each clock, thereby avoiding interference with the design to be tested during the verification process, and ensuring the accurate implementation of the verification process, wherein the parameter information of the clock includes but is not limited to the frequency, phase, amplitude and other information of the clock, of course, in the present invention, the main parameter used is the frequency of the clock, and other parameters are not further explained, that is, the clock generating module Module generates the clock signal of the same frequency as the clock parameter corresponding to the verification use case; In addition, in this step, to ensure that the clock generation module UVM verification platform top layer communicates accurately, the clock generation module sends the clock signal generated to the UVM verification platform top layer by the parameter transmission mechanism of UVM, as mentioned above, the corresponding relationship between the clock port of the design to be tested and the virtual interface of the UVM verification platform top layer is defined in the clock virtual interface file, that is, the corresponding relationship between the clock signal of each different frequency of the design to be tested and the virtual interface of the UVM verification platform top layer is specified, therefore the clock generation module is according to the clock virtual interface file of the UVM verification platform top layer, the clock signal generated by it is one-to-one corresponding to the virtual interface of the UVM verification platform top layer, and the clock signal generated is sent to the UVM verification platform top layer, so that the clock signal can be transmitted on the virtual interface of the UVM verification platform top layer.
[0023] Step S500, input the generated clock signal to the corresponding clock port of the design to be tested according to the clock virtual interface file; in this step, the virtual interface of the top layer of the UVM verification platform is connected to the clock port of the design to be tested in a one-to-one correspondence, so the top layer of the UVM verification platform can transmit the received clock signal to the clock port corresponding to the design to be tested through the virtual interface according to the clock virtual interface file; so that the design to be tested obtains the clock signal required for its verification, and the verification process can be carried out normally.
[0024] In summary, the method for generating controllable clock based on UVM of the present invention, the clock virtual interface file defining the corresponding relationship between the clock port of the design to be tested and the virtual interface of the top layer of the UVM verification platform is not arranged at the top layer of the UVM verification platform, and the clock virtual interface file is declared to the top layer of the UVM verification platform for use, so there is no need to modify the top layer file of the UVM verification platform to generate various clock signals required for the design to be tested, so that the generation of the clock signal required for the design to be tested is more efficient and faster; at the same time, the clock virtual interface file is not arranged at the top layer of the UVM verification platform, so there is no need to occupy the length of the top layer file, and the situations of various clocks can all be included, covering the clock signals of various frequencies required in the verification process of the design to be tested, so that the verification process is more comprehensive, and the verification result is more accurate;
[0025] The present invention has been described above in conjunction with the best embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations based on the essence of the present invention.
Claims
1. A method for generating a controllable clock based on UVM, characterized in that, The steps include: a. Obtain parameter information and clock port information of each clock of the design to be tested; b. Write a clock virtual interface file based on the clock port information of the design to be tested; c. Declare the clock virtual interface file to the top level of the UVM verification platform; d. Generate corresponding clock signals according to the clock virtual interface file at the top level of the UVM verification platform and the parameter information of each clock of the design to be tested; e. Input the generated clock signal to the corresponding clock port of the design under test according to the clock virtual interface file.
2. The method for generating a controllable clock based on UVM according to claim 1, wherein: Each clock in the design under test corresponds to its clock port one by one.
3. The method for generating a controllable clock based on UVM as claimed in claim 2, characterized in that, The clock virtual interface file defines the corresponding relationship between the clock port of the design to be tested and the virtual interface of the top layer of the UVM verification platform.
4. The method for generating a controllable clock based on UVM as claimed in claim 2, characterized in that, In the step c, the UVM verification platform top layer sends the declared clock virtual interface file to the clock generation module, and connects the clock virtual interface of the UVM verification platform top layer to the clock port of the design to be tested according to the clock virtual interface file.
5. The method for generating a controllable clock based on UVM as claimed in claim 4, characterized in that: In the step c, the top layer of the UVM verification platform sends the declared clock virtual interface file to the clock generation module through the parameter transmission mechanism of UVM.
6. The method for generating a controllable clock based on UVM as claimed in claim 4, characterized in that: In the step d, the test case transmits the parameter information of each clock of the design to be tested to the clock generation module, and the clock generation module generates a clock of corresponding frequency according to the received parameter information of each clock.
7. The method for generating a controllable clock based on UVM as claimed in claim 6, characterized in that: In the step d, the clock generation module sends the generated clock signal to the top layer of the UVM verification platform through the parameter transmission mechanism of UVM.
8. The method for generating a controllable clock based on UVM as claimed in claim 7, characterized in that: In the step e, the top layer of the UVM verification platform transmits the received clock signal to the clock port corresponding to the design under test through the virtual interface according to the clock virtual interface file.