Method and device for automatically generating register model, medium and product

Abstract

The invention provides a method and device for automatically generating a register model, a medium and a product, the method is applied to an automatic generation program, and the method comprises the steps that a user-defined template is read, and the user-defined template comprises first register description information filled in in a set format; analyzing first register description information from the self-defined template according to an analysis mode matched with the set format; and generating a corresponding first register model according to the first register description information. According to the technical scheme provided by the embodiment of the invention, the generation template can be subjected to custom editing, so that the register generation efficiency and accuracy are improved based on the custom template, and the flexibility, expandability, mobility and the autonomous controllable degree of the verification process are improved.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a method for automatically generating a register model, an electronic device, a storage medium, and a computer program product. Background Art

[0002] Registers are storage units used to store data in chips to implement specific functions. With the continuous advancement of process technology, chip design has become increasingly complex, and the number of registers required inside them has also increased. For example, for some system-on-chips (SoCs), the number of registers can reach tens of thousands. Once such a large number of registers go wrong, serious problems will occur in the chip. Therefore, register verification is required during the chip development stage.

[0003] When verifying a chip, it is necessary to build a register model for abstracting the chip registers. Currently, the method for building a register model is mainly for technicians to manually write the register model, which is inefficient and prone to errors. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a method, an electronic device, and a storage medium for automatically generating a register model.

[0005] According to one aspect of the present disclosure, a method for automatically generating a register model is provided, which is applied to automatically generating a program, comprising: reading a custom template, the custom template comprising: first register description information filled in a set format; parsing the first register description information from the custom template according to a parsing method matching the set format; and generating a corresponding first register model according to the first register description information.

[0006] In a possible implementation, the method further includes: in response to an editing operation on the custom template, reading the custom template to generate a second register model; wherein the editing operation includes: filling in the second register description information in the set format.

[0007] In a possible implementation, the custom template includes: a table; the setting format includes: each column corresponds to a custom field, and in each row, at least some of the cells corresponding to the custom fields are filled with field values; the parsing method includes: determining the custom information corresponding to each row based on whether each cell in each row is filled with field values, and based on the field values ​​filled in the cells; and obtaining register description information based on the custom information corresponding to each row.

[0008] In a possible implementation, when the register model to be generated is a universal verification methodology register model UVM, the custom fields include at least one or more of a block name field, a tag field, a block base address field, a register offset address field, a register name field, a domain name field, a start bit field, a data access type field, a reset flag field, a reset value field, and a backdoor path field.

[0009] In a possible implementation, the cells corresponding to at least some of the custom fields in each row are filled with field values, including: at least the cells corresponding to the label field in each row are filled with field values; if the label field fill value of this row corresponds to the register block level of UVM, then at least the cells corresponding to the block name field and the block base address field in this row are filled with corresponding field values; if the label field fill value of this row corresponds to the register level of UVM, then at least the cells corresponding to the register offset address field and the register name field in this row are filled with corresponding field values; if the label field fill value of this row corresponds to the domain level of UVM, then at least the cells corresponding to the domain name field and the start bit field in this row are filled with corresponding field values.

[0010] In a possible implementation manner, each of the custom fields further includes: at least one extended function field.

[0011] In a possible implementation, the parsing method according to the set format matching is used to parse the first register description information from the custom template, including: parsing the non-header line of the custom template, and determining the UVM class hierarchy corresponding to each line according to the fill value corresponding to the label field in each line; instantiating the custom information corresponding to each line according to the UVM class hierarchy corresponding to each line and the field values ​​filled in other custom fields of the line; traversing the custom information corresponding to each line to obtain the first register description information; the UVM class hierarchy at least includes: a register block hierarchy, a register hierarchy, and a domain hierarchy.

[0012] In a possible implementation, generating a corresponding first register model according to the first register description information includes: obtaining a first register model file based on a generation function and the first register description information; and generating a first register model based on the first register file.

[0013] In a possible implementation, the first register description information further includes mapping information for characterizing a mapping relationship between UVM class hierarchies corresponding to each row.

[0014] According to another aspect of the present disclosure, there is provided an apparatus for automatically generating a register model, comprising: a reading module for reading a custom template, the custom template comprising: first register description information filled in a set format; a parsing module for parsing the first register description information from the custom template according to a parsing method matching the set format; and a generating module for generating a corresponding first register model according to the first register description information.

[0015] According to another aspect of the present disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor implements the method provided in any embodiment of the present disclosure when executing the computer program.

[0016] According to another aspect of the present disclosure, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the method provided by any embodiment of the present disclosure is implemented.

[0017] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the method provided in any embodiment of the present disclosure is implemented.

[0018] In the technical solution provided by the embodiment of the present disclosure, since the custom template includes the first register description information filled in the set format, the automatic generation program can automatically parse the first register description information from the custom template according to the parsing method matching the set format, and automatically generate the corresponding first register model. On the one hand, this method of automatically generating a register model can reduce the workload of manual writing and improve the efficiency of register writing, generation efficiency and accuracy; on the other hand, since the generated template can be customized and edited, the flexibility is improved, and the register model file can be generated without relying on EDA software. It can adapt to a variety of verification methods, has strong portability and compatibility, and can further improve the degree of autonomy and controllability of the verification process.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in accordance with the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0021] Figure 1 A flowchart of a method for automatically generating a register model provided in an embodiment of the present disclosure.

[0022] Figure 2a , Figure 2b , Figure 3a , Figure 3b This is an example diagram of a custom template for an exemplary application scenario of an embodiment of the present disclosure.

[0023] Figure 4 A flowchart of a method for parsing first register description information in an exemplary application scenario of an embodiment of the present disclosure;

[0024] Figure 5 A schematic diagram of an automatically generated register model provided by an embodiment of the present disclosure.

[0025] Figure 6 A block diagram of an electronic device provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and descriptions are considered to be illustrative and non-restrictive in nature.

[0027] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0028] To facilitate understanding of the technical solutions of the embodiments of the present disclosure, the related technologies of the embodiments of the present disclosure are described below. The following related technologies can be arbitrarily combined with the technical solutions of the embodiments of the present disclosure as optional solutions, and they all belong to the protection scope of the embodiments of the present disclosure. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present disclosure.

[0029] In the process of chip design, in order to improve the design and verification, it is necessary to constantly modify the register data, such as the register address, the initial value of the field, the field length, etc. The corresponding verification code also needs to be modified, which leads to a large amount of repetitive iterative work. When verifying the chip, it is necessary to build a register model for abstracting the chip registers. The current method of building a register model is mainly for technicians to manually write the register model, which is inefficient and prone to errors.

[0030] In the related art, a verification method based on the register abstraction layer (RAL) mechanism is proposed. Based on the RAL mechanism, a register model can be easily established for chip simulation, thereby reducing the workload of verification engineers and improving the efficiency of register verification. For example: a UVM register model based on the Universal Verification Methodology (UVM); or a VMM register model based on the VMM (Verification Methodology Manual) verification methodology; or an OVM register model based on the Open Verification Methodology (OVM), etc.

[0031] Taking UVM as an example, in the chip verification process, the configuration process of registers depends on the UVM register model. The UVM register model is mainly composed of three types: blocks, registers, and fields. There is an inclusion relationship between the three, that is, in the register model, a block contains several registers, and a register contains several fields. When there are many registers of the module to be verified, there will be hundreds of classes in the register model, and the verifier needs to manually write these classes according to the registers of the specific module to be verified, which is arduous and inefficient.

[0032] In the related art, the file format specified by the Electronic Design Automation (EDA) software can be generated, and then the register model can be generated by the script provided by the EDA software. This method is highly dependent on the EDA software, and the degree of autonomy and controllability of the verification process is low. However, if a different EDA software is used, the existing verification mode or register model may not be adapted.

[0033] Figure 1A flowchart of a method for automatically generating a register model according to an embodiment of the present disclosure is shown. The method can be applied to an automatic generation program, that is, the method for automatically generating a register model is implemented by the automatic generation program. The automatic generation program is a software or tool that can automatically execute the method for automatically generating a register model according to the embodiment of the present disclosure, that is, automatically parse the first register description information from the custom template, and automatically generate the corresponding first register model, so as to reduce the need for manual coding and possible human errors, thereby improving the efficiency and accuracy of register generation. Figure 1 As shown, the method includes steps S101, S102 and S103.

[0034] Step S101: reading a custom template, wherein the custom template includes: first register description information filled in a set format.

[0035] The custom template described in the embodiment of the present disclosure may be a structured document or file. In the field of hardware design and verification, the custom template described in the embodiment of the present disclosure may be filled in according to a set format and may be used to describe register attribute information, such as name, bit width, offset address, reset value, access type, etc. The embodiment of the present disclosure does not limit the specific form of the custom template. The set format mainly refers to the structure and rules for defining the register description information.

[0036] Step S102: parsing the first register description information from the custom template according to the parsing method of the set format matching.

[0037] The parsing method refers to a method of extracting and understanding information according to certain preset rules, and the parsing method needs to match the set format, that is, extracting and understanding the register description information in a manner that matches the structure and rules of the register description information. The first register description information can be the total description information containing the register attribute data in all custom templates.

[0038] Step S103: Generate a corresponding first register model according to the first register description information.

[0039] Among them, the register model can be a UVM register model, a VMM register model, or an OVM register model. The embodiment of the present application does not limit the type of specific register model used and can be set according to actual needs.

[0040] Based on this technical solution, since the custom template includes the first register description information filled in the set format, the automatic generation program can automatically parse the first register description information from the custom template according to the parsing method that matches the set format, and automatically generate the corresponding first register model. On the one hand, this method of automatically generating a register model can reduce the workload of manual writing and improve the efficiency of register writing, generation efficiency and accuracy; on the other hand, since the generated template can be customized and edited, the flexibility is improved, and the register model file can be generated without relying on EDA software. It can adapt to a variety of verification methods, has strong portability and compatibility, and can further improve the degree of autonomy and controllability of the verification process.

[0041] In a possible implementation, the custom template includes a table; the setting format includes: each column corresponds to a custom field, and in each row, at least some of the cells corresponding to the custom fields are filled with field values; the parsing method includes: determining the custom information corresponding to each row according to whether each cell in each row is filled with field values, and according to the field values ​​filled in the cells; and obtaining register description information according to the custom information corresponding to each row.

[0042] Exemplarily, the table may be xml or csv, and the custom template may be a file in xml format or a file in csv format, which is not limited in the embodiments of the present disclosure.

[0043] Exemplarily, the custom field may include a tag field, which can be used to identify the register model level corresponding to each row, and may also include register (reg) related attribute fields, such as register name field, register offset address field, etc., and domain (field) related attribute fields, such as domain name field, start bit field, data access type field, reset flag field field, reset value field, etc. The custom field may also include block (block) related attribute fields, such as block name, block name field, block base address field, etc. The specific type and quantity of the custom field can be defined by the developer, and the embodiment of the present disclosure does not limit this.

[0044] Exemplarily, in a custom template, each column corresponds to a custom field, and in each row, at least some of the cells corresponding to the custom fields are filled with field values. The value filled in the cell can be specific data corresponding to the custom field, such as block name, label, block base address, register offset address, register name, domain name, start bit, data access type, reset value, backdoor path, etc., and specific data corresponding to the custom field, such as label data (located in the column where the cell of the label field is located). Furthermore, in each row, at least some of the cells corresponding to the custom fields are filled with field values.

[0045] Exemplarily, the parsing method may be to determine the custom information corresponding to each row according to whether each cell in each row is filled with a field value and according to the field value filled in the cell; and obtain the register description information according to the custom information corresponding to each row.

[0046] Based on this technical solution, the automatic generation program can automatically parse the first register description information from the custom template according to the parsing method of the set format matching, and automatically generate the corresponding first register model. On the one hand, this method of automatically generating register models can reduce the workload of manual writing and improve the efficiency of register writing, generation efficiency and accuracy; on the other hand, since the custom template can be customized and edited, the flexibility is improved, it has strong portability and compatibility, and can further improve the degree of autonomy and controllability of the verification process.

[0047] In a specific embodiment, the register model level corresponding to each row can be determined according to the fill value corresponding to the label field in each row; the custom information corresponding to each row can be instantiated according to the register model level corresponding to each row and the field values ​​filled in other custom fields in the row; and the first register description information can be obtained by traversing the custom information corresponding to each row.

[0048] Among them, different register model levels may have an inclusion relationship, and the register information of the row may be instantiated according to the register model level corresponding to each row and the field values ​​filled in other custom fields of the row to obtain the custom information corresponding to each row. The first register description information may also include mapping information for characterizing the mapping relationship between the UVM class levels corresponding to each row.

[0049] In this way, the embodiment of the present disclosure can improve the efficiency of register generation based on the custom template, improve flexibility, and have strong portability and compatibility. Further, the present disclosure can improve the degree of autonomy and controllability of the verification process.

[0050] In a possible implementation, generating a corresponding first register model according to the first register description information includes: adding the first register description information to a generation function to obtain a first register model file; and generating a first register model based on the first register file.

[0051] The generation function may be a build function, a rand function, a new function or other custom function defined in a Python script in a block class, a reg class or a field class or other classes. The disclosed embodiment does not limit the specific type of the generation function used. The generation function may generate a first register model file according to the first register description information, and the register model file may be a file that conforms to the corresponding register model format.

[0052] In this way, the embodiment of the present disclosure can automatically generate a register model, reduce the workload of manual writing, and improve the efficiency and accuracy of register writing; on the other hand, the embodiment of the present disclosure can improve the efficiency of register generation based on a custom template, improve flexibility, and have strong portability and compatibility. Furthermore, the present disclosure can improve the degree of autonomy and controllability of the verification process.

[0053] In a possible implementation, the method further includes: in response to an editing operation on the custom template, reading the custom template to generate a second register model; wherein the editing operation includes: filling in the second register description information in the set format.

[0054] Among them, the embodiment of the present disclosure can perform editing operations on the custom template, and can add, delete, modify, etc. operations on the custom template according to the set format, including but not limited to adding, deleting, modifying, etc. operations on the custom fields in the custom template and the fill values ​​of the cells corresponding to the custom fields. The embodiment of the present disclosure does not limit the editing operation method and object of the custom template. In a specific embodiment, in response to the editing operation on the custom template, the custom template can be read to generate a second register model.

[0055] In this way, the embodiment of the present disclosure can customize the generated template and improve the efficiency of register generation based on the customized template, improve flexibility, and have strong portability and compatibility. Further, the present disclosure can improve the degree of autonomy and controllability of the verification process.

[0056] Figure 2a , Figure 2b , Figure 3a , Figure 3b An example diagram of a custom template for an exemplary application scenario according to an embodiment of the present disclosure is shown.

[0057] In a possible implementation, when the register model to be generated is a universal verification methodology register model UVM, each custom field includes at least:

[0058] One or more of the block name field, tag field, block base address field, register offset address field, register name field, domain name field, start bit field, data access type field, reset flag field, reset value field, and backdoor path field.

[0059] Among them, Figures 2a to 3b In the custom template shown, the cell fill values ​​of the header row (usually the first row) can be various custom fields. Further, the various custom fields can include a label field, which can be used to identify the register model level corresponding to each row, and can also include register (reg) related attribute fields, such as register name field, register offset address field, etc., and domain (field) related attribute fields, such as domain name field, start bit field, data access type field, reset flag field, reset value field, etc. The custom fields can also include block (block) related attribute fields, such as block name, block name field, block base address field, etc. Therefore, based on these custom fields of the header row, the type of each cell fill value in each non-header row can be intuitively obtained.

[0060] Exemplarily, in a custom template, each column corresponds to a custom field, and in each row, at least some of the cells corresponding to the custom fields are filled with field values. The value filled in the cell can be specific data corresponding to the custom field, such as block name, label, block base address, register offset address, register name, domain name, start bit, data access type, reset value, backdoor path, etc., and specific data corresponding to the custom field, such as label data (located in the column where the cell of the label field is located). Furthermore, in each row, at least some of the cells corresponding to the custom fields are filled with field values.

[0061] In a possible implementation manner, each of the custom fields further includes: at least one extended function field.

[0062] In addition to the field types that each custom field should at least include, each custom field may also include at least one extended function field. The extended function field may be used to implement other extended functions such as register verification and logic calculation. The specific form and specific implementation function of the extended function field are not limited in the embodiment of the present disclosure.

[0063] In this way, the embodiment of the present disclosure can customize the generated template, thereby improving the register generation efficiency based on the customized template, improving the scalability, and being able to adapt to a variety of verification methods, with strong portability and compatibility. Further, the present disclosure can improve the degree of autonomy and controllability of the verification process.

[0064] In a possible implementation, when the register model to be generated is a universal verification methodology register model UVM, the cells corresponding to at least some of the custom fields in each row are filled with field values, including: at least the cells corresponding to the label field in each row are filled with field values; if the label field fill value of this row corresponds to the register block level of UVM, then at least the cells corresponding to the block name field and the block base address field in this row are filled with corresponding field values; if the label field fill value of this row corresponds to the register level of UVM, then at least the cells corresponding to the register offset address field and the register name field in this row are filled with corresponding field values; if the label field fill value of this row corresponds to the domain level of UVM, then at least the cells corresponding to the domain name field and the start bit field in this row are filled with corresponding field values.

[0065] For example, in Figures 2a to 3b In the custom template shown, in each non-header row, at least the cell corresponding to its label field is filled with a field value. If the label field filling value of this row corresponds to the register block level of the UVM model, then at least the cell corresponding to the block name field and the block base address field in this row is filled with the corresponding field value; if the label field filling value of this row corresponds to the register level of the UVM, then at least the cell corresponding to the register offset address field and the register name field in this row is filled with the corresponding field value; if the label field filling value of this row corresponds to the domain level of the UVM, then at least the cell corresponding to the domain name field and the start bit field in this row is filled with the corresponding field value. Further, the register model level corresponding to each row can be determined according to the filling value corresponding to the label field of each row in the custom template shown in Figures 2 and 3; according to the register model level corresponding to each row, and the field values ​​filled in other custom fields of the row, the custom information corresponding to each row is instantiated.

[0066] In this way, the embodiment of the present disclosure can automatically generate a register model on the one hand, improving the efficiency and accuracy of register writing; on the other hand, the embodiment of the present disclosure can improve the efficiency of register generation based on a custom template, improve flexibility, and have strong portability and compatibility. Furthermore, the present disclosure can improve the degree of autonomy and controllability of the verification process.

[0067] Figure 4 FIG. 1 shows a flow chart of a method for parsing first register description information according to an exemplary application scenario of an embodiment of the present disclosure. Figure 4 As shown, the method includes steps S401, S402 and S403.

[0068] In a possible implementation, the parsing the first register description information from the custom template according to the parsing method matching the set format includes:

[0069] Step S401: parsing the non-header rows of the custom template, and determining the UVM class hierarchy corresponding to each row according to the fill value corresponding to the tag field in each row.

[0070] Step S402: according to the UVM class hierarchy corresponding to each row and the field values ​​filled in other custom fields of the row, instantiate the custom information corresponding to each row.

[0071] Step S403: traverse the custom information corresponding to each row to obtain the first register description information.

[0072] Exemplarily, a python script can be used to parse the cell information of the remaining rows except the title row, and the UVM class hierarchy corresponding to each row can be determined according to the fill value corresponding to the label field of the corresponding row. Wherein, the UVM class hierarchy at least includes: register block hierarchy, register hierarchy, and domain hierarchy. The disclosed embodiment does not limit the number of specifically selected UVM class hierarchies. After determining the UVM class hierarchy corresponding to each row, the register information recorded in the row can be instantiated into corresponding block class, reg class or field class objects according to the UVM class hierarchy corresponding to each row, that is, the corresponding block hierarchy, reg hierarchy or field hierarchy, and the field values ​​filled in other custom fields of the row, that is, instantiated into custom information corresponding to each row. Further, the custom information corresponding to each row can be traversed to obtain the first register description information. Wherein, the first register description information can be the total description information containing all block data.

[0073] In a possible implementation, the first register description information further includes mapping information for characterizing a mapping relationship between UVM class hierarchies corresponding to each row. Generating a corresponding first register model according to the first register description information includes: adding the first register description information to a generation function to obtain a first register model file; and generating a first register model based on the first register file.

[0074] The generation function can be a build function, rand function, new function or other custom function defined in a python script in a block class, a reg class or a field class or other classes. The first register description information is added to the generation function to obtain a first register model file, such as a .sv file.

[0075] For example, the code of the build function may be:

[0076] virtual function void build():

[0077] field0=uvm_btc_field::type_id::create("field0")

[0078] field0.configure(this,8,0,"RO",0,8'h0,1,1,1);

[0079] endfunction.

[0080] The code of the New function can be:

[0081] runction new(string name=reg_test4_type);

[0082] super.new(name,32,UVM_CVR_REG_BITS);

[0083] if(has_coverage(UVM_CVR_REG_BITS))

[0084] cg_bits = new();

[0085] endfunction:new.

[0086] In this way, the disclosed embodiment can customize the generated template, thereby improving the register generation efficiency based on the customized template, improving flexibility, and generating register model files without relying on EDA software, and can adapt to a variety of verification methods, with strong portability and compatibility. Further, the disclosed embodiment can improve the degree of autonomy and controllability of the verification process.

[0087] Corresponding to the method provided in the embodiment of the present disclosure, the embodiment of the present disclosure provides a device for automatically generating a register model. Figure 5 As shown, the automatic register model generation device may include: a reading module 501, used to read a custom template, the custom template including: first register description information filled in a set format; a parsing module 502, used to parse the first register description information from the custom template according to a parsing method matching the set format; a generating module 503, used to generate a corresponding first register model according to the first register description information.

[0088] In one embodiment, the device further includes: an editing module for reading the custom template to generate a second register model in response to an editing operation on the custom template; wherein the editing operation includes: filling in the second register description information in the set format.

[0089] In one embodiment, the custom template includes: a table; the setting format includes: each column corresponds to a custom field, and in each row, at least some of the cells corresponding to the custom fields are filled with field values; the parsing module is also used to: determine the custom information corresponding to each row based on whether each cell in each row is filled with field values, and based on the field values ​​filled in the cells; and obtain register description information based on the custom information corresponding to each row.

[0090] In one embodiment, when the register model to be generated is a universal verification methodology register model UVM, the custom fields include at least one or more of a block name field, a tag field, a block base address field, a register offset address field, a register name field, a domain name field, a start bit field, a data access type field, a reset flag field, a reset value field, and a backdoor path field.

[0091] In one embodiment, a custom template setting module is also included, which is used to: fill at least the cell corresponding to the label field in each row with a field value; if the label field fill value of this row corresponds to the register block level of UVM, then at least the cells corresponding to the block name field and the block base address field in this row are filled with corresponding field values; if the label field fill value of this row corresponds to the register level of UVM, then at least the cells corresponding to the register offset address field and the register name field in this row are filled with corresponding field values; if the label field fill value of this row corresponds to the domain level of UVM, then at least the cells corresponding to the domain name field and the start bit field in this row are filled with corresponding field values.

[0092] In one implementation, each of the custom fields further includes: at least one extended function field.

[0093] In one embodiment, the parsing module 502 is further used to: parse the non-header row of the custom template, and determine the UVM class hierarchy corresponding to each row according to the fill value corresponding to the label field in each row; instantiate the custom information corresponding to each row according to the UVM class hierarchy corresponding to each row and the field values ​​filled in other custom fields in the row; traverse the custom information corresponding to each row to obtain the first register description information; the UVM class hierarchy at least includes: a register block hierarchy, a register hierarchy, and a domain hierarchy.

[0094] In one implementation, the generating module 503 is further configured to: add the first register description information to the generating function to obtain a first register model file; and generate a first register model based on the first register file.

[0095] In one implementation, the first register description information further includes mapping information for characterizing a mapping relationship between UVM class hierarchies corresponding to each row.

[0096] The functions of each module in each device of the embodiment of the present disclosure can be referred to the corresponding description in the above method, and have corresponding beneficial effects, which will not be repeated here.

[0097] Figure 6 FIG. 1 is a block diagram of an electronic device used to implement an embodiment of the present application. Figure 6 As shown, the electronic device includes: a memory 601 and a processor 602. The memory 601 stores a computer program that can be run on the processor 602. When the processor 602 executes the computer program, the method in the above embodiment is implemented. The number of the memory 601 and the processor 602 can be one or more.

[0098] The electronic device also includes:

[0099] The communication interface 603 is used to communicate with external devices and perform data exchange transmission.

[0100] If the memory 601, the processor 602 and the communication interface 603 are implemented independently, the memory 601, the processor 602 and the communication interface 603 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0101] Optionally, in a specific implementation, if the memory 601, the processor 602 and the communication interface 603 are integrated on a chip, the memory 601, the processor 602 and the communication interface 603 can communicate with each other through an internal interface.

[0102] An embodiment of the present application provides a computer-readable storage medium storing a computer program, which implements the method provided in the embodiment of the present application when the program is executed by a processor.

[0103] An embodiment of the present application also provides a chip, which includes a processor for calling and executing instructions stored in the memory from the memory, so that a communication device equipped with the chip executes the method provided by the embodiment of the present application.

[0104] An embodiment of the present application also provides a chip, including: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the processor is used to execute the method provided in the embodiment of the application.

[0105] It should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting the Advanced RISC Machines (ARM) architecture.

[0106] Optionally, the above-mentioned memory may include a read-only memory and a random access memory, and may also include a non-volatile random access memory. The memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may include a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may include a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example: Static RAM (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Sync Link DRAM (SLDRAM) and Direct Rambus RAM (DRRAM).

[0107] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium.

[0108] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0109] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features.

[0110] Any process or method description in the flow chart or otherwise described herein can be understood to represent a module, fragment or portion of a code including one or more executable instructions for implementing the steps of a specific logical function or process. And the scope of the preferred embodiment of the present application includes other implementations, in which the functions may not be performed in the order shown or discussed, including in a substantially simultaneous manner or in a reverse order according to the functions involved.

[0111] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or used in combination with these instruction execution systems, devices or apparatuses.

[0112] It should be understood that the various parts of the present application can be implemented with hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented with software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the above embodiment method can be completed by instructing the relevant hardware through a program, which can be stored in a computer-readable storage medium, and when the program is executed, it includes one of the steps of the method embodiment or a combination thereof.

[0113] In addition, each functional unit in each embodiment of the present application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. If the above-mentioned integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium can be a read-only memory, a disk or an optical disk, etc.

[0114] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for automatically generating a register model, applied to automatically generating a program, the method comprising: Reading a custom template, the custom template comprising: first register description information filled in a set format; Parsing the first register description information from the custom template according to the parsing method matched with the set format; A corresponding first register model is generated according to the first register description information.

2. The method according to claim 1, characterized in that The method further comprises: In response to an editing operation on the custom template, the custom template is read to generate a second register model; wherein the editing operation includes: filling in the second register description information in the set format.

3. The method according to claim 1, characterized in that The custom template includes: a table; The setting format includes: each column corresponds to a custom field, and in each row, at least some cells corresponding to the custom fields are filled with field values; The parsing method includes: determining the custom information corresponding to each row according to whether each cell in each row is filled with a field value and according to the field value filled in the cell; and obtaining register description information according to the custom information corresponding to each row.

4. The method according to claim 3, characterized in that In the case where the register model to be generated is a universal verification methodology register model UVM, each of the custom fields includes at least: One or more of the block name field, tag field, block base address field, register offset address field, register name field, domain name field, start bit field, data access type field, reset flag field, reset value field, and backdoor path field.

5. The method according to claim 4, characterized in that The cells corresponding to at least some of the custom fields in each row are filled with field values, including: In each row at least the cell corresponding to the label field is filled with the field value; If the value filled in the label field of this row corresponds to the register block hierarchy of UVM, then at least the cells corresponding to the block name field and the block base address field in this row are filled with the corresponding field values; If the value filled in the label field of this row corresponds to the register hierarchy of UVM, then at least the cells corresponding to the register offset address field and the register name field in this row are filled with the corresponding field values; If the fill value of the label field of this row corresponds to the domain hierarchy of UVM, then at least the cells corresponding to the domain name field and the start bit field in this row are filled with the corresponding field values.

6. The method according to claim 4, characterized in that The custom fields also include: At least one extended function field.

7. The method according to claim 5, characterized in that Parsing the first register description information from the custom template according to the parsing method matched with the set format includes: Parse the non-header rows of the custom template, and determine the UVM class hierarchy corresponding to each row according to the fill value corresponding to the tag field in each row; According to the UVM class hierarchy corresponding to each row and the field values ​​filled in other custom fields of the row, instantiate the custom information corresponding to each row; Traverse the custom information corresponding to each row to obtain the first register description information; The UVM class hierarchy at least includes: a register block hierarchy, a register hierarchy, and a domain hierarchy.

8. The method according to claim 7, generating a corresponding first register model according to the first register description information, comprising: Add the first register description information to the generation function to obtain the first register model file; Based on the first register file, a first register model is generated.

9. The method according to claim 7, wherein: The first register description information also includes mapping information, which is used to characterize the mapping relationship between the UVM class hierarchies corresponding to each row.

10. A device for automatically generating a register model, characterized in that: The device comprises: A reading module, used for reading a custom template, wherein the custom template includes: first register description information filled in a set format; A parsing module, configured to parse the first register description information from the custom template according to the parsing method matched with the set format; A generating module is used to generate a corresponding first register model according to the first register description information.

11. An electronic device comprising a memory, a processor and a computer program stored in the memory, wherein the processor implements the method according to any one of claims 1 to 9 when executing the computer program.

12. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

13. A computer program product, comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 9.

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