AI circuit design method and system based on RISC-V instruction extension

Abstract

The invention discloses an AI circuit design method and system based on RISC-V instruction extension, and the method comprises the steps: designing an AI calculation circuit structure, storing a weight coefficient and temporary data generated by an AI calculation circuit in an FIFO in an FPGA, and directly obtaining the weight coefficient and the temporary data from the FIFO when the next round of operation is carried out; after the FIFO reaches the capacity of the FIFO, a write operation is started, and the weight coefficient stored in the FIFO and the temporary data are written into the MEM; an AI expansion instruction is designed based on an RISC-V open source instruction set, the structure of an AI calculation circuit is combined with the AI expansion instruction, and software and hardware coordination action of MEM, CPU, AI and FIFO circuits is achieved. According to the invention, the AI instruction and the hardware circuit are effectively utilized, so that the MEM reading frequency is reduced, and the running speed of the system is obviously improved; meanwhile, through an integrated instruction design circuit, the instruction density is improved, and power consumption is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of artificial intelligence chip design, and specifically relates to an AI circuit design method and system based on RISC-V instruction extension. Background Art

[0002] The von Neumann architecture, also known as the Princeton architecture, is a memory structure that combines program instruction memory and data memory. The program instruction storage address and the data storage address point to different physical locations of the same memory. Figure 1 As shown in the figure, the traditional von Neumann architecture includes ALU (logic operation unit), CPU controller, internal data bus, PC (program counter) and various registers, and completes the algorithm processing through the computing circuit ALU in the form of instructions. The way to improve efficiency is to increase the main frequency and increase the number of instructions executed per unit time; the second is to simplify the instructions.

[0003] In order to break the bottleneck of the von Neumann computing architecture and reduce the overhead caused by data movement, the scientific community has made many improvements and attempts. The most direct approach is to increase the data bus bandwidth or clock frequency, but this will inevitably bring greater power consumption and hardware cost overhead, and its scalability is also severely limited. The mainstream solution currently used in FPGA design in the industry is to achieve high-speed and high-bandwidth data communication through a high-speed DDR interface.

[0004] In the related existing technologies, semi-customized chips based on FPGA hardware have good flexibility, but obvious disadvantages, such as high price, complex programming, and insufficient overall computing power. At present, domestic AI chip companies such as DeePhi Technology can provide semi-customized chip solutions based on FPGA. Figure 2 As shown, the FPGA has a built-in CPU and AI acceleration circuit. The CPU usually uses ARM, MIPS and other architectures, and the AI ​​circuit has a built-in multiplication and addition logic unit. The CPU instructions and the AI ​​circuit interact through MEM. During the program running process, there are a large number of MEM read operations, and the acquisition, execution, and access of instruction data are stored in MEM. The above solution will inevitably bring power consumption and cost overhead, and it is difficult to apply to AIoT devices with limited energy consumption and cost at the edge terminal. It does not change the problem of separation of data storage and data processing, so it can only alleviate it to a certain extent, but it cannot fundamentally solve the bottleneck of the von Neumann computing architecture. Because the CPU uses instruction sets such as ARM and MIPS, it is not open enough and the instruction expansion is limited. On the other hand, the storage resources inside the FPGA are not effectively utilized, and the performance of the computing circuit is limited. Summary of the invention

[0005] The purpose of the present invention is to provide an AI circuit design method and system based on RISC-V instruction extension to address the problems in the above-mentioned prior art, so as to realize the effective utilization of AI instructions and hardware circuits, reduce the number of times MEM is read, and significantly improve the operating speed of the system; at the same time, through the integrated instruction design circuit, the instruction density is improved and the power consumption is reduced.

[0006] In order to achieve the above object, the present invention has the following technical solutions: In a first aspect, a method for designing an AI circuit based on RISC-V instruction extension is provided, comprising: Design the structure of the AI ​​calculation circuit, store the weight coefficients and temporary data generated by the AI ​​calculation circuit in the first-in-first-out data buffer FIFO inside the field programmable gate array FPGA, and directly obtain the weight coefficients and temporary data from the FIFO when performing the next round of calculations; when the FIFO reaches its own capacity, start a write operation to write the weight coefficients and temporary data stored in the FIFO into the MEM memory; AI extension instructions are designed based on the RISC-V open source instruction set, and the structure of the AI ​​computing circuit is combined with the AI ​​extension instructions to achieve the software and hardware coordinated action of MEM memory, CPU, AI computing circuit and first-in-first-out data buffer FIFO circuit.

[0007] As a preferred solution, in the step of designing the structure of the AI ​​computing circuit, the field programmable gate array FPGA is internally provided with a CPU designed based on the RISC-V open source instruction set architecture, a first-in-first-out data buffer FIFO composed of a block random access memory BlockRAM, and an AI computing circuit, and the MEM memory is externally mounted on the field programmable gate array FPGA.

[0008] As a preferred solution, when the FIFO reaches its own capacity, a write operation is initiated to write the weight coefficients and temporary data stored in the FIFO into the MEM memory. The capacity of the FIFO itself includes any one or more combinations of the bit width, depth and number of the FIFO.

[0009] As a preferred solution, in the step of designing AI extended instructions based on the RISC-V open source instruction set, the user-defined instructions in the assembly code of the RISC-V open source instruction set are implemented through pseudo-instructions .insn, and the format is as follows:

[0010] In the formula, .insn is used to inform the compiler that the current instruction is an instruction in .insn format; r is used to specify that the instruction type is R-type; opcode, func3, func7, rd, rs1 and rs2 correspond to the bit fields of the instruction format respectively, among which func3 corresponds to Xs1, Xs2 and Xd, Xs1 is used to describe the depth of the first-in-first-out data buffer FIFO, and Xs2 is used to describe the timing of output to the MEM memory.

[0011] As a preferred solution, in the step of designing an AI extended instruction based on the RISC-V open source instruction set, the designed AI extended instruction is JJ_AI_CAL, the encoding Opcode describes the extended instruction set operation custom0, the value of Xd is 0; the value of Xs1 is 1, describing the first-in-first-out data buffer FIFO depth; the value of Xs2 is 1, describing the timing of output to the MEM memory; the value of Funct7 is 3.

[0012] In a second aspect, an AI circuit design system based on RISC-V instruction extension is provided, including: The AI ​​computing circuit structure design module is used to design the structure of the AI ​​computing circuit, store the weight coefficients and temporary data generated by the AI ​​computing circuit in the first-in-first-out data buffer FIFO inside the field programmable gate array FPGA, and directly obtain the weight coefficients and temporary data from the FIFO when performing the next round of calculations; when the FIFO reaches its own capacity, start a write operation to write the weight coefficients and temporary data stored in the FIFO into the MEM memory; The AI ​​extended instruction design module is used to design AI extended instructions based on the RISC-V open source instruction set, combine the structure of the AI ​​computing circuit with the AI ​​extended instructions, and realize the software and hardware coordinated action of MEM memory, CPU, AI computing circuit and first-in-first-out data buffer FIFO circuit.

[0013] As a preferred solution, in the AI ​​computing circuit structure designed by the AI ​​computing circuit structure design module, the field programmable gate array FPGA is internally provided with a CPU designed based on the RISC-V open source instruction set architecture, a first-in-first-out data buffer FIFO composed of a block random access memory Block RAM, and an AI computing circuit, and the MEM memory is externally mounted on the field programmable gate array FPGA.

[0014] As a preferred solution, when the FIFO reaches its own capacity, the AI ​​computing circuit structure design module starts a write operation to write the weight coefficients and temporary data stored in the FIFO into the MEM memory. The capacity of the FIFO itself includes any one or more combinations of the bit width, depth and number of the FIFO.

[0015] As a preferred solution, when the AI ​​extended instruction design module designs AI extended instructions based on the RISC-V open source instruction set, the user-defined instructions in the assembly code of the RISC-V open source instruction set are implemented through pseudo-instructions .insn, and the format is as follows:

[0016] In the formula, .insn is used to inform the compiler that the current instruction is an instruction in .insn format; r is used to specify that the instruction type is R-type; opcode, func3, func7, rd, rs1 and rs2 correspond to the bit fields of the instruction format respectively, among which func3 corresponds to Xs1, Xs2 and Xd, Xs1 is used to describe the depth of the first-in-first-out data buffer FIFO, and Xs2 is used to describe the timing of output to the MEM memory.

[0017] As a preferred solution, the AI ​​extended instruction designed by the AI ​​extended instruction design module is JJ_AI_CAL, the encoded Opcode describes the extended instruction set operation custom0, the value of Xd is 0; the value of Xs1 is 1, describing the first-in-first-out data buffer FIFO depth; the value of Xs2 is 1, describing the timing of output to MEM memory; the value of Funct7 is 3.

[0018] In a third aspect, an electronic device is provided, comprising a processor and a memory, wherein the processor is used to execute a computer program stored in the memory to implement the AI ​​circuit design method based on RISC-V instruction extension as described in the first aspect.

[0019] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores at least one instruction, and when the at least one instruction is executed by a processor, the AI ​​circuit design method based on RISC-V instruction extension as described in the first aspect is implemented.

[0020] Compared with the prior art, the first aspect of the present invention has at least the following beneficial effects: In order to solve the bottleneck of the traditional von Neumann system architecture and reduce the overhead caused by data movement, without incurring power consumption and hardware cost overhead, the present invention is based on the RISC-V open source instruction set friendly extension technology and integrated circuit technology, etc., and targets the actual application scenarios of the power grid. It utilizes the first-in-first-out data buffer FIFO resources inside the field programmable gate array FPGA, combines the structure of the AI ​​computing circuit with the AI ​​extension instructions, and realizes the software and hardware coordinated action of the MEM memory, CPU, AI computing circuit and the first-in-first-out data buffer FIFO circuit, which reduces the clock frequency requirements, reduces the number of read and write times of the MEM memory, significantly improves the system's operating speed, improves the computing power of the overall circuit, and reduces the system's power consumption.

[0021] It can be understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0023] Figure 1 Schematic diagram of the traditional von Neumann architecture; Figure 2 Schematic diagram of traditional FPGA AI circuit design principles; Figure 3 A schematic diagram of the AI ​​computing circuit structure designed in an embodiment of the present invention; Figure 4 Schematic diagram of the principle of an AI circuit design method based on RISC-V instruction extension in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0025] Artificial intelligence chips are chips specially designed for accelerating intelligent algorithms and models, such as deep learning and machine learning algorithms. For new power systems, a large number of complex intelligent power application scenarios exist in various links such as generation-transmission-transformation-distribution-use. In the future, edge processing and computing will be directly performed in these scenarios, which will greatly reduce the pressure on data centers and reduce operating power consumption, greatly promoting the digitalization and low-carbon development of power grids. Intelligent chips provide computing power support for the large-scale development and deployment of intelligent power applications. In recent years, they have become the focus of research and development for major domestic and foreign top technology companies and universities.

[0026] Traditional computers based on the von Neumann architecture separate the processor and storage. When the central processor processes data, it constantly "moves" data back and forth from the memory through the data bus. The parasitic capacitance and parasitic resistance generated by the data bus will lead to increased system delays and additional energy losses. The serious mismatch between processor performance and storage performance, as well as the delay and power consumption of data transmission through the bus have always restricted the improvement of the overall performance of the computer. Therefore, the development of computers with traditional von Neumann architecture has encountered bottlenecks. The CPU processes artificial intelligence algorithms, uses basic multiplication and addition instruction sets, and performs convolution on images and other basic neural network computing units. The operating efficiency is very low, the CPU occupancy rate is very high, and other instructions cannot be run. Secondary expansion is required through RISC-V instructions.

[0027] At present, the "storage-computing-in-one" technology has not yet been industrialized. Through in-depth research and implementation of this application, storage and computing can be integrated into one, and data does not need to be moved back and forth from the storage device, realizing the combination of storage and computing, and providing an important design method for the system architecture of artificial intelligence chips. In the face of the large-scale application of artificial intelligence in the future, the proposal of this application has significant economic and social benefits for improving the computing power of power grid equipment, improving the intelligence level of equipment, and deriving a large number of edge intelligent applications.

[0028] See also Figure 3 , an embodiment of the present invention proposes an AI circuit design method based on RISC-V instruction extension, including: Design the structure of the AI ​​calculation circuit, store the weight coefficients and temporary data generated by the AI ​​calculation circuit in the first-in-first-out data buffer FIFO inside the field programmable gate array FPGA, and directly obtain the weight coefficients and temporary data from the FIFO when performing the next round of calculations; when the FIFO reaches its own capacity, start a write operation to write the weight coefficients and temporary data stored in the FIFO into the MEM memory; AI extension instructions are designed based on the RISC-V open source instruction set, and the structure of the AI ​​computing circuit is combined with the AI ​​extension instructions to achieve the software and hardware coordinated action of MEM memory, CPU, AI computing circuit and first-in-first-out data buffer FIFO circuit.

[0029] In one possible implementation, when designing the structure of the AI ​​computing circuit in an embodiment of the present invention, the field programmable gate array FPGA is internally provided with a CPU designed based on the RISC-V open source instruction set architecture, a first-in-first-out data buffer FIFO composed of a block random access memory Block RAM, and an AI computing circuit, and the MEM memory is externally mounted on the field programmable gate array FPGA.

[0030] The FIFO (First In, First Out) inside the FPGA (Field Programmable Gate Array) is a first-in, first-out data buffer used to temporarily store and buffer data inside the FPGA. In FPGAs, FIFOs are usually used for data transmission between different clock domains, or as data cache to reduce data processing delays.

[0031] The working principle of FIFO is based on the automatic increment of the internal read and write pointers. When data is written into the FIFO, the write pointer points to the next free position and automatically increases by 1; when data is read from the FIFO, the read pointer points to the next position to be read and automatically increases by 1. By comparing the position relationship of the read and write pointers, the empty and full status of the FIFO can be determined.

[0032] Depending on whether the read and write clocks are the same clock, FIFO can be divided into synchronous FIFO and asynchronous FIFO.

[0033] Synchronous FIFO: Read and write operations use the same clock signal. When the clock edge comes, read and write operations can occur simultaneously. The design of synchronous FIFO is relatively simple, but it is less common in practical applications.

[0034] Asynchronous FIFO: Read and write operations use different clock signals. The read and write clocks are two independent clocks. The design of asynchronous FIFO is relatively complex, but it is widely used because it can transfer data between different clock domains.

[0035] Important parameters of FIFO include: Width, the number of data bits that the FIFO can read or write at a time. It determines the width of data that the FIFO can handle. Depth, how many N-bit data the FIFO can store (if the width is N). It determines the amount of data that the FIFO can cache. Full Flag, when the FIFO is full or about to be full, a signal sent by the FIFO status circuit to prevent the FIFO write operation from continuing to write data to the FIFO and causing overflow. Empty Flag, when the FIFO is empty or about to be empty, a signal sent by the FIFO status circuit to prevent the FIFO read operation from continuing to read data from the FIFO and causing invalid data to be read.

[0036] MEM, or "memory", refers to the components or space used to store information in computer science. It is the basis for the normal operation of the computer and is used to temporarily or permanently store data and programs. In computer hardware, MEM usually refers to memory (RAM) and storage devices (such as hard disks, flash memory, etc.). Among them, memory (RAM) is a volatile memory used to temporarily store data and programs being processed. When the computer is powered off, the data in RAM will be lost. The access speed of RAM is very fast and it is the main storage space directly accessed by the CPU. Storage devices include hard disks, solid-state drives (SSDs), flash memory (FlashMemory), etc., which are used to store data and programs for a long time, and data will not be lost even if the computer is powered off. The access speed of storage devices is relatively slow, but the capacity is usually much larger than RAM.

[0037] MEM memory is the main component of a computer system used to store data and programs. It allows the computer to quickly access and modify this information when processing data. When a computer executes a program, the program is loaded into the memory. The CPU reads instructions from the memory and executes them, thereby enabling the program to run. The memory can also be used as a cache to store recently accessed data or instructions for faster access.

[0038] The operating system is responsible for allocating memory space for running programs. It uses various algorithms to ensure efficient use of memory and avoid memory fragmentation. To prevent memory conflicts and data corruption between programs, the operating system provides memory protection mechanisms. This includes virtual memory technology, which allows each program to have its own address space and prevents them from accessing the memory of other programs. When a program no longer needs memory, the operating system reclaims this memory space so that other programs can use it.

[0039] Generally, MEM memory is optimized by: reducing memory usage by compressing the data stored in memory. This can improve memory utilization and allow more programs to run simultaneously. By dividing the memory into fixed-size pages and allowing programs to access memory in units of pages. This helps reduce memory fragmentation and improves the efficiency of memory management. And, using cache to store recently accessed data or instructions to speed up access. This can significantly improve program performance.

[0040] RISC-V is an open source instruction set architecture (ISA) based on the Reduced Instruction Set (RISC) principle. As an emerging open source instruction set architecture, RISC-V has the following characteristics: First of all, the RISC-V instruction set architecture is completely open source. Secondly, the RISC-V architecture adopts a modular design concept, and different modules can be selected for combination according to specific needs. This modular design makes the RISC-V processor highly customizable and able to meet the needs of different application scenarios. This also makes the RISC-V instruction set architecture more flexible and scalable. The design of the RISC-V instruction set follows the principle of reduced instruction set, with a concise and clear instruction format and fewer instruction types. This makes the RISC-V processor simpler and more efficient in hardware implementation, while also reducing the complexity of software development. Finally, RISC-V has a wide range of software support, including operating systems, compilers, development tool chains, etc. This enables the RISC-V processor to run a variety of mainstream software applications, providing users with a wealth of choices.

[0041] The RISC-V open source instruction set architecture has been widely used in multiple fields, including but not limited to embedded systems, cloud computing and big data, artificial intelligence and machine learning, as well as the Internet of Things and edge computing.

[0042] RISC-V processors have been widely used in embedded systems due to their low cost, high reliability and low power consumption. For example, microcontrollers, sensors, smart devices, etc. can all adopt the RISC-V architecture.

[0043] The high energy efficiency and flexible customization of RISC-V processors have also made them popular in the fields of cloud computing and big data. For example, servers, databases, distributed systems, etc. can all use RISC-V architecture to optimize performance and power consumption.

[0044] RISC-V can support the latest computer science and engineering technologies, such as artificial intelligence, Internet of Things, edge computing, etc. For example, neural network accelerators, image processors, speech recognizers, etc. can all be implemented using the RISC-V architecture.

[0045] RISC-V processors are also widely used in the fields of IoT and edge computing. For example, smart homes, smart cars, smart cities, etc. can all use RISC-V architecture to build more intelligent, efficient and reliable IoT systems.

[0046] A FIFO (First In First Out) queue composed of a Block RAM (Block Random Access Memory) is a data structure widely used in digital system design, especially in scenarios where caching, data buffering or data transmission across clock domains is required. FIFO, or First In First Out, is a traditional sequential execution method. In computers, a First In First Out queue is a traditional sequential execution method in which the first instruction to enter is completed and retired first, followed by the second instruction. The FIFO queue has the advantages of simple processing and low overhead, but does not classify messages and adopts a best-effort forwarding mode. The Block RAM FIFO of an embodiment of the present invention is mainly composed of a Block RAM and some peripheral circuits. BlockRAM is a large-capacity, high-speed memory, which is usually used to store a large amount of data. In the FIFO, the Block RAM is used as the main part for storing data, while the peripheral circuit is used to control the read and write operations of the data, generate empty and full flags, etc.

[0047] The Block RAM FIFO works as follows: Write Operation: When there is data to be written into the FIFO, the write operation begins.

[0048] The data is written to the specified location in the block RAM.

[0049] The write pointer points to the next address to be written, and automatically increases by 1 after writing.

[0050] If the FIFO is full (i.e. the write pointer reaches the end of the block RAM or the preset full mark position), the write operation is blocked to prevent data overflow.

[0051] Read Operation: When data needs to be read from the FIFO, a read operation begins.

[0052] Data is read from the specified location in the Block RAM.

[0053] The read pointer points to the next address to be read and automatically increases by 1 after reading.

[0054] If the FIFO is empty (that is, the read pointer reaches the beginning of the block RAM or the preset empty flag position), the read operation is blocked to prevent reading invalid data.

[0055] Empty and full flags: Empty flag: When all the data in the FIFO is read out, the empty flag is set, indicating that the FIFO is empty. At this time, the read operation is blocked.

[0056] Full flag: When the data in the FIFO reaches the preset capacity limit, the full flag is set, indicating that the FIFO is full. At this time, the write operation is blocked.

[0057] In one possible implementation, when the FIFO reaches its own capacity, a write operation is initiated to write the weight coefficients and temporary data stored in the FIFO into the MEM memory. The capacity of the FIFO itself includes any one or more combinations of the bit width, depth, and number of the FIFO. In the embodiment of the present invention, since the weight coefficients and temporary data generated by the AI ​​calculation circuit can be stored in the FIFO, there is no need to frequently interact with the MEM memory. The frequency of interaction depends on the depth of the FIFO. Therefore, the depth of the FIFO can basically be approximated to the speed of the increase. Of course, in some other possible implementations, the depth of the FIFO in the embodiment of the present invention may also be replaced by the bit width, number, etc. of the FIFO.

[0058] In a possible implementation, in the step of designing AI extended instructions based on the RISC-V open source instruction set, the user-defined instructions in the assembly code of the RISC-V open source instruction set are implemented by pseudo-instructions .insn, and the format is as follows:

[0059] In the formula, .insn is used to inform the compiler that the current instruction is in the form of .insn; r is used to specify that the instruction type is R-type; opcode, func3, func7, rd, rs1 and rs2 correspond to the bit fields of the instruction format respectively, where func3 corresponds to Xs1, Xs2 and Xd, Xs1 is used to describe the depth of the first-in-first-out data buffer FIFO, and Xs2 is used to describe the timing of output to the MEM memory. Pseudo-instructions are instructions used to instruct the assembler on how to assemble. They do not control the operation of the machine, will not be assembled into machine code, and will not occupy ROM space. Pseudo-instructions only exist in assembly language. They are usually not called instructions in high-level languages, but statements. Pseudo-instructions provide the assembler with key information such as which are instructions, which are data, the word length of the data, the starting address and the ending address of the program.

[0060] Further, in the step of designing an AI extension instruction based on the RISC-V open source instruction set described in the embodiment of the present invention, the designed AI extension instruction is JJ_AI_CAL, and the specific description of the instruction is shown in the following table:

[0061] The encoding Opcode describes the extended instruction set operation custom0, the value of Xd is 0; the value of Xs1 is 1, describing the first-in-first-out data buffer FIFO depth; the value of Xs2 is 1, describing the timing of output to MEM memory; the value of Funct7 is 3.

[0062] An opcode is the part of an instruction that specifies what type of operation the computer should perform. Opcodes are usually used with operands (i.e., data or locations of data specified in an instruction) to complete a specific calculation or task.

[0063] The RISC-V open source instruction set achieves software and hardware collaboration of MEM / CPU / AI / FIFO circuits through extended instructions, reduces clock frequency requirements, reduces the number of MEM read and write times, improves the computing power of the overall circuit, and reduces system power consumption.

[0064] The AI ​​circuit design method based on RISC-V instruction extension in the embodiment of the present invention makes full use of the FIFO inside the FPGA to achieve a multiple relationship between the FIFO depth and the system computing power. The complementarity between FIFO and MEM directly improves the operating efficiency and utilization of the FPGA. The circuit is designed by integrating instructions, which further improves the instruction density and reduces power consumption.

[0065] Another embodiment of the present invention further proposes an AI circuit design system based on RISC-V instruction extension, comprising: The AI ​​computing circuit structure design module is used to design the structure of the AI ​​computing circuit, store the weight coefficients and temporary data generated by the AI ​​computing circuit in the first-in-first-out data buffer FIFO inside the field programmable gate array FPGA, and directly obtain the weight coefficients and temporary data from the FIFO when performing the next round of calculations; when the FIFO reaches its own capacity, start a write operation to write the weight coefficients and temporary data stored in the FIFO into the MEM memory; The AI ​​extended instruction design module is used to design AI extended instructions based on the RISC-V open source instruction set, combine the structure of the AI ​​computing circuit with the AI ​​extended instructions, and realize the software and hardware coordinated action of MEM memory, CPU, AI computing circuit and first-in-first-out data buffer FIFO circuit.

[0066] In one possible implementation, in the AI ​​computing circuit structure designed by the AI ​​computing circuit structure design module, the field programmable gate array FPGA is internally provided with a CPU designed based on the RISC-V open source instruction set architecture, a first-in-first-out data buffer FIFO composed of a block random access memory Block RAM, and an AI computing circuit, and the MEM memory is externally mounted on the field programmable gate array FPGA.

[0067] In a possible implementation, when the FIFO reaches its own capacity, the AI ​​computing circuit structure design module starts a write operation to write the weight coefficients and temporary data stored in the FIFO into the MEM memory. The capacity of the FIFO itself includes any one or more combinations of the bit width, depth and number of the FIFO.

[0068] In a possible implementation, when the AI ​​extended instruction design module designs AI extended instructions based on the RISC-V open source instruction set, the user-defined instructions in the assembly code of the RISC-V open source instruction set are implemented through pseudo instructions .insn, and the format is as follows:

[0069] In the formula, .insn is used to inform the compiler that the current instruction is an instruction in .insn format; r is used to specify that the instruction type is R-type; opcode, func3, func7, rd, rs1 and rs2 correspond to the bit fields of the instruction format respectively, among which func3 corresponds to Xs1, Xs2 and Xd, Xs1 is used to describe the depth of the first-in-first-out data buffer FIFO, and Xs2 is used to describe the timing of output to the MEM memory.

[0070] In a possible implementation, the AI ​​extended instruction designed by the AI ​​extended instruction design module is JJ_AI_CAL, the encoded Opcode describes the extended instruction set operation custom0, the value of Xd is 0; the value of Xs1 is 1, describing the first-in-first-out data buffer FIFO depth; the value of Xs2 is 1, describing the timing of output to MEM memory; the value of Funct7 is 3.

[0071] In order to meet the demand for high-performance computing power in AI applications, the RISC-V architecture allows designers to add custom AI instruction sets. These instruction sets can optimize common operations in AI computing, such as matrix operations, vector operations, etc., thereby significantly improving the performance and efficiency of AI computing. The embodiment of the present invention can achieve software and hardware collaboration between circuits such as MEM (memory), CPU (central processing unit), AI (artificial intelligence) and FIFO (first-in, first-out queue) through the AI ​​instruction extension design of RISC-V. This collaborative design can make full use of hardware resources and improve the overall computing power of the system. The software and hardware collaborative design enables the RISC-V architecture to handle AI tasks more effectively, thereby improving the computing power of the system. This improvement is crucial for AI applications that require high-performance computing. FIFO plays an important role in FPGA. It can be used as a data buffer to help match data transmission at different rates. In addition, FIFO can also be used to protect the integrity and consistency of data during transmission. FIFO and MEM complement each other in FPGA. FIFO is mainly used to cache data, while MEM is used to store data and programs. By making rational use of FIFO and MEM, the operating efficiency and resource utilization of FPGA can be optimized. The embodiment of the present invention can optimize data transmission and storage by making full use of the FIFO inside the FPGA and combining the use of MEM. This optimization can directly improve the operating efficiency and resource utilization of the FPGA, making the FPGA more efficient and reliable when processing complex tasks.

[0072] Another embodiment of the present invention further proposes an electronic device, comprising a processor and a memory, wherein the processor is used to execute a computer program stored in the memory to implement the AI ​​circuit design method based on RISC-V instruction extension.

[0073] Another embodiment of the present invention further proposes a computer-readable storage medium, which stores at least one instruction, and when the at least one instruction is executed by a processor, the AI ​​circuit design method based on RISC-V instruction extension is implemented.

[0074] The computer program includes computer program code, which may be in source code form, object code form, executable file or some intermediate form. The computer-readable storage medium may include: any entity or device, medium, USB flash drive, mobile hard disk, disk, optical disk, computer memory, read-only memory, random access memory, electric carrier signal, telecommunication signal and software distribution medium, etc. that can carry the computer program code. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals. For ease of explanation, the above content only shows the part related to the embodiment of the present invention. For specific technical details not disclosed, please refer to the method part of the embodiment of the present invention. The computer-readable storage medium is non-temporary and can be stored in a storage device formed by various electronic devices, which can realize the execution process recorded in the method of the embodiment of the present invention.

[0075] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0076] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0077] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0078] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. An AI circuit design method based on RISC-V instruction extension, characterized in that: include: Design the structure of the AI ​​calculation circuit, store the weight coefficients and temporary data generated by the AI ​​calculation circuit in the first-in-first-out data buffer FIFO inside the field programmable gate array FPGA, and directly obtain the weight coefficients and temporary data from the FIFO when performing the next round of calculations; when the FIFO reaches its own capacity, start a write operation to write the weight coefficients and temporary data stored in the FIFO into the MEM memory; AI extension instructions are designed based on the RISC-V open source instruction set, and the structure of the AI ​​computing circuit is combined with the AI ​​extension instructions to achieve the software and hardware coordinated action of MEM memory, CPU, AI computing circuit and first-in-first-out data buffer FIFO circuit.

2. The AI ​​circuit design method based on RISC-V instruction extension according to claim 1 is characterized in that: In the step of designing the structure of the AI ​​computing circuit, the field programmable gate array FPGA is internally provided with a CPU designed based on the RISC-V open source instruction set architecture, a first-in-first-out data buffer FIFO composed of a block random access memory Block RAM, and an AI computing circuit, and the MEM memory is externally mounted on the field programmable gate array FPGA.

3. The AI ​​circuit design method based on RISC-V instruction extension according to claim 1 is characterized in that: When the FIFO reaches its own capacity, a write operation is initiated to write the weight coefficients and temporary data stored in the FIFO into the MEM memory. The capacity of the FIFO itself includes any one or more combinations of the bit width, depth and number of the FIFO.

4. The AI ​​circuit design method based on RISC-V instruction extension according to claim 1 is characterized in that: In the step of designing AI extended instructions based on the RISC-V open source instruction set, the user-defined instructions in the assembly code of the RISC-V open source instruction set are implemented by pseudo-instructions .insn, and the format is as follows: In the formula, .insn is used to inform the compiler that the current instruction is an instruction in .insn format; r is used to specify that the instruction type is R-type; opcode, func3, func7, rd, rs1 and rs2 correspond to the bit fields of the instruction format respectively, among which func3 corresponds to Xs1, Xs2 and Xd, Xs1 is used to describe the depth of the first-in-first-out data buffer FIFO, and Xs2 is used to describe the timing of output to the MEM memory.

5. The AI ​​circuit design method based on RISC-V instruction extension according to claim 4 is characterized in that: In the step of designing an AI extended instruction based on the RISC-V open source instruction set, the designed AI extended instruction is JJ_AI_CAL, the encoding Opcode describes the extended instruction set operation custom0, the value of Xd is 0; the value of Xs1 is 1, describing the first-in-first-out data buffer FIFO depth; the value of Xs2 is 1, describing the timing of output to the MEM memory; the value of Funct7 is 3.

6. An AI circuit design system based on RISC-V instruction extension, characterized in that: include: The AI ​​computing circuit structure design module is used to design the structure of the AI ​​computing circuit, store the weight coefficients and temporary data generated by the AI ​​computing circuit in the first-in-first-out data buffer FIFO inside the field programmable gate array FPGA, and directly obtain the weight coefficients and temporary data from the FIFO when performing the next round of calculations; when the FIFO reaches its own capacity, start a write operation to write the weight coefficients and temporary data stored in the FIFO into the MEM memory; The AI ​​extended instruction design module is used to design AI extended instructions based on the RISC-V open source instruction set, combine the structure of the AI ​​computing circuit with the AI ​​extended instructions, and realize the software and hardware coordinated action of MEM memory, CPU, AI computing circuit and first-in-first-out data buffer FIFO circuit.

7. The AI ​​circuit design system based on RISC-V instruction extension according to claim 6, characterized in that: In the AI ​​computing circuit structure designed by the AI ​​computing circuit structure design module, the field programmable gate array FPGA is internally provided with a CPU designed based on the RISC-V open source instruction set architecture, a first-in-first-out data buffer FIFO composed of a block random access memory Block RAM, and an AI computing circuit, and the MEM memory is externally mounted on the field programmable gate array FPGA.

8. The AI ​​circuit design system based on RISC-V instruction extension according to claim 6, characterized in that: When the FIFO reaches its own capacity, the AI ​​computing circuit structure design module starts a write operation to write the weight coefficients and temporary data stored in the FIFO into the MEM memory. The capacity of the FIFO itself includes any one or more combinations of the bit width, depth and number of the FIFO.

9. The AI ​​circuit design system based on RISC-V instruction extension according to claim 6, characterized in that: When the AI ​​extended instruction design module designs AI extended instructions based on the RISC-V open source instruction set, the user-defined instructions in the assembly code of the RISC-V open source instruction set are implemented through pseudo-instructions .insn, and the format is as follows: In the formula, .insn is used to inform the compiler that the current instruction is an instruction in .insn format; r is used to specify that the instruction type is R-type; opcode, func3, func7, rd, rs1 and rs2 correspond to the bit fields of the instruction format respectively, among which func3 corresponds to Xs1, Xs2 and Xd, Xs1 is used to describe the depth of the first-in-first-out data buffer FIFO, and Xs2 is used to describe the timing of output to the MEM memory.

10. The AI ​​circuit design system based on RISC-V instruction extension according to claim 9, characterized in that: The AI ​​extended instruction designed by the AI ​​extended instruction design module is JJ_AI_CAL, the encoding Opcode describes the extended instruction set operation custom0, the value of Xd is 0; the value of Xs1 is 1, describing the first-in-first-out data buffer FIFO depth; the value of Xs2 is 1, describing the timing of output to MEM memory; the value of Funct7 is 3.

11. An electronic device, characterized in that: It comprises a processor and a memory, wherein the processor is used to execute a computer program stored in the memory to implement an AI circuit design method based on RISC-V instruction extension as described in any one of claims 1 to 5.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one instruction, and when the at least one instruction is executed by the processor, it implements the AI ​​circuit design method based on RISC-V instruction extension as described in any one of claims 1 to 5.

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