Task timestamp recording method for simulating multi-core system network communication

Abstract

The invention provides a task execution timestamp recording method for simulating data communication of a multi-core system, which comprises the following steps that: when a busy signal of an operation state control unit is valid, a clock timing unit records a current task ID (Identity), records a count value of a task interval clock timer, and stops and clears the count value of the task interval clock timer; starting a task execution clock timer to count, when a task execution state signal changes, recording and resetting the task execution clock timer, and sending a count value of each state into a timestamp information arrangement unit; and when the task execution state jumps from the write-back state to the idle state, stopping and resetting the task execution clock timer, starting the task interval clock timer, and updating the relative task ID as the current task ID. According to the method, recording of various timestamps is achieved, the task execution sequence of the task in each core and the occupation time of each state can be recovered according to the recorded relative timestamp information, and simulation of the data communication process of a multi-core system is assisted.

Description

Technical Field

[0001] The present invention relates to the technical field of heterogeneous multi-core system simulation devices, and in particular to a task timestamp recording method for simulating multi-core system network communication. Background Art

[0002] As the scale and complexity of heterogeneous multi-core systems increase, the difficulty and time cost of simulation verification continue to increase. Therefore, designing a flexible and efficient simulation verification platform for heterogeneous multi-core systems has become a hot issue in the industry. In order to solve this problem, a solution based on software-hardware co-simulation of heterogeneous multi-core systems is designed. The software-hardware co-simulator simulates the data communication in the on-chip network through software, and the hardware is designed as a reconfigurable computing system that simulates the data calculation of the multi-core system. Through software-hardware collaborative communication, while ensuring the simulation accuracy, it also effectively improves the simulation efficiency.

[0003] In order to accurately simulate the data communication process of the on-chip network, the software side needs to simulate the periodic changes in the running state of the real node when executing different tasks. Due to the heterogeneous characteristics of multi-cores, the software side cannot accurately simulate the periodic changes in the running state of the computing unit when executing different tasks. The timestamp information generated by the real computing unit when executing the task is required for the software side to simulate the data communication process of the on-chip network. The traditional absolute timestamp recording method often uses a large-bit-width global clock counter. When a large amount of absolute timestamp information is collected, a large amount of on-chip storage resources and transmission bandwidth will be occupied, affecting the execution efficiency of the hardware platform. Although the recording of relative timestamps can greatly reduce the bit width of each timestamp, due to the large difference in the execution time of different tasks, the counter must retain a large enough bit width for timestamp collection. This makes the timestamps generated by tasks with shorter execution time have a large number of leading zeros occupying storage space, making it impossible to effectively utilize the on-chip storage resources. Summary of the invention

[0004] In order to solve the problem that different cores have different numbers of execution state change cycles when executing different tasks, the present invention proposes a task execution timestamp recording method for simulating multi-core system data communication to achieve the recording of multiple timestamps.

[0005] The present invention discloses a task execution timestamp recording method for simulating multi-core system network communication. The task execution timestamp recording method for simulating multi-core system network communication is based on a task execution timestamp recording circuit for simulating multi-core system data communication. The task execution timestamp recording circuit includes a task information storage unit, an operation status control unit, a clock timing unit, a timestamp information sorting unit and a write-back management unit; the clock timing unit includes a task interval clock timer and a task execution clock timer.

[0006] The task timestamp recording method for simulating multi-core system network communication comprises the following steps:

[0007] Step S1, when the busy signal of the operation state control unit is valid, the clock timing unit records the current task ID, records the task interval clock timer count value as the task relative start timestamp RT, and stops and clears the task interval clock timer count;

[0008] Step S2, start the task execution clock timer to count, when the task execution state generated by the operation state control unit changes, record and clear the task execution clock timer, and send the count value of each state to the timestamp information sorting unit;

[0009] Step S3, when the task execution state jumps from the write-back state to the idle state, the task execution clock timer is stopped and cleared, the task interval clock timer is started, and the relative task ID is updated to the current task ID;

[0010] Step S4: The timestamp information sorting unit compresses and sorts the current task ID, the stored relative task ID, and the generated relative timestamp into a timestamp information sequence and stores it in the RAM.

[0011] Furthermore, in step 1, after the task information storage unit stores a new task information, it sends a request signal to the operation status control unit, waits for the busy signal of the operation status control unit to be valid, and the rising edge of the busy signal indicates that the task starts to execute. The clock timing unit obtains the current task ID from the task information storage unit and records the task interval clock timer. After recording, the timer is cleared and stopped.

[0012] The count value represents the relative start timestamp RT of the current task relative to the last task after execution. The timestamp and its valid signal, the current task ID and the relative task ID stored in the last task execution process are sent to the timestamp information sorting unit.

[0013] Furthermore, in step 2, the task execution state is controlled by a ring state machine in the computing state control unit that controls the computing unit to execute the task, and different execution states are generated at different stages of the computing unit executing the task, including: idle, node content input, data input, task execution, and data write back;

[0014] The count value of each state is the relative time of the state with respect to the previous state, including the node content input timestamp NT, the data input timestamp DT, the task execution timestamp ET, and the data write-back timestamp WT; each time the timestamp of a state is recorded, the timestamp and its valid signal are sent to the timestamp information sorting unit for storage.

[0015] Furthermore, in step 2, the specific process of obtaining the timestamp is as follows:

[0016] S21, after the operation state control unit obtains a complete task information, the execution state jumps from the idle state to the content input state, and the task execution clock timer counts at this time; in the content input state, the address and data size of the configuration information of the operation unit are matched according to the node content register index, and the configuration information or instruction file and other node contents are obtained from the DDR according to this information, and the node content is written to the operation unit configuration information register and the instruction memory;

[0017] S22, when the node content is written, the computing unit enters the state of receiving the computing source data, and the execution state jumps to the data input state, records and clears the count value of the task execution clock timer, which is the time taken by the computing node to receive the node content, and serves as the node content input timestamp NT; in the data input state, the computing source data is obtained according to the address and data size of the computing source data stored in the computing source data register, and the data valid signal is written into the computing unit together with the data for calculation;

[0018] S23, after the input of the computing source data is completed, the computing unit starts to calculate the data. At this time, the execution state jumps to the task execution state, and the count value of the task execution clock timer is recorded and cleared. The count value is the time taken by the computing node to receive the computing source data, which is used as the data input timestamp DT; the task execution state indicates the time when the last computing source data is input and the first output data is output from the computing unit;

[0019] S24, when the rising edge of the output data valid signal is detected, the execution state jumps to the data write-back state, and the task execution clock timer count value is recorded and cleared. The count value is the time used by the operation unit to calculate, which is used as the task execution timestamp ET; in the data write-back state, the data is written back to the corresponding address space according to the write-back address;

[0020] S25. After the write-back is completed, the execution state jumps back to the idle state, and the count value of the task execution clock timer is recorded. The count value is the time used to write the data back to the DDR, which is used as the data write-back timestamp WT; the execution state continues to wait for new task execution requests in the idle state.

[0021] Furthermore, in step 3, when the task execution state jumps from the write-back state back to the idle state, the task execution clock timer is stopped and cleared, the task interval clock timer is started to count, and the current task ID is stored; when the next task starts to execute, the task ID is used as the relative task ID and is written into the timestamp information sequence together with the ID of the next task.

[0022] The task interval clock timer and task execution clock timer have sufficient bit width counts. When the task execution clock timer generates a count overflow, it is an abnormal situation. The clock timing unit generates an overflow alarm signal to report the abnormal situation. When the task interval clock timer generates an overflow, it indicates that the last task has been executed. The timestamp information sorting unit will issue a write-back request to write the remaining timestamp information sequence back to the DDR.

[0023] Furthermore, in step 4, the specific process of timestamp sorting is as follows:

[0024] S41, when the task starts to be executed, the current task ID and the relative task ID are stored;

[0025] S42, the clock timer timing bit width is n. When the relative start timestamp RT of the task arrives, the timestamp is stored; and the highest bit of the timestamp is compared with 1. When the result is 0, it means that the current bit is a leading zero. The leading zero counter is increased by one, and the value is shifted left by one bit and then judged again until the comparison result is 1, indicating that the current bit is not a leading zero. The counter is stopped and the count value is stored. The count value is the number of leading zeros RT of the current timestamp. zero , then the bit width of the timestamp after removing the leading zero is RT wid :

[0026] RT wid =n-RT zero

[0027] Set a group of registers Stemp_r with a bit width of 5*n, and set the timestamp from 0 to RT according to the bit width after removing the timestamp wid -1 bit is assigned to the high RT of Stemp_r wid Bit;

[0028] S43, repeat S42, calculate the bit width NT of the node content input timestamp NT, the data input timestamp DT, the task execution timestamp ET, and the data write-back timestamp WT after removing the leading zeros wid , DT wid , E.T. wid and WT wid , and fill the timestamp after removing the leading zero into the Stemp_r register in order from high to low;

[0029] S44, according to the above calculation, it can be known that the actual bit width of the timestamp generated by this task is Stemp wid :

[0030] Stemp wid =RT wid +NT wid +DT wid +ETwid +WT wid

[0031] According to Stemp wid It can be known that the minimum number of bytes occupied by Stemp_r is m, and the first m bytes of Stemp_r are combined with the current task ID and the relative task ID as a timestamp information sequence and stored in RAM;

[0032] S45, recording the number of bytes stored in the RAM, and when the number of bytes occupied by a burst is met, sending a write-back request and a write-back address to the write-back management unit.

[0033] Furthermore, the absolute time when the current task starts is EndT+RT, and the absolute time when the task ends is EndT:

[0034] EndT=REndT+RT+NT+DT+ET+WT

[0035] Among them, REndT is the end time of the relative task, RT is the relative start timestamp of the task, NT is the node content input timestamp, DT is the data input timestamp, ET is the task execution timestamp, and WT is the data write-back timestamp;

[0036] The end time of the current task is used as the base time for subsequent tasks to be calculated. The absolute time of the start, execution process, and end of the tasks executed by all cores can be obtained, and the execution order of the tasks can be restored accordingly.

[0037] Furthermore, taking the completion time of the current task as the base time BaseT, the absolute time InjectT of injecting the data generated by this task into the network is:

[0038] InjectT=BaseT+NT+DT+ET

[0039] NT is the node content input timestamp, DT is the data input timestamp, and ET is the task execution timestamp;

[0040] When the global clock counter reaches this moment, the virtual data packet generated by the virtual processing unit will be injected into the simulated network to realize the data communication simulation of the task.

[0041] The beneficial effects achieved by the present invention are:

[0042] According to the above steps, the refined relative timestamps generated by the task execution process can be obtained at the minimum storage and transmission bit width cost. According to the calculation, the start time of all tasks relative to the end of the previous task and the time of each state of the task during the execution process can be obtained. Assuming that the first task of all computing units is executed at the same time, the order and occupied time of the task execution on each core can be restored according to the recorded relative timestamp information. And the generated real computing time can help simulate the state changes of the multi-core system when executing tasks on real nodes, and assist in the simulation of the data communication network of the multi-core system. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A block diagram of a task execution timestamp recording circuit for simulating multi-core system data communication according to the present invention;

[0044] Figure 2 A schematic diagram of the steps for implementing a task execution timestamp recording method for simulating multi-core system data communication according to the present invention;

[0045] Figure 3 A task execution state classification schematic diagram of a task execution timestamp recording method for simulating multi-core system data communication according to the present invention;

[0046] Figure 4 It is a schematic diagram of the structure of the sequence according to the timestamp information;

[0047] Figure 5 The present invention is a flowchart of the execution of a test algorithm in a specific embodiment of a task execution timestamp recording method for simulating multi-core system data communication. DETAILED DESCRIPTION

[0048] The present invention will be further described below in conjunction with specific embodiments, and the advantages and features of the present invention will become clearer as the description proceeds. However, these embodiments are exemplary only and do not constitute any limitation to the scope of the present invention. It should be understood by those skilled in the art that the details and forms of the technical solution of the present invention may be modified or replaced without departing from the spirit and scope of the present invention, but these modifications and replacements all fall within the scope of protection of the present invention.

[0049] As attached Figure 1 As shown, a task execution timestamp recording circuit for simulating multi-core system data communication is provided, which includes a task information storage unit, an operation status control unit, a clock timing unit, a timestamp information sorting unit, and a write-back management unit.

[0050] The task control storage unit is used to unpack and store current task information, and initiate a task execution request to the operation control unit when the operation state control unit is idle;

[0051] The operation state control unit is electrically connected to the task information storage unit, and controls the operation unit to implement the task execution process of the operation unit and generate task execution state information according to the task information stored in the task information storage unit;

[0052] The clock timing unit includes a task interval clock timer and a task execution clock timer;

[0053] The task interval clock timer is used to record the time difference between the start time of the current task and the end time of the previous task, and the time difference is called the relative start timestamp RT of the task;

[0054] The task execution clock timer is used to record the time used for each state of the computing control state machine after the computing unit receives the task information;

[0055] The timestamp information arrangement unit compresses and arranges the timestamp information generated by the timestamp timing unit and the current task number and the relative task number into a task timestamp sequence and stores it in the RAM, and sends a write-back signal to the write-back unit when the stored task time slice sequence meets a burst length;

[0056] The write-back management unit writes the data and timestamp information back to the DDR according to the task information.

[0057] As a preferred embodiment of the present invention, refer to Figure 2 ,The task execution timestamp recording method includes the following steps:

[0058] S1. When the busy signal of the operation control state unit is valid, the clock timing unit records the current task ID, records the task interval clock timer count value as the relative start timestamp RT of the task, and stops and clears the task interval clock counter count.

[0059] Specifically, after the task information storage unit stores a new task information, it sends a request signal to the operation state control unit, waits for the busy signal of the operation state control unit to be valid, and the rising edge of the busy signal indicates that the task starts to execute. The clock timing unit obtains the current task ID from the task information storage unit and records the task interval clock timer. After the recording is completed, the timer is cleared and stopped. The count value represents the relative start timestamp RT of the current task relative to the end of the previous task execution. The timestamp and its valid signal are sent to the timestamp information sorting unit together with the relative task ID stored by the previous task.

[0060] In some implementation examples, the main fields of a single task are listed in Table 1, including information such as the task ID and the dependency relationship between tasks. When the task meets the launch conditions, the processing end writes the information in the task field into the task information storage unit for the operation control unit to control the operation unit to execute the task, and generates the task execution status for timestamp recording.

[0061] Table 1

[0062]

[0063] S2. Start the task execution clock timer to count. When the task execution status signal changes, record and clear the task execution clock timer, and send the count value of each status to the timestamp information sorting unit.

[0064] Specifically, refer to Figure 3 The task execution state is determined by the ring state machine in the operation state control unit that controls the operation unit to execute the task. Different execution states are generated at different stages of the operation unit's task execution, including five states: idle, node content input, data input, task execution, and data write back. The count value of each state is the relative time of the state relative to the previous state, including the node content input timestamp NT, the data input timestamp DT, the task execution timestamp ET, and the data write back timestamp WT. Each time the timestamp of a state is recorded, the timestamp and its valid signal are sent to the timestamp information sorting unit for storage.

[0065] The specific process of obtaining the timestamp is as follows:

[0066] S21, after the operation state control unit obtains a complete task information, the execution state jumps from the idle state to the content input state, and the task execution clock timer counts. In this state, the address and data size of the configuration information of the operation unit are matched according to the node content register index, and the configuration information or instruction file and other node contents are obtained from the DDR according to this information, and the node content is written to the operation unit configuration information register and the instruction memory.

[0067] S22, when the node content is written, the computing unit enters the state of receiving the computing source data, and the execution state jumps to the data input state, and the task execution clock timer count value is recorded and cleared. The count value is the time taken by the computing node to receive the node content, which is called the node content input timestamp NT. In this state, the computing source data is obtained according to the address and data size of the computing source data stored in the computing source data register, and the data valid signal is written into the computing unit together with the data for calculation.

[0068] S23, after the calculation source data is input, the computing unit starts to calculate the data. At this time, the execution state jumps to the task execution state, and the task execution clock timer count value is recorded and cleared. The count value is the time taken by the computing node to receive the calculation source data, which is called the data input timestamp DT. This state indicates the time when the last calculation source data is input and the first output data is output from the computing unit.

[0069] S24, when the rising edge of the output data valid signal is detected, the execution state jumps to the data write-back state, and the task execution clock timer count value is recorded and cleared. The count value is the time used by the calculation unit, which is called the task execution timestamp ET. In this state, the data is written back to the corresponding address space according to the write-back address.

[0070] S25, after the write-back is completed, the execution state jumps back to the idle state, and the task execution clock timer count value is recorded. The count value is the time taken to write the data back to the DDR, which is called the data write-back timestamp WT. The execution state continues to wait for new task execution requests in the idle state.

[0071] S3. When the task execution state jumps from the write-back state back to the idle state, the task execution clock timer is stopped and cleared, the task interval clock timer is started, and the relative task ID is updated to the current task ID.

[0072] Specifically, when the task execution state jumps from the write-back state to the idle state, it means that the task execution is completed. At this time, the task execution clock timer records the data write-back timestamp WT, stops and clears it; the task interval clock timer counts to record the interval time between tasks, and the current task ID is stored. When the next task starts to execute, the task ID is used as the relative task ID and is written into the timestamp information sequence together with the ID of the next task.

[0073] The task interval clock timer and the task execution clock timer have sufficient bit width counts. When the task execution clock timer generates a count overflow, it is an abnormal situation. The clock timing unit generates an overflow alarm signal to report the abnormal situation. When the task interval clock timer overflows, it means that the current task is the last task executed by the core. The timestamp information sorting unit will issue a write-back request to write the remaining timestamp information sequence back to the DDR.

[0074] S4, the timestamp information arrangement unit compresses and arranges the current task ID, the stored relative task ID, and the generated relative timestamp into a timestamp information sequence and stores it in the RAM. When the stored information meets the number of bytes of a burst, a write-back request, data size and address information are sent to the write-back unit, and the write-back unit writes the data back to the DDR.

[0075] Specifically, the timestamp sorting process is as follows:

[0076] S41. When the task starts to be executed, the current task ID and the relative task ID are stored.

[0077] S42, suppose the clock timer timing bit width is n, when the relative start timestamp RT of the task arrives, the timestamp is stored. And the highest bit of the timestamp is compared with 1, when the result is 0, it means that the current bit is a leading zero, the leading zero counter is increased by 1, and the value is shifted left by one bit and then judged again, until the comparison result is 1, indicating that the current bit is not a leading zero, the counter is stopped, and the count value is stored, and the count value is the number of leading zeros RT of the current timestamp zero , then the bit width of the timestamp after removing the leading zero is RT wid :

[0078] RT wid =n-RT zero

[0079] Set a group of registers Stemp_r with a bit width of 5*n, and set the timestamp from 0 to RT according to the bit width after removing the timestamp wid -1 bit is assigned to the high RT of Stemp_r wid Bit.

[0080] S43, repeat S42, calculate the bit width NT of the node content input timestamp NT, the data input timestamp DT, the task execution timestamp ET, and the data write-back timestamp WT after removing the leading zeros wid , DT wid , E.T. wid and WT wid The timestamp after removing the leading zero is filled into the Stemp_r register in sequence from high to low.

[0081] S44, according to the above calculation, it can be known that the actual bit width of the timestamp generated by this task is Stemp wid :

[0082] Stemp wid =RT wid +NT wid +DT wid +ET wid +WT wid

[0083] According to Stemp wid It can be known that the minimum number of bytes occupied by Stemp_r is m, and the first m bytes of Stemp_r are combined with the current task ID and the relative task ID as a timestamp information sequence and stored in the RAM.

[0084] S45, recording the number of bytes stored in the RAM, and when the number of bytes occupied by a burst is met, sending a write-back request and a write-back address to the write-back management unit.

[0085] In some implementation examples, reference Figure 4 , the task ID bit width is 16 bits, and the timestamp bit width is 16 bits. The timestamp after removing the leading zero is concatenated with the current task ID and the relative task ID. After removing the leading zero, the actual effective information bit width of the timestamp information sequence register is between 40 bits and 112 bits. According to the judgment, the minimum number of bytes that can store this value is 5 to 14 bytes. According to the minimum number of bytes, the value in the timestamp register is stored in RAM in bytes, and the actual bit width value RT of each timestamp is stored. wid NT wid , DT wid , E.T. wid , WT wid The timestamp value is stored for subsequent recovery.

[0086] In some implementation examples, after obtaining the timestamp sequence of all tasks, all timestamp information of each task is separated and written into the task timestamp structure array. Assume that the scheduling time of the first batch of tasks is ignored, and the first task of each computing unit starts execution at the same time. Let the end time of the relative task be EndT, then the absolute time when the current task starts is EndT+RT, and the absolute time when the task ends is End:

[0087] End=EndT+RT+NT+DT+ET+WT

[0088] The end time of the current task is used as the base time for subsequent tasks to be calculated. In this way, the absolute time of the start, execution process, and end of the tasks executed by all cores can be obtained, and the execution order of the tasks can be restored.

[0089] In some implementation examples, when simulating data of a multi-core system data communication network, the time when the current task is completed is taken as the base time BaseT, and the absolute time InjectT when the data generated by this task is injected into the network is:

[0090] InjectT=BaseT+NT+DT+ET

[0091] When the global clock counter reaches this moment, the virtual data packet generated by the virtual processing unit will be injected into the simulated network to realize the data communication simulation of the task.

[0092] In some implementation examples, in a software and hardware collaborative multi-core simulator, the lower computer used for simulating task calculation is a multi-core system equipped with Xilinx's XCZU19EG FPGA chip, which uses AXI as the interconnection bus of the computing unit, and the ARM end is the task scheduling control center of the multi-core system, and the system clock is 100Mhz. When the system uses an absolute timestamp to collect task execution timestamps, in order to ensure that all times of the execution process of the lower computer can be covered, a 64-bit wide global counter is used to count the global clock of the system from start to stop, and each task records task start, node content input, data input, task execution, and data write back 5 timestamps, plus task ID information, a single task timestamp sequence is 336bit, occupying 42 bytes of storage space. When the method described in the present invention is used, the timestamp timer bit width is 16bit, and the length of the timestamp of a single task is between 40 and 112bit after sorting, occupying 5 to 14 bytes of storage space. After using the recording method of the present invention, the length of a single task timestamp information sequence is reduced by 2-7 times compared to the storage occupancy of the absolute timestamp recording method.

[0093] In this implementation example, a complex matrix inversion algorithm based on LU decomposition is used to simulate the multi-core task execution process of the lower computer. The algorithm is mapped into 5 batches of tasks on the reference model. The execution process of the algorithm is as follows: Figure 5 As shown. The 16-order, 32-order, and 64-order matrix data sets and task lists are sent to the lower computer for execution and calculation respectively. The execution cycle numbers of the three and the percentage of cycle reduction are compared in Table 2. It can be seen from the table that when the timestamp recording method of the present invention is adopted, the system can reduce the number of cycles by about 15% when executing the same task, that is, the present invention can effectively reduce the time used by the system to execute tasks and improve the execution efficiency of the multi-core system of the lower computer.

[0094] Table 2

[0095]

[0096] The above are only specific steps of the present invention and do not constitute any limitation to the protection scope of the present invention; any technical solutions formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the present invention; some parts not elaborated in detail in the present invention belong to the known technologies of those skilled in the art.

Claims

1. A task execution timestamp recording method for simulating multi-core system network communication, characterized in that: The task execution timestamp recording method for simulating multi-core system network communication is based on a task execution timestamp recording circuit for simulating multi-core system data communication. The task execution timestamp recording circuit includes a task information storage unit, an operation status control unit, a clock timing unit, a timestamp information sorting unit and a write-back management unit; the clock timing unit includes a task interval clock timer and a task execution clock timer. The task timestamp recording method for simulating multi-core system network communication comprises the following steps: Step S1, when the busy signal of the operation state control unit is valid, the clock timing unit records the current task ID, records the task interval clock timer count value as the task relative start timestamp RT, and stops and clears the task interval clock timer count; Step S2, start the task execution clock timer to count, when the task execution state generated by the operation state control unit changes, record and clear the task execution clock timer, and send the count value of each state to the timestamp information sorting unit; Step S3, when the task execution state jumps from the write-back state to the idle state, the task execution clock timer is stopped and cleared, the task interval clock timer is started, and the relative task ID is updated to the current task ID; Step S4: The timestamp information sorting unit compresses and sorts the current task ID, the stored relative task ID, and the generated relative timestamp into a timestamp information sequence and stores it in the RAM.

2. The task timestamp recording method for simulating multi-core system network communication according to claim 1, characterized in that: In step 1, after the task information storage unit stores a new task information, it sends a request signal to the operation status control unit, waits for the busy signal of the operation status control unit to be valid, and the rising edge of the busy signal indicates that the task starts to execute. The clock timing unit obtains the current task ID from the task information storage unit and records the task interval clock timer. After recording, the timer is cleared and stopped. The count value represents the relative start timestamp RT of the current task relative to the last task after execution. The timestamp and its valid signal, the current task ID and the relative task ID stored in the last task execution process are sent to the timestamp information sorting unit.

3. The task timestamp recording method for simulating multi-core system network communication according to claim 1, characterized in that: In step 2, the task execution state is controlled by a ring state machine in the computing state control unit that controls the computing unit to execute the task, and different execution states are generated at different stages of the computing unit executing the task, including: idle, node content input, data input, task execution, and data write back; The count value of each state is the relative time of the state with respect to the previous state, including the node content input timestamp NT, the data input timestamp DT, the task execution timestamp ET, and the data write-back timestamp WT; each time the timestamp of a state is recorded, the timestamp and its valid signal are sent to the timestamp information sorting unit for storage.

4. The task timestamp recording method for simulating multi-core system network communication according to claim 3, characterized in that: In step 2, the specific process of obtaining the timestamp is as follows: S21, after the operation state control unit obtains a complete task information, the execution state jumps from the idle state to the node content input state, and the task execution clock timer counts at this time; in the node content input state, the address and data size of the configuration information of the operation unit are matched according to the node content register index, and the configuration information or instruction file and other node contents are obtained from the DDR according to this information, and the node content is written to the operation unit configuration information register and the instruction memory; S22, when the node content is written, the computing unit enters the state of receiving the computing source data, and the execution state jumps to the data input state, records and clears the count value of the task execution clock timer, which is the time taken by the computing node to receive the node content, and serves as the node content input timestamp NT; in the data input state, the computing source data is obtained according to the address and data size of the computing source data stored in the computing source data register, and the data valid signal is written into the computing unit together with the data for calculation; S23, after the input of the computing source data is completed, the computing unit starts to calculate the data. At this time, the execution state jumps to the task execution state, and the count value of the task execution clock timer is recorded and cleared. The count value is the time taken by the computing node to receive the computing source data, which is used as the data input timestamp DT; the task execution state indicates the time when the last computing source data is input and the first output data is output from the computing unit; S24, when the rising edge of the output data valid signal is detected, the execution state jumps to the data write-back state, and the task execution clock timer count value is recorded and cleared. The count value is the time used by the operation unit to calculate, which is used as the task execution timestamp ET; in the data write-back state, the data is written back to the corresponding address space according to the write-back address; S25. After the write-back is completed, the execution state jumps back to the idle state, and the count value of the task execution clock timer is recorded. The count value is the time used to write the data back to the DDR, which is used as the data write-back timestamp WT; the execution state continues to wait for new task execution requests in the idle state.

5. The task timestamp recording method for simulating multi-core system network communication according to claim 1, characterized in that: In step 3, when the task execution state jumps from the write-back state to the idle state, the task execution clock timer is stopped and cleared, the task interval clock timer is started to count, and the current task ID is stored; when the next task starts to execute, the task ID is used as the relative task ID and is written into the timestamp information sequence together with the ID of the next task. The task interval clock timer and task execution clock timer have sufficient bit width counts. When the task execution clock timer generates a count overflow, it is an abnormal situation. The clock timing unit generates an overflow alarm signal to report the abnormal situation. When the task interval clock timer generates an overflow, it indicates that the last task has been executed. The timestamp information sorting unit will issue a write-back request to write the remaining timestamp information sequence back to the DDR.

6. The task timestamp recording method for simulating multi-core system network communication according to claim 1, characterized in that: In step 4, the specific process of timestamp sorting is as follows: S41, when the task starts to be executed, the current task ID and the relative task ID are stored; S42, the clock timer timing bit width is n, when the relative start timestamp RT of the task arrives, the timestamp is stored; The highest bit of the timestamp is compared with 1. When the result is 0, it means that the current bit is a leading zero. The leading zero counter is incremented by 1, and the value is shifted left by one bit and judged again until the comparison result is 1, indicating that the current bit is not a leading 0. The counter is stopped and the count value is stored. The count value is the number of leading zeros in the current timestamp RT zero , then the bit width of the timestamp after removing the leading zero is RT wid : RT wid =n-RT zero Set a group of registers Stemp_r with a bit width of 5*n, and set the timestamp from 0 to RT according to the bit width after removing the timestamp wid -1 bit is assigned to the high RT of Stemp_r wid Bit; S43, repeat S42, calculate the bit width NT of the node content input timestamp NT, the data input timestamp DT, the task execution timestamp ET, and the data write-back timestamp WT after removing the leading zeros wid , DT wid , E.T. wid and WT wid , and fill the timestamp after removing the leading zero into the Stemp_r register in order from high to low; S44, according to the above calculation, it can be known that the actual bit width of the timestamp generated by this task is Stemp wid : Stemp wid =RT wid +NT wid +DT wid +ET wid +WT wid According to Stemp wid It can be known that the minimum number of bytes occupied by Stemp_r is m, and the first m bytes of Stemp_r are combined with the current task ID and the relative task ID as a timestamp information sequence and stored in RAM; S45, recording the number of bytes stored in the RAM, and when the number of bytes occupied by a burst is met, sending a write-back request and a write-back address to the write-back management unit.

7. The task execution timestamp recording method for simulating multi-core system data communication according to claim 1, characterized in that: The absolute time when the current task starts is EndT+RT, and the absolute time when the task ends is EndT: EndT=REndT+RT+NT+DT+ET+WT Among them, REndT is the end time of the relative task, RT is the relative start timestamp of the task, NT is the node content input timestamp, DT is the data input timestamp, ET is the task execution timestamp, and WT is the data write-back timestamp; The end time of the current task is used as the base time for subsequent tasks to be calculated. The absolute time of the start, execution process, and end of the tasks executed by all cores can be obtained, and the execution order of the tasks can be restored accordingly.

8. The task execution timestamp recording method for simulating multi-core system data communication according to claim 1, characterized in that: Taking the completion time of the current task as the base time BaseT, the absolute time InjectT when the data generated by this task is injected into the network is: InjectT=BaseT+NT+DT+ET NT is the node content input timestamp, DT is the data input timestamp, and ET is the task execution timestamp; When the global clock counter reaches this moment, the virtual data packet generated by the virtual processing unit will be injected into the simulated network to realize the data communication simulation of the task.

Images