Transistor layout method and device, storage medium and electronic equipment

Abstract

The invention discloses a transistor layout method and device, a storage medium and electronic equipment, and the method comprises the steps: obtaining an initial standard unit circuit; determining a transistor to be folded in the initial standard unit circuit; folding the transistor to be folded according to the folding strategy to obtain a plurality of folded transistors; modeling the folded transistor according to a graph theory algorithm to generate a graph structure; and carrying out combination processing on the plurality of folded transistors based on the graph structure, and carrying out layout by taking the combined folded transistors as independent elements to generate a target transistor layout. According to the scheme, the layout complexity of the transistor can be reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technology, and specifically to a transistor layout method, device, storage medium, and electronic device. Background Art

[0002] In integrated circuit design, as device density continues to increase, how to achieve high-performance and high-efficiency circuit design within a limited layout area has become a key technical challenge. As the basic building block of integrated circuits, the layout optimization of standard cells directly affects the overall performance, power consumption and manufacturing cost of the chip.

[0003] Transistor folding is a key technology for optimizing the layout of large-size transistors. Large-size transistors usually occupy a large layout area and increase the complexity of wiring, which has an adverse effect on signal transmission speed and power consumption. By splitting a large-size transistor into several small-size transistors, the diffusion area of ​​a single transistor can be reduced, the wiring structure can be optimized, and the compactness of the layout and circuit performance can be improved.

[0004] However, the layout of the folded transistor needs to solve the connection and arrangement problems of multiple small transistors, and the layout complexity of the transistor is relatively high. Summary of the invention

[0005] The embodiments of the present application provide a transistor layout method, device, storage medium and electronic device, which can reduce the layout complexity of transistors.

[0006] In a first aspect, an embodiment of the present application provides a transistor layout method, including:

[0007] Obtaining an initial standard unit circuit;

[0008] determining a transistor to be folded in the initial standard unit circuit;

[0009] Folding the transistors to be folded according to the folding strategy to obtain a plurality of folded transistors;

[0010] Modeling the folded transistor according to a graph theory algorithm to generate a graph structure;

[0011] A plurality of the folding transistors are combined based on the graph structure, and the combined folding transistors are laid out as separate elements to generate a target transistor layout.

[0012] In the transistor layout method provided in the embodiment of the present application, the folded transistor is modeled according to a graph theory algorithm to generate a graph structure, including:

[0013] Classifying the plurality of folding transistors according to transistor types into first folding transistors and second folding transistors;

[0014] The first folding transistor and the second folding transistor are modeled based on a graph theory algorithm to obtain a graph structure, where the graph structure includes a first sub-graph structure and a second sub-graph structure.

[0015] In the transistor layout method provided in the embodiment of the present application, the combining process of the plurality of folded transistors based on the graph structure includes:

[0016] Determine a first target combination mode of a plurality of first sub-transistors in each of the first folding transistors based on the first sub-graph structure, and combine a plurality of first sub-transistors in each of the first folding transistors according to the first target combination mode;

[0017] A second target combination of the second sub-transistors in each of the second folding transistors is determined based on the second sub-graph structure, and the second sub-transistors in each of the second folding transistors are combined according to the second target combination.

[0018] In the transistor layout method provided in the embodiment of the present application, the determining of a first target combination of a plurality of first sub-transistors in each of the first folded transistors based on the first sub-graph structure includes:

[0019] Determining the number of odd-degree points in the first subgraph structure;

[0020] Based on the number of odd-degree points and the connectivity of the first subgraph structure, the combination of a plurality of first sub-transistors in each of the first folding transistors is traversed to determine a first target combination.

[0021] In the transistor layout method provided in the embodiment of the present application, the determining of the second target combination of the plurality of second sub-transistors in each of the second folded transistors based on the second sub-graph structure includes:

[0022] Determining the number of odd-degree points in the second subgraph structure;

[0023] Based on the number of odd-degree points and the connectivity of the second subgraph structure, the combination of a plurality of second sub-transistors in each of the second folding transistors is traversed to determine a second target combination.

[0024] In the transistor layout method provided in the embodiment of the present application, the first folding transistor and the second folding transistor are modeled based on the graph theory algorithm to obtain a first subgraph structure and a second subgraph structure, including:

[0025] Representing the source and drain of each first sub-transistor in the first folded transistor as a node, and representing each first sub-transistor as an edge connecting the nodes, to form a first sub-graph structure;

[0026] The source and drain of each second sub-transistor in the second folded transistor are represented as nodes, and each second sub-transistor is represented as an edge connecting the nodes to form a second sub-graph structure.

[0027] In the transistor layout method provided in the embodiment of the present application, the combined folded transistors are laid out as separate elements to generate a target transistor layout, including:

[0028] Based on the symmetry of the first folding transistor and the second folding transistor, fine-tune the combination of the first folding transistor and / or the second folding transistor to obtain a first combined transistor and a second combined transistor;

[0029] The first combined transistor and the second combined transistor are laid out as separate elements to generate a target transistor layout.

[0030] In a second aspect, an embodiment of the present application provides a transistor layout device, including:

[0031] An acquisition unit, used for acquiring an initial standard unit circuit;

[0032] A determination unit, used for determining the transistor to be folded in the initial standard unit circuit;

[0033] A folding unit, used for folding the transistor to be folded according to a folding strategy to obtain a plurality of folded transistors;

[0034] A modeling unit, used for modeling the folded transistor according to a graph theory algorithm to generate a graph structure;

[0035] A combining unit is used to combine a plurality of the folding transistors based on the graph structure, and layout the combined folding transistors as separate elements to generate a target transistor layout.

[0036] In a third aspect, the present application provides a storage medium storing a plurality of instructions, wherein the instructions are suitable for loading by a processor to execute any of the above-mentioned transistor layout methods.

[0037] In a fourth aspect, the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-described transistor layout methods when executing the computer program.

[0038] In summary, the transistor layout method provided by the embodiment of the present application includes obtaining an initial standard unit circuit; determining the transistors to be folded in the initial standard unit circuit; folding the transistors to be folded according to the folding strategy to obtain a plurality of folded transistors; modeling the folded transistors according to the graph theory algorithm to generate a graph structure; combining a plurality of the folded transistors based on the graph structure, and laying out the combined folded transistors as separate elements to generate a target transistor layout. This solution reduces the layout complexity of transistors by combining transistor folding with the graph theory algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 It is a schematic diagram of an application scenario of the transistor layout method provided in an embodiment of the present application.

[0041] Figure 2 It is a flow chart of the transistor layout method provided in an embodiment of the present application.

[0042] Figure 3 It is a schematic diagram of the graph structure provided in the embodiment of the present application.

[0043] Figure 4 This is a schematic diagram of a first transistor combination provided in an embodiment of the present application.

[0044] Figure 5 This is a schematic diagram of a second transistor combination provided in an embodiment of the present application.

[0045] Figure 6 This is a schematic diagram of a third transistor combination provided in an embodiment of the present application.

[0046] Figure 7 It is a structural schematic diagram of a transistor layout device provided in an embodiment of the present application.

[0047] Figure 8 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0049] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0050] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0051] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0052] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, terms such as "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0053] Transistor folding is a key technology for optimizing the layout of large-size transistors. Large-size transistors usually occupy a large layout area and increase the complexity of wiring, which has an adverse effect on signal transmission speed and power consumption. By splitting a large-size transistor into several small-size transistors, the diffusion area of ​​a single transistor can be reduced, the wiring structure can be optimized, and the compactness of the layout and circuit performance can be improved.

[0054] However, the layout of the folded transistor needs to solve the connection and arrangement problems of multiple small transistors, and the layout complexity of the transistor is relatively high.

[0055] Based on this, the embodiments of the present application provide a transistor layout method, device, storage medium and electronic device. Specifically, the transistor layout device can be integrated in an electronic device, and the electronic device can be a server or a terminal. Among them, the terminal can include a mobile phone, a wearable smart device, a tablet computer, a laptop computer, and a personal computer (PC), etc.; the server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0056] For example, Figure 1 As shown, the electronic device can obtain an initial standard unit circuit; determine the transistors to be folded in the initial standard unit circuit; fold the transistors to be folded according to the folding strategy to obtain a number of folded transistors; model the folded transistors according to the graph theory algorithm to generate a graph structure; combine a number of the folded transistors based on the graph structure, and layout the combined folded transistors as separate elements to generate a target transistor layout.

[0057] The technical solutions shown in the present application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments is not intended to limit the priority order of the embodiments.

[0058] See also Figure 2 , Figure 2 : is a schematic diagram of a transistor layout method provided in an embodiment of the present application. The specific process of the transistor layout method can be as follows:

[0059] 101. Obtain an initial standard unit circuit.

[0060] The initial standard unit circuit refers to a basic circuit unit in integrated circuit design.

[0061] 102. Determine transistors to be folded in an initial standard unit circuit.

[0062] Typically, transistors to be folded refer to PMOS transistors and NMOS transistors with larger areas or critical layouts in standard unit circuits, to ensure that the folded transistors still meet the functional requirements of the circuit design.

[0063] 103. Folding the transistors to be folded is performed according to the folding strategy to obtain a plurality of folded transistors.

[0064] In the implementation of this application, the folding strategy includes a scheme of reducing the number of folding times and a scheme of folding with the same width.

[0065] Among them, the scheme of reducing the number of folding times aims to reduce the number of folded transistors by minimizing the number of folding operations, so as to simplify the complexity of the circuit, reduce the workload in the layout process, and help improve the stability and reliability of the circuit. Reducing the number of folding times can make each transistor easier to manage and optimize, thereby improving the performance of the overall circuit.

[0066] Among them, the same-width folding scheme can make the folded transistors have the same width. In this way, the uniformity and consistency of the layout can be optimized while maintaining the integrity of the circuit function. Transistors with consistent width help achieve better signal transmission and power consumption efficiency, because transistors with consistent width can operate under the same conditions, reducing the inconsistency problem caused by width differences.

[0067] When folding a transistor to be folded, a suitable folding point can be selected according to the folding strategy. Then, a large-size transistor is split into multiple small transistors based on the folding point, and the current characteristics of each segment of the transistor are ensured to be consistent with the original transistor. After that, the multiple small transistors obtained by splitting are arranged to obtain a folded transistor.

[0068] 104. Model the folded transistor based on graph theory algorithms and generate a graph structure.

[0069] It is understandable that the folding transistor includes a PMOS transistor and an NMOS transistor. Since the PMOS transistor and the NMOS transistor have different electrical characteristics, the PMOS transistor and the NMOS transistor need to be combined separately during the subsequent combination process.

[0070] Therefore, before modeling, the folded transistors need to be classified, and then the folded transistors are modeled according to the graph theory algorithm. Specifically, a plurality of folded transistors can be classified according to the transistor type, and divided into a first folded transistor and a second folded transistor; then the first folded transistor and the second folded transistor are modeled based on the graph theory algorithm to obtain a graph structure, which may include a first sub-graph structure and a second sub-graph structure.

[0071] It can be understood that when the first folding transistor is a PMOS transistor, the second folding transistor is an NMOS transistor. When the first folding transistor is an NMOS transistor, the second folding transistor is a PMOS transistor.

[0072] Modeling the first folded transistor and the second folded transistor based on a graph theory algorithm refers to abstracting the first folded transistor and the second folded transistor into a graph structure. In this way, the transistor layout problem in the entire standard unit circuit is transformed into a graph optimization problem. Each first folded transistor includes a plurality of first sub-transistors, and each second folded transistor includes a plurality of second sub-transistors.

[0073] In the embodiment of the present application, the source and drain of each first sub-transistor in the first folded transistor can be represented as a node, and each first sub-transistor can be represented as an edge connecting the nodes to form a first sub-graph structure. The source and drain of each second sub-transistor in the second folded transistor can be represented as a node, and each second sub-transistor can be represented as an edge connecting the nodes to form a second sub-graph structure.

[0074] For example, Figure 3 As shown, (a) and (b) are the sub-graph structures corresponding to the nmos transistor and pmos transistor in a standard unit circuit, respectively. The transistor M1 and the transistor M2 in the nmos transistor are folded into two first sub-transistors, and the transistor M3 is folded into three first sub-transistors. The transistor M5 and the transistor M6 in the pmos transistor are folded into two second sub-transistors, and the M4 transistor is folded into three second sub-transistors. Among them, VSS is the ground signal node of the circuit, Z is the logic signal node in the circuit, and net is the node represented by the source and drain.

[0075] 105. Combining a plurality of folded transistors based on the graph structure, and laying out the combined folded transistors as separate components to generate a target transistor layout.

[0076] Specifically, a first target combination mode of a plurality of first sub-transistors in each first folding transistor may be determined based on the first sub-graph structure, and the plurality of first sub-transistors in each first folding transistor may be combined according to the first target combination mode. Then, a second target combination mode of a plurality of second sub-transistors in each second folding transistor may be determined based on the second sub-graph structure, and the plurality of second sub-transistors in each second folding transistor may be combined according to the second target combination mode.

[0077] When combining folded transistors, the number of Euler paths in the graph should be minimized. By reducing Euler paths, the number of gaps (GAPs) that must appear in the layout can be reduced, and reducing the number of gaps helps to achieve a more compact and efficient circuit layout. Therefore, the purpose of combining folded transistors is to reduce the number of odd-degree points (nodes with an odd number of connecting edges) as much as possible while maintaining the connectivity of the graph structure, thereby reducing the wiring gaps.

[0078] In the specific implementation process, all nodes in the graph structure can be traversed first, and the number of connected edges of each node can be counted to determine the odd-degree points according to the number of connected edges of each node, thereby obtaining the number of odd-degree points in the graph structure.

[0079] For example, for the first folding transistor, the number of odd-degree points in the first subgraph structure can be determined first; then, based on the number of odd-degree points and the connectivity of the first subgraph structure, the combination of several first sub-transistors in each first folding transistor is traversed to determine the first target combination.

[0080] For the second folding transistor, the number of odd-degree points in the second subgraph structure can be determined first; then based on the number of odd-degree points and the connectivity of the second subgraph structure, the combination of several second sub-transistors in each second folding transistor is traversed to determine the second target combination.

[0081] Specifically, you can traverse the connection of each odd-degree point and try different combinations. After the combination, recalculate the connectivity of the graph structure and the number of odd-degree points, and choose a combination that can reduce or maintain the number of odd-degree points. For example, assuming that transistors M1 and M2 share a diffusion: you can first check whether their source and drain belong to the same signal. If the sharing condition is met, merge their connections into one edge.

[0082] In the embodiments of the present application, the combination modes may include Diffusion Share, Poly Gate Share and VDD / GND Share. Diffusion Share refers to multiple transistors sharing the same source or drain. Poly Gate Share refers to transistor combination by connecting gates. VDD / GND Share refers to transistor combination by sharing power supply or ground.

[0083] For example, take the first folding transistor as an example for illustration.

[0084] like Figure 4 As shown, there are two ways to combine transistor M1. The left picture is a combination of net18 diffusion share, and the right picture is a combination of net11 diffusion share. The combination of the left picture causes the graph to be disconnected, so it is discarded. The right picture is connected, and the number of odd-numbered points is not increased, so the transistor M1 can be combined in the way of the right picture (the first target combination). Figure 5As shown, for transistor M2, there are two combinations as follows. It can be seen that no matter which combination method is used for transistor M2, the graph will be disconnected, so transistor M2 cannot be combined and can only be regarded as two separate transistors during layout. Figure 6 As shown, for the transistor M3, there are the following two combination methods, both of which can be selected.

[0085] Therefore, the final combination of the first folding transistors is that all transistors M1 are combined together, all transistors M3 are combined together, and transistors M2 cannot be combined.

[0086] It is understandable that if there are multiple combinations that meet the conditions, the combination that can reduce the wiring length or optimize the layout can be preferentially selected as the target combination.

[0087] Considering the symmetry of pmos transistors and nmos transistors, if pmos transistors and nmos transistors are combined according to the above steps, it is very likely that only a layout solution with a larger width can be solved. Therefore, in the actual application process, after obtaining the above combination method, the combination method can be fine-tuned in combination with the empirical strategy (engineer's experience).

[0088] That is, in some embodiments, the step of "laying out the combined folded transistor as a separate element to generate a target transistor layout" can be specifically as follows: based on the symmetry of the first folded transistor and the second folded transistor, fine-tuning the combination of the first folded transistor and / or the second folded transistor to obtain the first combined transistor and the second combined transistor; laying out the first combined transistor and the second combined transistor as separate elements to generate a target transistor layout.

[0089] It should be noted that the first combined transistor and the second combined transistor refer to transistors that have been combined, including not only transistor groups that have been successfully combined, but also single transistors that have not been successfully combined.

[0090] In summary, the transistor layout method provided by the embodiment of the present application includes obtaining an initial standard unit circuit; determining the transistor to be folded in the initial standard unit circuit; folding the transistor to be folded according to the folding strategy to obtain several folded transistors; modeling the folded transistor according to the graph theory algorithm to generate a graph structure; combining several of the folded transistors based on the graph structure, and laying out the combined folded transistors as separate elements to generate a target transistor layout. This solution can reduce the layout area occupied by a single transistor by folding a large-size transistor into multiple small transistors and combining them according to rules. The arrangement of the folded transistors is more flexible, which helps to reduce the complexity of the overall layout. In addition, the folded transistors are abstracted into a graph structure, and the relationship between nodes and edges is analyzed by the graph theory algorithm, the connection path and layout are optimized, and the manual adjustment workload in the layout process is significantly reduced, thereby improving the layout generation speed, which is suitable for high-complexity integrated circuit design. In addition, by optimizing odd-degree points and diffusion sharing, the wiring path is effectively shortened, the wiring intersection is reduced, and the layout complexity of the transistor is reduced. That is, this solution can reduce the layout complexity of the transistor by combining transistor folding with the graph theory algorithm.

[0091] In order to better implement the transistor layout method provided in the embodiment of the present application, the embodiment of the present application also provides a transistor layout device, wherein the meanings of the terms are the same as those in the above transistor layout method, and the specific implementation details can refer to the description in the method embodiment.

[0092] See also Figure 7 , Figure 7 20 is a schematic diagram of the structure of a transistor layout device provided in an embodiment of the present application. The transistor layout device may include an acquisition unit 201, a determination unit 202, a folding unit 203, a modeling unit 204 and a combination unit 204.

[0093] An acquisition unit 201 is used to acquire an initial standard unit circuit;

[0094] A determination unit 202, used to determine the transistor to be folded in the initial standard unit circuit;

[0095] A folding unit 203, configured to fold the transistors to be folded according to the folding strategy to obtain a plurality of folded transistors;

[0096] A modeling unit 204, configured to model the folded transistor according to a graph theory algorithm and generate a graph structure;

[0097] The combining unit 205 is used to combine a plurality of folded transistors based on the graph structure, and layout the combined folded transistors as separate elements to generate a target transistor layout.

[0098] The specific implementation of each of the above units can refer to the above-mentioned embodiment of the transistor layout method, which will not be described one by one here.

[0099] In summary, the transistor layout device provided in the embodiment of the present application can obtain the initial standard unit circuit through the acquisition unit 201; the determination unit 202 determines the transistor to be folded in the initial standard unit circuit; the folding unit 203 folds the transistor to be folded according to the folding strategy to obtain a plurality of folded transistors; the modeling unit 204 models the folded transistor according to the graph theory algorithm to generate a graph structure; the combination unit 205 combines the plurality of folded transistors based on the graph structure, and lays out the combined folded transistors as separate elements to generate a target transistor layout. This solution can reduce the layout complexity of transistors by combining transistor folding with the graph theory algorithm.

[0100] The present application also provides an electronic device, in which the transistor layout device of the present application can be integrated, such as Figure 8 As shown, it shows a schematic diagram of the structure of the electronic device involved in the embodiment of the present application, specifically:

[0101] The electronic device may include one or more processors 301 of processing cores and one or more computer-readable storage media memories 302 and other components. Those skilled in the art will appreciate that Figure 8 The electronic device structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0102] The processor 301 is the control center of the electronic device, which uses various interfaces and lines to connect various parts of the entire electronic device, and executes various functions of the electronic device and processes data by running or executing the software program and / or the present application stored in the memory 302, and calling the data stored in the memory 302, so as to monitor the electronic device as a whole. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operation storage medium, user interface and application program, etc., and the modem processor mainly processes wireless communication. It is understandable that the above-mentioned modem processor may not be integrated into the processor 301.

[0103] The memory 302 can be used to store software programs and the present application. The processor 301 executes various functional applications and data processing by running the software programs and the present application stored in the memory 302. The memory 302 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating storage medium, an application required for at least one function, etc.; the data storage area may store data created according to the use of the electronic device, etc. In addition, the memory 302 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices. Accordingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0104] Although not shown, the electronic device may further include a display unit, an input unit, a power supply, etc., which will not be described in detail herein. Specifically in this embodiment, the processor 301 in the electronic device will load the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 will run the application programs stored in the memory 302, thereby realizing various functions, as follows:

[0105] Obtaining an initial standard unit circuit;

[0106] determining transistors to be folded in an initial standard unit circuit;

[0107] Folding the transistor to be folded according to the folding strategy to obtain a plurality of folded transistors;

[0108] Model the folded transistor based on graph theory algorithms to generate a graph structure;

[0109] A plurality of folded transistors are combined based on a graph structure, and the combined folded transistors are laid out as separate components to generate a target transistor layout.

[0110] A person of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be completed by instructions, or by controlling related hardware through instructions. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0111] To this end, an embodiment of the present application provides a storage medium in which a plurality of instructions are stored, and the instructions can be loaded by a processor to execute the steps in any method provided in the embodiment of the present application. For example, the instructions can execute the following steps:

[0112] Obtaining an initial standard unit circuit;

[0113] determining transistors to be folded in an initial standard unit circuit;

[0114] Folding the transistor to be folded according to the folding strategy to obtain a plurality of folded transistors;

[0115] Model the folded transistor based on graph theory algorithms to generate a graph structure;

[0116] A plurality of folded transistors are combined based on a graph structure, and the combined folded transistors are laid out as separate components to generate a target transistor layout.

[0117] The specific implementation of the above operations can be found in the previous embodiments, which will not be described in detail here.

[0118] The storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0119] Since the instructions stored in the storage medium can execute the steps in any method provided in the embodiments of the present application, the beneficial effects that can be achieved by any method provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0120] The transistor layout method, device, storage medium and electronic device provided by the present application are respectively introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the core idea of ​​the present application; at the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A transistor layout method, characterized in that: include: Obtaining an initial standard unit circuit; determining a transistor to be folded in the initial standard unit circuit; Folding the transistors to be folded according to the folding strategy to obtain a plurality of folded transistors; Modeling the folded transistor according to a graph theory algorithm to generate a graph structure; A plurality of the folding transistors are combined based on the graph structure, and the combined folding transistors are laid out as separate elements to generate a target transistor layout.

2. The transistor layout method according to claim 1, wherein: The step of modeling the folded transistor according to a graph theory algorithm to generate a graph structure includes: Classifying the plurality of folding transistors according to transistor types into first folding transistors and second folding transistors; The first folding transistor and the second folding transistor are modeled based on a graph theory algorithm to obtain a graph structure, where the graph structure includes a first sub-graph structure and a second sub-graph structure.

3. The transistor layout method according to claim 2, characterized in that: The combining process of the plurality of folding transistors based on the graph structure comprises: Determine a first target combination mode of a plurality of first sub-transistors in each of the first folding transistors based on the first sub-graph structure, and combine a plurality of first sub-transistors in each of the first folding transistors according to the first target combination mode; A second target combination of the second sub-transistors in each of the second folding transistors is determined based on the second sub-graph structure, and the second sub-transistors in each of the second folding transistors are combined according to the second target combination.

4. The transistor layout method according to claim 3, wherein: The determining, based on the first sub-graph structure, a first target combination of a plurality of first sub-transistors in each of the first folding transistors comprises: Determining the number of odd-degree points in the first subgraph structure; Based on the number of odd-degree points and the connectivity of the first subgraph structure, the combination of a plurality of first sub-transistors in each of the first folding transistors is traversed to determine a first target combination.

5. The transistor layout method according to claim 3, wherein: The determining, based on the second subgraph structure, a second target combination of a plurality of second sub-transistors in each of the second folding transistors comprises: Determining the number of odd-degree points in the second subgraph structure; Based on the number of odd-degree points and the connectivity of the second subgraph structure, the combination of a plurality of second sub-transistors in each of the second folding transistors is traversed to determine a second target combination.

6. The transistor layout method according to claim 2, wherein: The first folding transistor and the second folding transistor are modeled based on a graph theory algorithm to obtain a first subgraph structure and a second subgraph structure, including: Representing the source and drain of each first sub-transistor in the first folded transistor as a node, and representing each first sub-transistor as an edge connecting the nodes, to form a first sub-graph structure; The source and drain of each second sub-transistor in the second folded transistor are represented as nodes, and each second sub-transistor is represented as an edge connecting the nodes to form a second sub-graph structure.

7. The transistor layout method according to claim 2, wherein: The step of laying out the combined folded transistors as separate elements to generate a target transistor layout comprises: Based on the symmetry of the first folding transistor and the second folding transistor, fine-tune the combination of the first folding transistor and / or the second folding transistor to obtain a first combined transistor and a second combined transistor; The first combined transistor and the second combined transistor are laid out as separate elements to generate a target transistor layout.

8. A transistor layout device, characterized in that: include: An acquisition unit, used for acquiring an initial standard unit circuit; A determination unit, used for determining the transistor to be folded in the initial standard unit circuit; A folding unit, used for folding the transistor to be folded according to a folding strategy to obtain a plurality of folded transistors; A modeling unit, used for modeling the folded transistor according to a graph theory algorithm to generate a graph structure; A combining unit is used to combine a plurality of the folding transistors based on the graph structure, and layout the combined folding transistors as separate elements to generate a target transistor layout.

9. A storage medium, characterized in that: The storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor to execute the transistor layout method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the transistor layout method according to any one of claims 1 to 7 is implemented.

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