Artificial intelligence chip and pooling method thereof

Abstract

The invention provides an artificial intelligence chip and a pooling method thereof. The artificial intelligence chip comprises an instruction scheduling module, an instruction decoding module, a register block, a pooling control circuit and a floating point arithmetic unit. The instruction decoding module decodes the pooling instruction of the instruction scheduling module to generate a decoding result. Based on the decoding result, the pooling control circuit determines the number of execution cycles of the pooling instruction and reads the feature map value from the register set. The pooling control circuit provides the execution cycle number and a plurality of feature points of the receptive field of the feature map numerical value to the floating point arithmetic unit. The floating point arithmetic unit pools the plurality of feature points of the receptive field based on the execution cycle number to generate a pooling result of the receptive field.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to an artificial intelligence chip and a pooling method thereof. Background Art

[0002] Artificial Intelligence (AI) chips can provide huge computing power. The huge computing power of AI chips comes from a large number of internal hardware cores. An AI chip usually contains multiple programmable processors, such as a stream processor cluster (SPC). Each programmable processor usually contains multiple compute units (CU, or compute cores), and each compute unit usually contains multiple execution units (EU, or execution cores), such as integer (INT) core, floating point (FP) core, tensor core (Tcore) and vector core (Vcore). By organizing various types of computing units through programming, AI chips can support general computing, scientific computing and neural network computing.

[0003] Neural network calculations perform convolution, activation, pooling and other calculations. Pooling operations are very common in convolutional neural networks. Pooling is a non-linear downsampling operation. "Pooling" originated from computer vision and refers to the merging and integration of resources, imitating the human visual system to reduce the dimension of data. The pooling operation moves the pooling window to different positions of the data matrix (such as tensors and feature maps) according to the stride, and becomes a different receptive field. Then, after each movement of the pooling window, multiple data elements (such as feature points) in the receptive field are pooled (such as taking the maximum value or averaging) to obtain a data element of the pooling matrix. After the pooling window completely scans the entire data matrix according to the stride, the execution unit can store the pooling matrix in the memory. The pooling operation reduces the dimensional size of the data matrix, thereby reducing the number of parameters and the amount of calculation of the neural network calculation. The pooling operation can control overfitting to a certain extent.

[0004] Common pooling operations include max pooling, average pooling, or other pooling algorithms. Suppose the size of the receptive field is K×K, and the data elements in the receptive field are P_1, P_2, P_3, …, P_k×k. The result of average pooling is (P_1+P_2+P_3+…+P_k×k) / (K×K). It is generally believed that average pooling can better preserve the background information of the feature map. The result of max pooling is MAX(P_1, P_2, P_3, …,P_k×k), which is the maximum value among the K×K feature points. It is generally believed that max pooling can better preserve the texture information of the feature map.

[0005] Conventional technology is to use the conventional floating-point hardware of the central processing unit (CPU) or graphics processing unit (GPU) to complete the pooling operation. The disadvantage of this method is that it requires multiple general floating-point instructions to meet application requirements. If the receptive field is 3×3 (assuming that the data elements in the receptive field are P1, P2, P3, P4, P5, P6, P7, P8 and P9), mean pooling requires "tmp1=P1+P2", "tmp2=P3+tmp1", "tmp3=P4+tmp2", "tmp4=P5+tmp3", "tmp5=P6+tmp4", "tmp6=P7+tmp5", "tmp7=P8+tmp6", "tmp8=P9+tmp7" and "result=(1 / 9)×tem8", a total of 9 regular floating-point operation instructions; maximum pooling requires "tmp1=MAX(P1, P2)", "tmp2=MAX(P3, tmp1)", "tmp3=MAX(P4, tmp2)", "tmp4=MAX(P5, tmp3)", "tmp5=MAX(P6, There are 8 instructions in total, namely, “tmp4=MAX(P7, tmp5)”, “tmp7=MAX(P8, tmp6)” and “result=MAX(P9, tmp7)”. It can be seen that the disadvantage of conventional technology is that many instructions lead to long calculation time. How to perform pooling operation is one of many technical issues in this field. Summary of the invention

[0006] The present invention is directed to an artificial intelligence chip and a pooling method thereof, so as to perform a pooling operation on multiple feature points of feature map values.

[0007] In an embodiment according to the present invention, an artificial intelligence chip includes an instruction scheduling module, an instruction decoding module, a register file, a pooling control circuit, and a first floating point operation unit. The instruction decoding module is coupled to the instruction scheduling module to receive a pooling instruction. The instruction decoding module decodes the pooling instruction to generate a decoding result. The pooling control circuit is coupled to the instruction decoding module and the register file. The first floating point operation unit is coupled to the pooling control circuit. The pooling control circuit determines the number of execution cycles of the pooling instruction based on the decoding result, and provides the number of execution cycles to the first floating point operation unit. The pooling control circuit reads a feature map value from the register file based on the decoding result, and provides a plurality of feature points of a first receptive field of the feature map value to the first floating point operation unit. The first floating point operation unit performs a pooling operation on a plurality of feature points of the first receptive field based on the number of execution cycles to generate a pooling result of the first receptive field.

[0008] In an embodiment according to the present invention, the pooling method includes: decoding a pooling instruction by an instruction decoding module of an artificial intelligence chip to generate a decoding result; determining the number of execution cycles of the pooling instruction based on the decoding result by a pooling control circuit of the artificial intelligence chip; providing the number of execution cycles to a first floating-point operation unit by the pooling control circuit; reading a feature map value from a register group based on the decoding result by the pooling control circuit; providing multiple feature points of a first receptive field of the feature map value to the first floating-point operation unit by the pooling control circuit; and performing a pooling operation on the multiple feature points of the first receptive field based on the number of execution cycles by the first floating-point operation unit to generate a pooling result of the first receptive field.

[0009] Based on the above, the pooling control circuit of the embodiments of the present invention determines the number of execution cycles of the pooling instruction and reads the feature map value based on the decoding result of the pooling instruction, and the pooling control circuit determines the first receptive field based on the step size moving pooling window. The pooling control circuit provides multiple feature points of the first receptive field of the feature map value to the first floating-point operation unit, and the first floating-point operation unit performs a pooling operation (e.g., mean pooling or maximum pooling) on ​​the feature points of the first receptive field based on the number of execution cycles. In some embodiments, the artificial intelligence chip is arranged with multiple floating-point operation units, and the pooling control circuit determines different receptive fields based on the step size moving pooling window. The pooling control circuit provides the feature points of each receptive field in the multiple receptive fields to the corresponding floating-point operation unit, so that different floating-point operation units can simultaneously perform pooling operations on feature points of different receptive fields. In some embodiments, a small amount of control and calculation logic is added to the standard floating-point operation unit to realize a hardware resource dedicated to pooling operations (including mean pooling and maximum pooling), thereby accelerating the pooling process. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of a circuit block of an artificial intelligence chip according to an embodiment of the present invention; Figure 2 It is a flow chart of a pooling method of an artificial intelligence chip according to an embodiment of the present invention; Figure 3 is a circuit block diagram of a pooling control circuit according to an embodiment of the present invention; Figure 4 is a circuit block diagram of a floating-point operation unit according to an embodiment of the present invention; Figure 5 is a circuit block diagram of a floating-point operation unit according to another embodiment of the present invention; Figure 6 is a circuit block diagram of a floating-point operation unit according to another embodiment of the present invention; Figure 7 is a circuit block diagram of a mean pooling circuit and a maximum pooling circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0011] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0012] The term "coupled (or connected)" used in the entire specification of this case (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. The terms "first", "second", etc. mentioned in the entire specification of this case (including the claims) are used to name the components (element) or to distinguish different embodiments or ranges, and are not used to limit the upper or lower limit of the number of components, nor to limit the order of components.

[0013] In addition, it should be noted that the parameter type of the artificial intelligence chip and the pooling method thereof provided in at least one embodiment of this case is a floating point number, and the parameter type may have different specific physical meanings depending on the application scenario. For example, the AI ​​chip and the pooling method thereof provided in at least one embodiment of this case can be applied in the fields of speech processing, image processing, text processing, video processing, etc.

[0014] For example, in the field of speech processing, parameters can be any parameters used, input, or generated in tasks such as feature extraction, speech enhancement, and speech recognition, such as speech feature vectors, filtering parameters, and the like.

[0015] For example, in the field of image processing, parameters can be any parameters used, input, or generated in tasks such as image preprocessing, feature extraction, image segmentation, and target detection, such as image feature vectors, various edge detection operators (such as Sobel operator, Canny operator, Prewitt operator, etc.), image filtering operators (such as Gaussian filtering, median filtering, bilateral filtering, etc.), morphological operators (such as corrosion, expansion, opening operation, closing operation, etc.), etc.

[0016] For example, in the field of text processing, parameters can be any parameters used, input, or generated in tasks such as text classification, sentiment analysis, and text generation, such as the semantic feature vector of the text.

[0017] For example, in the field of video processing, the parameters may be parameters in the field of image processing as described above, or parameters used, inputted, or generated in the field of video processing, such as an optical flow operator (used to estimate motion between video frames) or a target tracking operator (used to track a specific target in a video).

[0018] Of course, the present invention is not limited to this. For other application scenarios or fields, as long as pooling is required, the pooling method described in at least one embodiment of the present invention can be applied, and will not be described in detail here.

[0019] Figure 11 is a circuit block diagram of an artificial intelligence chip 100 according to an embodiment of the present invention. In different application examples, the artificial intelligence chip 100 can be used as a graphics processor, a general-purpose graphics processor (GPGPU) or other processing circuits. The artificial intelligence chip 100 can provide huge computing power. The huge computing power of the artificial intelligence chip 100 comes from a large number of internal hardware cores.

[0020] exist Figure 1 In the illustrated embodiment, the artificial intelligence chip 100 includes an instruction scheduling module 110, an instruction decoding module 120, a pooling control circuit 130, a register group 140, and a plurality of floating point operation units, for example Figure 1 The floating point operation unit 150_1, floating point operation unit 150_2, ..., floating point operation unit 150_N are shown. The number N of floating point operation units 150_1 to floating point operation units 150_N can be any integer determined based on actual design and application. Floating point operation units 150_1 to floating point operation units 150_N are coupled to the pooling control circuit 130 and the register group 140. The pooling control circuit 130 is coupled to the instruction decoding module 120 and the register group 140. The instruction decoding module 120 is coupled to the instruction scheduling module 110 to receive the pooling instruction. In this embodiment, the pooling instruction includes two instructions, POOL.MEAN and POOL.MAX. The POOL.MEAN instruction is used to perform mean pooling operation, and the POOL.MAX instruction is used to perform maximum pooling operation.

[0021] Figure 2 This is a flow chart of a pooling method for an artificial intelligence chip according to an embodiment of the present invention. Figure 1 and Figure 2 In step S210, the instruction decoding module 120 decodes the pooling instruction from the instruction scheduling module 110 to generate a decoding result. The pooling instruction supports different parameter configurations, including pooling type, receptive field size, padding bit width, step size, neural network operation direction (forward or reverse) and multiple data formats (including fp16, fp8, int8, int4), which can adapt to different convolutional neural network (CNN) application requirements. In step S220, the pooling control circuit 130 determines the number of execution cycles of the pooling instruction, the pooling type (enabling mean or maximum value calculation resources) and other related parameters based on the decoding result of the pooling instruction, and reads the feature map value (generally a data matrix) from the register group 140.

[0022] Assuming that the size of the receptive field is K×K, and the number of feature points received or processed by any one of the floating-point arithmetic units 150_1 to 150_N in each cycle of the iterative operation is L, the number of execution cycles is (K×K) / L. For example, assuming that the size of the receptive field is 3×3 feature points, and the number of feature points received or processed by any one of the floating-point arithmetic units 150_1 to 150_N in each cycle of the iterative operation is 3, the number of execution cycles is (3×3) / 3=3, that is, 1 iterative operation is performed 3 times.

[0023] In step S230, the pooling control circuit 130 provides relevant parameters such as the number of execution cycles and the pooling type (enabling mean or maximum value calculation resources) to the floating-point operation unit 150_1 to the floating-point operation unit 150_N. In addition, the pooling control circuit 130 moves the pooling window based on the step size parameter of the pooling instruction to determine different receptive fields in the feature map. The pooling control circuit 130 also provides each of the floating-point operation units 150_1 to the floating-point operation unit 150_N with multiple feature points of the corresponding receptive field of the feature map value in step S230. For example, the pooling control circuit 130 provides multiple feature points of the first receptive field of the feature map value to the floating-point operation unit 150_1, and provides multiple feature points of the second receptive field of the feature map value to the floating-point operation unit 150_2.

[0024] In step S240, the floating-point operation units 150_1 to 150_N perform pooling operations on feature points of different receptive fields based on the number of execution cycles to generate pooling results of different receptive fields. For example, the floating-point operation unit 150_1 performs pooling operations on multiple feature points of the first receptive field based on the number of execution cycles to generate the pooling result of the first receptive field. Similarly, the floating-point operation unit 150_2 performs pooling operations on multiple feature points of the second receptive field based on the number of execution cycles to generate the pooling result of the second receptive field.

[0025] In summary, the pooling control circuit 130 determines the number of execution cycles of the pooling instruction and reads the feature map value based on the decoding result of the pooling instruction, and the pooling control circuit 130 moves the pooling window based on the step parameter to determine the first receptive field. The pooling control circuit 130 provides multiple feature points of a receptive field of the feature map value to the floating-point operation unit 150_1, and the floating-point operation unit 150_1 performs a pooling operation (such as mean pooling or maximum pooling) on ​​the feature points of this receptive field based on the number of execution cycles to generate a pooling result. Similarly, the pooling control circuit 130 provides multiple feature points of another receptive field of the feature map value to the floating-point operation unit 150_2, and the floating-point operation unit 150_2 performs a pooling operation on multiple feature points of this other receptive field based on the number of execution cycles to generate a pooling result. The pooling control circuit 130 provides feature points of multiple receptive fields to the floating-point operation units 150_1 to 150_N, so that different floating-point operation units 150_1 to 150_N can simultaneously perform pooling operations on feature points of different receptive fields, thereby accelerating the pooling process.

[0026] Figure 3 is a circuit block diagram of a pooling control circuit 130 according to an embodiment of the present invention. Figure 3 The instruction scheduling module 110, the instruction decoding module 120, the pooling control circuit 130, the register group 140 and the floating point operation unit 150_1 to the floating point operation unit 150_N can refer to Figure 1 The relevant instructions are already given, so I will not repeat them here. Figure 3 The pooling control circuit 130 shown can be used as Figure 1 One of many implementation examples of the pooling control circuit 130 is shown. Figure 3 In the illustrated embodiment, the pooling control circuit 130 includes a pooling operation control module 131, an operand acquisition module 132, and a feature map input control module 133. According to different designs, in some embodiments, at least one of the instruction scheduling module 110, the instruction decoding module 120, the pooling control circuit 130, the pooling operation control module 131, the operand acquisition module 132, and the feature map input control module 133 may be implemented in a hardware circuit, firmware, software (i.e., program), or a combination of the foregoing.

[0027] In terms of hardware, at least one of the above-mentioned instruction scheduling module 110, instruction decoding module 120, pooling control circuit 130, pooling operation control module 131, operand acquisition module 132 and feature map input control module 133 can be implemented in a logic circuit on an integrated circuit. For example, the relevant functions of at least one of the instruction scheduling module 110, instruction decoding module 120, pooling control circuit 130, pooling operation control module 131, operand acquisition module 132 and feature map input control module 133 can be implemented in various logic blocks, modules and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASIC), digital signal processors (DSP), field programmable gate arrays (FPGA), central processing units or other processing units. The relevant functions of at least one of the instruction scheduling module 110, the instruction decoding module 120, the pooling control circuit 130, the pooling operation control module 131, the operand acquisition module 132 and the feature map input control module 133 can be implemented as hardware circuits, such as various logic blocks, modules and circuits in an integrated circuit, using hardware description languages ​​(Hardware Description Languages, such as Verilog HDL or VHDL) or other suitable programming languages.

[0028] In software or firmware form, the relevant functions of at least one of the above-mentioned instruction scheduling module 110, instruction decoding module 120, pooling control circuit 130, pooling operation control module 131, operand acquisition module 132 and feature map input control module 133 can be implemented as programming codes. For example, at least one of the instruction scheduling module 110, instruction decoding module 120, pooling control circuit 130, pooling operation control module 131, operand acquisition module 132 and feature map input control module 133 is implemented using general programming languages ​​(such as C, C++ or assembly language) or other suitable programming languages. The programming code can be recorded or stored in a "non-transitory machine-readable storage medium". In some embodiments, the non-transitory machine-readable storage medium includes, for example, a semiconductor memory and (or) a storage device. An electronic device (such as a computer, a CPU, a hardware controller, a microcontroller, a hardware processor or a microprocessor) can read and execute the programming code from the non-temporary machine-readable storage medium, thereby realizing the relevant functions of at least one of the instruction scheduling module 110, the instruction decoding module 120, the pooling control circuit 130, the pooling operation control module 131, the operand acquisition module 132 and the feature map input control module 133.

[0029] The pooling operation control module 131 is coupled to the instruction decoding module 120 to receive the decoding result. The pooling instruction is sent to the pooling operation control module 131 through the instruction scheduling module 110 and the instruction decoding module 120 for further decoding of the pooling parameters. The pooling operation control module 131 determines the number of execution cycles of the pooling instruction based on the decoding result of the pooling instruction, and then provides the number of execution cycles to the floating-point operation unit 150_1 to the floating-point operation unit 150_N. The pooling operation control module 131 will also directly broadcast the pooling computing resource control information to all floating-point operation units 150_1 to the floating-point operation unit 150_N. For example, the pooling operation control module 131 will determine the number of execution cycles of the current instruction based on the parameters such as the size of the receptive field and the step size in the instruction, and send this instruction in a loop until the current channel-by-channel convolution is completed.

[0030] The operand acquisition module 132 is coupled to the pooling operation control module 131 and the register group 140. The operand acquisition module 132 reads the feature map value from the register group 140 based on the control of the pooling operation control module 131. For example, the pooling operation control module 131 calculates the address of the feature map according to the parameter, and then sends the address to the operand acquisition module 132, so that the operand acquisition module 132 reads the feature map value from the register group 140. The feature map input control module 133 is coupled to the operand acquisition module 132 to receive the feature map value. The feature map input control module 133 provides the feature points of different receptive fields of the feature map value to the floating point operation unit 150_1 to the floating point operation unit 150_N. For example, the feature map input control module 133 provides multiple feature points of the first receptive field of the feature map value to the floating point operation unit 150_1. Similarly, the feature map input control module 133 provides multiple feature points of the second receptive field of the feature map value to the floating point operation unit 150_2.

[0031] After receiving the relevant feature map, the feature map input control module 133 selects corresponding feature points for each floating-point operation unit 150_1 to floating-point operation unit 150_N according to the current number of cycles. For example, assuming that the size of the receptive field is 3×3 feature points, the data elements (feature points) in a certain receptive field of the feature map value are P1, P2, P3, P4, P5, P6, P7, P8 and P9, and the number of feature points received or processed by the floating-point operation unit 150_1 in each cycle of the iterative operation is 3. In the first cycle of the iterative operation, the feature map input control module 133 provides the feature points P1, P2 and P3 to the floating-point operation unit 150_1. In the second cycle of the iterative operation, the feature map input control module 133 provides the feature points P4, P5 and P6 to the floating-point operation unit 150_1. In the third cycle of the iterative operation, the feature map input control module 133 provides the feature points P7, P8 and P9 to the floating-point operation unit 150_1. The operation of the feature map input control module 133 on other floating point operation units 150_2 to floating point operation units 150_N can refer to the operation description of the feature map input control module 133 on the floating point operation unit 150_1 and be analogized, so it is not repeated. The floating point operation unit 150_1 to the floating point operation unit 150_N can receive three feature points from the feature map input control module 133 and perform pooling operations in each cycle. After three cycles, the floating point operation unit 150_1 to the floating point operation unit 150_N can complete the pooling operations of different receptive fields and output the pooling results of different receptive fields to the register group 140.

[0032] In some embodiments, a small amount of control and calculation logic can be added to the standard floating-point unit to implement floating-point units 150_1 to 150_N as hardware specifically for pooling operations (including mean pooling and maximum pooling), thereby accelerating the pooling process. The pooling control circuit 130 supports different parameter configurations, including pooling type, receptive field size, zero padding width, step size, neural network operation direction (forward or reverse), and multiple data formats (including fp16, fp8, int8, int4). The pooling control circuit 130 can adapt to the application requirements of different convolutional neural networks and is very flexible.

[0033] Figure 4 FIG. 4 is a circuit block diagram of a floating-point operation unit 400 according to an embodiment of the present invention. Figure 4 The floating point unit 400 shown may refer to Figure 1 or Figure 3 The relevant descriptions of any one of the floating-point operation units 150_1 to 150_N are given and can be deduced by analogy. Figure 4 The floating point unit 400 shown may be used as Figure 1 or Figure 3 One of many implementation examples of any one of the floating point operation units 150_1 to 150_N shown. Figure 4 In the illustrated embodiment, the floating point operation unit 400 includes a carry save adder (CSA) 410, an adder 420, a multiplexer 430, a multiplexer 440, an adder 450, a floating point number normalization circuit 460, a loop intermediate result memory access circuit 470, a multiplier 480, and a multiplexer 490. In this embodiment, the adder 450, the floating point number normalization circuit 460, the multiplier 480, and the multiplexer 490 may be components of a standard floating point operation unit, while the carry save adder 410, the adder 420, the multiplexer 430, the multiplexer 440, and the loop intermediate result memory access circuit 470 are added to the standard floating point operation unit to be implemented as hardware dedicated to the mean pooling operation.

[0034] The instruction decoding module 120 decodes the pooling instruction POOL.MEAN from the instruction scheduling module 110 to generate a decoding result. Based on the decoding result of the pooling instruction POOL.MEAN, the pooling control circuit 130 determines the number of execution cycles of the pooling instruction and reads the feature points of the feature map values ​​from the register group 140 to the carry-save adder 410. The carry-save adder 410 is coupled to the pooling control circuit 130 to receive a plurality of feature points of the corresponding receptive field, such as feature point IN41, feature point IN42, and feature point IN43. The carry-save adder 410 generates a sum value tmp41 and a carry value tmp42 based on the plurality of feature points of the corresponding receptive field, that is, IN41 + IN42 + IN43 = tmp41 + tmp42. The adder 420 is coupled to the carry-save adder 410 to receive the sum value tmp41 and the carry value tmp42. The adder 420 generates a sum tmp43 based on the sum tmp41 and the carry tmp42, that is, tmp41 + tmp42 = tmp43. The first input of the multiplexer 430 is coupled to the adder 420 to receive the sum tmp43. The output of the multiplexer 430 is coupled to the first input of the adder 450. The first input of the multiplexer 440 is coupled to the output of the loop intermediate result access circuit 470. The loop intermediate result access circuit 470 provides the sum tmp44 of the previous execution cycle in multiple cycles (execution cycles) of the average pooling operation. In the case of the first cycle of the average pooling operation performed by the floating-point operation unit 400, the sum tmp44 is zero. The output of the multiplexer 440 is coupled to the second input of the adder 450.

[0035] In the case where the floating-point arithmetic unit 400 is used as hardware dedicated to the average pooling operation, the multiplexer 430 transmits the sum tmp43 to the first input terminal of the adder 450, and the multiplexer 440 transmits the sum tmp44 of the previous execution cycle to the second input terminal of the adder 450. In the case where the floating-point arithmetic unit 400 is used as a standard floating-point arithmetic unit, and in the case where this standard floating-point arithmetic unit performs floating-point addition "a + b", the second input terminal of the multiplexer 430 receives the floating-point number a, and the second input terminal of the multiplexer 440 receives the floating-point number b. At this time, the multiplexer 430 transmits the floating-point number a to the first input terminal of the adder 450, and the multiplexer 440 transmits the floating-point number b to the second input terminal of the adder 450.

[0036] The input end of the floating point number normalization circuit 460 is coupled to the output end of the adder 450 to receive the sum value tmp45. The output end of the floating point number normalization circuit 460 is coupled to the input end of the loop intermediate result access circuit 470 and the first input end of the multiplexer 490. The floating point number normalization circuit 460 normalizes the sum value tmp45 based on the floating point number standard format to generate a normalized sum value tmp45′ to the loop intermediate result access circuit 470 and the multiplexer 490.

[0037] The instruction decoding module 120 decodes the floating-point multiplication instruction FMUL from the instruction scheduling module 110 regarding the mean pooling operation to generate a decoding result. Based on the decoding result of the floating-point multiplication instruction FMUL, the pooling control circuit 130 reads the feature point sum SUM41 from the register group 140 to the multiplier 480. The first input end of the multiplier 480 receives the feature point sum SUM41 of the receptive field corresponding to the floating-point operation unit 400 from the pooling control circuit 130. The second input end of the multiplier 480 receives the average coefficient AC41 of the corresponding receptive field from the pooling control circuit 130. The second input end of the multiplexer 490 is coupled to the output end of the multiplier 480.

[0038] For example, assuming that the size of the corresponding receptive field is 3×3 feature points, and assuming that the data elements in the corresponding receptive field are P1, P2, P3, P4, P5, P6, P7, P8 and P9, the mean pooling operation of the corresponding receptive field includes summing iterations and multiplications, and the summing iterations include 3 summing cycles, and the average coefficient AC41 of the corresponding receptive field is 1 / (3×3) =1 / 9. In the first summing cycle, the feature point IN41, the feature point IN42 and the feature point IN43 are P1, P2 and P3 respectively, the loop intermediate result access circuit 470 provides the sum tmp44 with a value of zero to the multiplexer 440, and the floating point number normalization circuit 460 writes the sum tmp45' (i.e., P1 + P2 + P3) of the first summing cycle into the loop intermediate result access circuit 470. In the second summing cycle, the characteristic points IN41, IN42 and IN43 are P4, P5 and P6 respectively, the loop intermediate result memory access circuit 470 provides the sum value tmp44 (i.e., P1 + P2 + P3) of the first summing cycle to the multiplexer 440, and the floating point number normalization circuit 460 writes the sum value tmp45' (i.e., P4 + P5 + P6 + tmp44 = P1 + P2 + P3 + P4 + P5 + P6) of the second summing cycle into the loop intermediate result memory access circuit 470. In the third summing cycle, feature point IN41, feature point IN42 and feature point IN43 are P7, P8 and P9 respectively, and the loop intermediate result access circuit 470 provides the sum value tmp44 (i.e., P1 + P2 + P3 + P4 + P5 + P6) of the second summing cycle to the multiplexer 440, and the floating point number normalization circuit 460 writes the sum value tmp45' (i.e., SUM41 = P7 + P8 + P9 + tmp44 = P1 + P2 + P3 + P4 + P5 + P6 + P7 + P8 + P9) of the third summing cycle into the register group 140 through the multiplexer 490. In the multiplication of the mean pooling operation, the first input terminal of the multiplier 480 receives the feature point sum value SUM41 (i.e., P1 + P2 + P3 + P4 + P5 + P6 + P7 + P8 + P9) from the pooling control circuit 130. A second input terminal of the multiplier 480 receives an average coefficient AC41 (e.g., 1 / 9) from the pooling control circuit 130 . The multiplier 480 writes the average pooling result (i.e., (P1 + P2 + P3 + P4 + P5 + P6 + P7 + P8 + P9) / 9) into the register group 140 via the multiplexer 490 .

[0039] In summary, in the mean pooling operation of the 3×3 receptive field, the conventional technology requires 9 instructions and 9 instruction cycles, while the above embodiment only requires 2 instructions, POOL.MEAN and FMUL, to complete the mean pooling operation, which takes a total of 4 instruction cycles. That is, the above embodiment can complete the mean pooling operation with fewer instructions and at a faster speed.

[0040] Figure 5 FIG. 5 is a circuit block diagram of a floating-point operation unit 500 according to another embodiment of the present invention. Figure 5 The floating point unit 500 shown can refer to Figure 1 or Figure 3 The relevant descriptions of any one of the floating-point operation units 150_1 to 150_N are given and can be deduced by analogy. Figure 5 The floating point unit 500 shown can be used as Figure 1 or Figure 3 One of many implementation examples of any one of the floating point operation units 150_1 to 150_N shown. Figure 5 In the illustrated embodiment, the floating point operation unit 500 includes a comparator 510, a comparator 520, a multiplexer 530, a multiplexer 540, a comparator 550, and a loop intermediate result storage access circuit 560. In this embodiment, the comparator 550 may be a component of a standard floating point operation unit, and the comparator 510, the comparator 520, the multiplexer 530, the multiplexer 540, and the loop intermediate result storage access circuit 560 are added to the standard floating point operation unit to be implemented as hardware specifically for maximum value pooling operation.

[0041] The instruction decoding module 120 decodes the pooling instruction POOL.MAX from the instruction scheduling module 110 to generate a decoding result. Based on the decoding result of the pooling instruction POOL.MAX, the pooling control circuit 130 determines the number of execution cycles of the pooling instruction and reads the feature points of the feature map values ​​from the register group 140 to the comparator 510 and the comparator 520. The comparator 510 is coupled to the pooling control circuit 130 to receive the first part of the multiple feature points of the corresponding receptive field, such as the feature point IN51 and the feature point IN52. The comparator 510 selects the maximum feature point tmp52 from the first part. The comparator 520 is coupled to the pooling control circuit 130 to receive the second part of the multiple feature points of the corresponding receptive field, such as the feature point IN53. The comparator 520 is also coupled to the output end of the loop intermediate result access circuit 560 to receive the maximum feature point tmp51 of the previous execution cycle in multiple cycles (execution cycles) of the maximum value pooling operation from the loop intermediate result access circuit 560. In the case of the first cycle of the maximum pooling operation performed by the floating point operation unit 500, the initial value of the maximum feature point tmp51 is negative infinity to ensure that the final result does not come from the initial value of the maximum feature point tmp51. The comparator 520 selects the maximum feature point tmp53 from the second part of the current execution cycle (e.g., feature point IN53) and the maximum feature point tmp51 of the previous execution cycle.

[0042] A first input terminal of the multiplexer 530 is coupled to an output terminal of the comparator 510 to receive the maximum feature point tmp52. An output terminal of the multiplexer 530 is coupled to a first input terminal of a comparator 550. A first input terminal of the multiplexer 540 is coupled to an output terminal of the comparator 520 to receive the maximum feature point tmp53. An output terminal of the multiplexer 540 is coupled to a second input terminal of the comparator 550. In the case where the floating point arithmetic unit 500 is used as hardware dedicated to the maximum value pooling operation, the multiplexer 530 transmits the maximum feature point tmp52 to the first input terminal of the comparator 550, and the multiplexer 540 transmits the maximum feature point tmp53 to the second input terminal of the comparator 550. In the case where the floating-point arithmetic unit 500 is used as a standard floating-point arithmetic unit, and in the case where this standard floating-point arithmetic unit performs a comparison operation, the second input end of the multiplexer 530 receives the floating-point number a, and the second input end of the multiplexer 540 receives the floating-point number b. At this time, the multiplexer 530 transmits the floating-point number a to the first input end of the comparator 550, and the multiplexer 540 transmits the floating-point number b to the second input end of the comparator 550. The comparator 550 selects the maximum feature point tmp54 from the maximum feature point tmp52 output by the multiplexer 530 and the maximum feature point tmp53 output by the multiplexer 540. The input end of the loop intermediate result access circuit 560 is coupled to the output end of the comparator 550 to receive the maximum feature point tmp54 of this execution cycle of the maximum value pooling operation.

[0043] For example, assuming that the size of the corresponding receptive field is 3×3 feature points, and assuming that the data elements in the corresponding receptive field are P1, P2, P3, P4, P5, P6, P7, P8 and P9, the maximum pooling operation (comparison iteration) of the corresponding receptive field includes 3 comparison cycles. In the first comparison cycle, the feature point IN51, the feature point IN52 and the feature point IN53 are P1, P2 and P3 respectively, and the loop intermediate result access circuit 560 provides the maximum feature point tmp51 with a value of negative infinity to the comparator 520, and the comparator 550 writes the maximum feature point tmp54 of the first comparison cycle (i.e., the maximum of P1, P2 and P3) into the loop intermediate result access circuit 560. In the second comparison cycle, the feature points IN51, IN52 and IN53 are P4, P5 and P6 respectively, and the loop intermediate result memory access circuit 560 provides the maximum feature point tmp51 of the first comparison cycle (i.e., the maximum of P1, P2 and P3) to the comparator 520, and the comparator 550 writes the maximum feature point tmp54 of the second comparison cycle (i.e., the maximum of P1, P2, P3, P4, P5 and P6) into the loop intermediate result memory access circuit 560. In the third comparison cycle, the feature points IN51, IN52 and IN53 are P7, P8 and P9 respectively, and the loop intermediate result access circuit 560 provides the maximum feature point tmp51 of the second comparison cycle (i.e., the largest of P1, P2, P3, P4, P5 and P6) to the comparator 520, and the comparator 550 writes the maximum feature point tmp54 of the third comparison cycle (i.e., the largest of P1, P2, P3, P4, P5, P6, P7, P8 and P9) into the register group 140.

[0044] In summary, in the maximum pooling operation of the 3×3 receptive field, the conventional technology requires 8 instructions and 8 instruction cycles, while the above embodiment only requires one instruction, POOL.MAX, to complete the maximum pooling operation, which takes a total of 3 instruction cycles. That is, the above embodiment can complete the maximum pooling operation with fewer instructions and at a faster speed.

[0045] Figure 6 FIG. 4 is a circuit block diagram of a floating-point operation unit 600 according to another embodiment of the present invention. Figure 6 The floating point unit 600 shown can refer to Figure 1 or Figure 3 The relevant descriptions of any one of the floating-point operation units 150_1 to 150_N are given and can be deduced by analogy. Figure 6 The floating point unit 600 shown may be used as Figure 1 or Figure 3 One of many implementation examples of any one of the floating point operation units 150_1 to 150_N shown. Figure 6 In the illustrated embodiment, the floating point operation unit 600 includes a mean pooling circuit 610 , a maximum pooling circuit 620 , a loop intermediate result memory access circuit 630 , and a multiplexer 640 .

[0046] The average pooling circuit 610 is coupled to the pooling control circuit 130 to receive a plurality of feature points of the corresponding receptive field, such as feature point IN61, feature point IN62, and feature point IN63. The average pooling circuit 610 selectively performs an average pooling operation on the plurality of feature points of the corresponding receptive field based on the control of the pooling control circuit 130. The average pooling operation of the average pooling circuit 610 can refer to Figure 4 The maximum pooling circuit 620 is coupled to the pooling control circuit 130 to receive a plurality of feature points of the corresponding receptive field. The maximum pooling circuit 620 selectively performs a maximum pooling operation on the plurality of feature points of the corresponding receptive field based on the control of the pooling control circuit 130. The maximum pooling operation of the maximum pooling circuit 620 can refer to Figure 5 The relevant descriptions about the maximum pooling operation in the illustrated embodiment are given and can be deduced by analogy.

[0047] The loop intermediate result memory access circuit 630 is coupled to the average pooling circuit 610 to receive the loop intermediate result tmp61 of the current execution cycle in multiple cycles (execution cycles) of the average pooling operation. The loop intermediate result memory access circuit 630 is coupled to the average pooling circuit 610 to provide the loop intermediate result tmp62 of the previous execution cycle in the average pooling operation. The loop intermediate result memory access circuit 630 is coupled to the maximum value pooling circuit 620 to receive the loop intermediate result tmp63 of the current execution cycle in multiple cycles (execution cycles) of the maximum value pooling operation. The loop intermediate result memory access circuit 630 is coupled to the maximum value pooling circuit 620 to provide the loop intermediate result tmp64 of the previous execution cycle of the maximum value pooling operation.

[0048] The first input terminal of the multiplexer 640 is coupled to the output terminal of the average pooling circuit 610. The second input terminal of the multiplexer 640 is coupled to the output terminal of the maximum pooling circuit 620. In response to the pooling operation of the pooling instruction being the average pooling operation, the maximum pooling circuit 620 is disabled, and the multiplexer 640 writes the average pooling result of the average pooling circuit 610 into the register group 140. In response to the pooling operation of the pooling instruction being the maximum pooling operation, the average pooling circuit 610 is disabled, and the multiplexer 640 writes the maximum pooling result of the maximum pooling circuit 620 into the register group 140.

[0049] Figure 7is a circuit block diagram of a mean pooling circuit 610 and a maximum pooling circuit 620 according to an embodiment of the present invention. Figure 7 The average pooling circuit 610, the maximum pooling circuit 620, the loop intermediate result access circuit 630 and the multiplexer 640 can refer to Figure 6 The relevant instructions are already given, so I will not repeat them here. Figure 7 The average pooling circuit 610 and the maximum pooling circuit 620 shown can be used as Figure 6 The mean pooling circuit 610 and the maximum pooling circuit 620 are shown as one of many implementation examples.

[0050] exist Figure 7 In the illustrated embodiment, the mean pooling circuit 610 includes a carry-save adder 611, an adder 612, a multiplexer 613, a multiplexer 614, an adder 615, a floating point number normalization circuit 616, a multiplier 617, and a multiplexer 618. The carry-save adder 611 is coupled to the pooling control circuit 130 to receive a plurality of feature points corresponding to the receptive field, such as feature point IN61, feature point IN62, and feature point IN63. The carry-save adder 611 generates a sum value tmp71 and a carry value tmp72 based on the feature point IN61, feature point IN62, and feature point IN63. The adder 612 is coupled to the carry-save adder 611 to receive the sum value tmp71 and the carry value tmp72. The adder 612 generates a sum value tmp73 based on the sum value tmp71 and the carry value tmp72. A first input terminal of the multiplexer 613 is coupled to the adder 612 to receive the sum tmp73. A first input terminal of the adder 615 is coupled to the output terminal of the multiplexer 613. A second input terminal of the adder 615 is coupled to the output terminal of the multiplexer 614. An input terminal of the floating point number normalization circuit 616 is coupled to the output terminal of the adder 615 to receive the sum tmp75. A first input terminal of the multiplier 617 receives the feature point sum SUM41 of the corresponding receptive field from the pooling control circuit 130. A second input terminal of the multiplier 617 receives the average coefficient AC41 of the corresponding receptive field from the pooling control circuit 130. A first input terminal of the multiplexer 618 is coupled to the output terminal of the floating point number normalization circuit 616. A second input terminal of the multiplexer 618 is coupled to the output terminal of the multiplier 617. An output terminal of the multiplexer 618 is coupled to a first input terminal of the multiplexer 640 .

[0051] The loop intermediate result memory access circuit 630 is coupled to the output terminal of the floating point number normalization circuit 616 to receive the loop intermediate result tmp61 of the current execution cycle in multiple cycles (execution cycles) of the average pooling operation. The loop intermediate result memory access circuit 630 is coupled to the first input terminal of the multiplexer 614 to provide the loop intermediate result tmp62 of the previous execution cycle of the average pooling operation. Figure 7 The carry-save adder 611, adder 612, multiplexer 613, multiplexer 614, adder 615, floating point number normalization circuit 616, multiplier 617, multiplexer 618 and loop intermediate result access circuit 630 shown in FIG. Figure 4 The related descriptions of the carry-save adder 410, adder 420, multiplexer 430, multiplexer 440, adder 450, floating-point number normalization circuit 460, multiplier 480, multiplexer 490 and loop intermediate result access circuit 470 are explained and deduced by analogy, so they are not repeated here.

[0052] exist Figure 7 In the illustrated embodiment, the maximum pooling circuit 620 includes a comparator 621, a comparator 622, a multiplexer 623, a multiplexer 624, and a comparator 625. The comparator 621 is coupled to the pooling control circuit 130 to receive a first portion of a plurality of feature points corresponding to the receptive field, such as feature point IN61 and feature point IN62. The comparator 621 selects the maximum feature point tmp76 from the first portion. The comparator 622 is coupled to the pooling control circuit 130 to receive a second portion of a plurality of feature points corresponding to the receptive field, such as feature point IN63. The comparator 622 is also coupled to the loop intermediate result access circuit 630 to receive the maximum feature point (loop intermediate result tmp64) of the previous execution cycle in multiple loops (execution cycles) of the maximum pooling operation. In the case of the first loop of the floating point arithmetic unit 600 performing the maximum pooling operation, the loop intermediate result tmp64 is zero. The comparator 622 selects the maximum feature point tmp77 from the second part of the current execution cycle (eg, the feature point IN63 ) and the maximum feature point of the previous execution cycle (the loop intermediate result tmp64 ).

[0053] The first input terminal of the multiplexer 623 is coupled to the output terminal of the comparator 621 to receive the maximum feature point tmp76. The first input terminal of the multiplexer 624 is coupled to the output terminal of the comparator 622 to receive the maximum feature point tmp77. The first input terminal of the comparator 625 is coupled to the output terminal of the multiplexer 623. The second input terminal of the comparator 625 is coupled to the output terminal of the multiplexer 624. The comparator 625 selects the maximum feature point (loop intermediate result tmp63) from the output of the multiplexer 623 and the output of the multiplexer 624. The loop intermediate result access circuit 630 is coupled to the output terminal of the comparator 625 to receive the loop intermediate result tmp63 of the current execution cycle in multiple cycles (execution cycles) of the maximum value pooling operation. The loop intermediate result access circuit 630 is coupled to the comparator 622 to provide the loop intermediate result tmp64 of the previous execution cycle of the maximum value pooling operation. The comparator 622 selects the maximum feature point tmp77 from the second part (eg, feature point IN63 ) of the current execution cycle and the loop intermediate result tmp64 of the previous execution cycle of the maximum pooling operation. Figure 7 The comparator 621, the comparator 622, the multiplexer 623, the multiplexer 624, the comparator 625 and the loop intermediate result access circuit 630 can refer to Figure 5 The related descriptions of the comparator 510 , the comparator 520 , the multiplexer 530 , the multiplexer 540 , the comparator 550 and the loop intermediate result access circuit 560 are explained by analogy and will not be repeated here.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An artificial intelligence chip, characterized in that: The artificial intelligence chip includes: Instruction scheduling module; an instruction decoding module, coupled to the instruction scheduling module to receive the pooling instruction, wherein the instruction decoding module decodes the pooling instruction to generate a decoding result; Register group; A pooling control circuit coupled to the instruction decoding module and the register set; and A first floating point operation unit is coupled to the pooling control circuit, wherein: The pooling control circuit determines the number of execution cycles of the pooling instruction based on the decoding result, and provides the number of execution cycles to the first floating-point operation unit; The pooling control circuit reads a feature map value from the register group based on the decoding result, and provides a plurality of feature points of a first receptive field of the feature map value to the first floating-point operation unit; and The first floating-point operation unit performs a pooling operation on multiple feature points of the first receptive field based on the number of execution cycles to generate a pooling result of the first receptive field.

2. The artificial intelligence chip according to claim 1, characterized in that: The artificial intelligence chip also includes: A second floating point operation unit is coupled to the pooling control circuit, wherein: The pooling control circuit provides the execution cycle number to the second floating point operation unit; The pooling control circuit provides a plurality of feature points of a second receptive field of the feature map value to the second floating-point operation unit based on the decoding result; and The second floating-point operation unit performs a pooling operation on the plurality of feature points of the second receptive field based on the number of execution cycles to generate a pooling result of the second receptive field.

3. The artificial intelligence chip according to claim 1, characterized in that: The pooling control circuit comprises: a pooling operation control module, coupled to the instruction decoding module to receive the decoding result, wherein the pooling operation control module determines the execution cycle number of the pooling instruction based on the decoding result, and provides the execution cycle number to the first floating point operation unit; an operand acquisition module, coupled to the pooling operation control module and the register group, wherein the operand acquisition module reads the feature map value from the register group based on the control of the pooling operation control module; and A feature map input control module is coupled to the operand acquisition module to receive the feature map value, wherein the feature map input control module provides multiple feature points of the first receptive field of the feature map value to the first floating point operation unit.

4. The artificial intelligence chip according to claim 1, characterized in that: The first floating-point operation unit comprises: a carry-save adder coupled to the pooling control circuit to receive a plurality of feature points of the first receptive field, wherein the carry-save adder generates a first sum value and a carry value based on the plurality of feature points of the first receptive field; a first adder coupled to the carry-save adder to receive the first sum value and the carry value, wherein the first adder generates a second sum value based on the first sum value and the carry value; a first multiplexer, wherein a first input terminal of the first multiplexer is coupled to the first adder to receive the second sum value; a second multiplexer; a second adder, wherein a first input terminal of the second adder is coupled to the output terminal of the first multiplexer, and a second input terminal of the second adder is coupled to the output terminal of the second multiplexer; a floating point number normalization circuit, wherein an input terminal of the floating point number normalization circuit is coupled to an output terminal of the second adder; A loop intermediate result memory access circuit, wherein an input end of the loop intermediate result memory access circuit is coupled to an output end of the floating point number normalization circuit, and an output end of the loop intermediate result memory access circuit is coupled to a first input end of the second multiplexer; a multiplier, wherein a first input terminal of the multiplier receives a sum of feature points of the first receptive field from the pooling control circuit, and a second input terminal of the multiplier receives an average coefficient of the first receptive field from the pooling control circuit; and A third multiplexer, wherein a first input terminal of the third multiplexer is coupled to the output terminal of the floating point number normalization circuit, and a second input terminal of the third multiplexer is coupled to the output terminal of the multiplier.

5. The artificial intelligence chip according to claim 1, characterized in that: The first floating-point operation unit comprises: a first comparator, coupled to the pooling control circuit to receive a first portion of the plurality of feature points of the first receptive field, wherein the first comparator selects a first maximum feature point from the first portion; a second comparator, coupled to the pooling control circuit to receive a second portion of the plurality of feature points of the first receptive field, wherein the second comparator outputs a second maximum feature point; a first multiplexer, wherein a first input terminal of the first multiplexer is coupled to an output terminal of the first comparator to receive the first maximum characteristic point; a second multiplexer, wherein a first input terminal of the second multiplexer is coupled to an output terminal of the second comparator; a third comparator, wherein a first input terminal of the third comparator is coupled to the output terminal of the first multiplexer, a second input terminal of the third comparator is coupled to the output terminal of the second multiplexer, and the third comparator selects a third maximum feature point from the output of the first multiplexer and the output of the second multiplexer; and A loop intermediate result access circuit, wherein an input end of the loop intermediate result access circuit is coupled to an output end of the third comparator, and an output end of the loop intermediate result access circuit is coupled to the second comparator to provide the third maximum characteristic point of the previous execution cycle; The second comparator selects the second maximum feature point from the second part of the current execution cycle and the third maximum feature point of the previous execution cycle.

6. The artificial intelligence chip according to claim 1, characterized in that: The first floating-point operation unit comprises: A mean pooling circuit coupled to the pooling control circuit to receive a plurality of feature points of the first receptive field, wherein the mean pooling circuit selectively performs a mean pooling operation on the plurality of feature points of the first receptive field based on control of the pooling control circuit; a maximum pooling circuit, coupled to the pooling control circuit to receive a plurality of feature points of the first receptive field, wherein the maximum pooling circuit selectively performs a maximum pooling operation on the plurality of feature points of the first receptive field based on control of the pooling control circuit; A loop intermediate result memory access circuit, wherein the loop intermediate result memory access circuit is coupled to the mean pooling circuit to receive the loop intermediate result of the mean pooling operation of this execution cycle, the loop intermediate result memory access circuit is coupled to the mean pooling circuit to provide the loop intermediate result of the mean pooling operation of the previous execution cycle, the loop intermediate result memory access circuit is coupled to the maximum value pooling circuit to receive the loop intermediate result of the maximum value pooling operation of this execution cycle, and the loop intermediate result memory access circuit is coupled to the maximum value pooling circuit to provide the loop intermediate result of the maximum value pooling operation of the previous execution cycle; and A first multiplexer, wherein a first input terminal of the first multiplexer is coupled to an output terminal of the average pooling circuit, and a second input terminal of the first multiplexer is coupled to an output terminal of the maximum pooling circuit.

7. The artificial intelligence chip according to claim 6, characterized in that: The average pooling circuit comprises: a carry-save adder coupled to the pooling control circuit to receive a plurality of feature points of the first receptive field, wherein the carry-save adder generates a first sum value and a carry value based on the plurality of feature points of the first receptive field; a first adder coupled to the carry-save adder to receive the first sum value and the carry value, wherein the first adder generates a second sum value based on the first sum value and the carry value; a second multiplexer, wherein a first input terminal of the second multiplexer is coupled to the first adder to receive the second sum value; a third multiplexer; a second adder, wherein a first input terminal of the second adder is coupled to an output terminal of the second multiplexer, and a second input terminal of the second adder is coupled to an output terminal of the third multiplexer; a floating point number normalization circuit, wherein an input terminal of the floating point number normalization circuit is coupled to an output terminal of the second adder; a multiplier, wherein a first input terminal of the multiplier receives a sum of feature points of the first receptive field from the pooling control circuit, and a second input terminal of the multiplier receives an average coefficient of the first receptive field from the pooling control circuit; and a fourth multiplexer, wherein a first input terminal of the fourth multiplexer is coupled to an output terminal of the floating point number normalization circuit, a second input terminal of the fourth multiplexer is coupled to an output terminal of the multiplier, and an output terminal of the fourth multiplexer is coupled to a first input terminal of the first multiplexer; The loop intermediate result memory access circuit is coupled to the output end of the floating-point number normalization circuit to receive the loop intermediate result of the mean pooling operation of the current execution cycle, and the loop intermediate result memory access circuit is coupled to the first input end of the third multiplexer to provide the loop intermediate result of the mean pooling operation of the previous execution cycle.

8. The artificial intelligence chip according to claim 6, characterized in that: The maximum pooling circuit comprises: a first comparator, coupled to the pooling control circuit to receive a first portion of the plurality of feature points of the first receptive field, wherein the first comparator selects a first maximum feature point from the first portion; a second comparator, coupled to the pooling control circuit to receive a second portion of the plurality of feature points of the first receptive field, wherein the second comparator outputs a second maximum feature point; a second multiplexer, wherein a first input terminal of the second multiplexer is coupled to an output terminal of the first comparator to receive the first maximum characteristic point; a third multiplexer, wherein a first input terminal of the third multiplexer is coupled to an output terminal of the second comparator; and a third comparator, wherein a first input terminal of the third comparator is coupled to the output terminal of the second multiplexer, a second input terminal of the third comparator is coupled to the output terminal of the third multiplexer, and the third comparator selects a third maximum characteristic point from the output of the second multiplexer and the output of the third multiplexer; wherein the loop intermediate result access circuit is coupled to the output terminal of the third comparator to receive the loop intermediate result of the maximum value pooling operation of the current execution cycle, and the loop intermediate result access circuit is coupled to the second comparator to provide the loop intermediate result of the maximum value pooling operation of the previous execution cycle; The second comparator selects the second maximum feature point from the second part of the current execution cycle and the loop intermediate result of the maximum pooling operation of the previous execution cycle.

9. A pooling method for an artificial intelligence chip, characterized in that: The pooling method comprises: The instruction decoding module of the artificial intelligence chip decodes the pooling instruction to generate a decoding result, wherein the instruction decoding module is coupled to the instruction scheduling module of the artificial intelligence chip to receive the pooling instruction; The pooling control circuit of the artificial intelligence chip determines the number of execution cycles of the pooling instruction based on the decoding result, wherein the pooling control circuit is coupled to the instruction decoding module, the register group of the artificial intelligence chip, and the first floating-point operation unit of the artificial intelligence chip; The pooling control circuit provides the execution cycle number to the first floating point operation unit; The pooling control circuit reads a characteristic map value from the register group based on the decoding result; The pooling control circuit provides a plurality of feature points of the first receptive field of the feature map value to the first floating point operation unit; and The first floating-point operation unit performs a pooling operation on the plurality of feature points of the first receptive field based on the number of execution cycles to generate a pooling result of the first receptive field.

10. The pooling method according to claim 9, characterized in that: The pooling method further comprises: The pooling control circuit provides the execution cycle number to a second floating-point operation unit of the artificial intelligence chip, wherein the second floating-point operation unit is coupled to the pooling control circuit; The pooling control circuit provides a plurality of feature points of a second receptive field of the feature map value to the second floating-point operation unit based on the decoding result; and The second floating-point operation unit performs a pooling operation on the plurality of feature points of the second receptive field based on the number of execution cycles to generate a pooling result of the second receptive field.

11. The pooling method according to claim 9, characterized in that: The pooling method further comprises: determining, by a pooling operation control module of the pooling control circuit, the number of execution cycles of the pooling instruction based on the decoding result, wherein the pooling operation control module is coupled to the instruction decoding module to receive the decoding result; The pooling operation control module provides the execution cycle number to the first floating point operation unit; The operand acquisition module of the pooling control circuit reads the characteristic map value from the register group based on the control of the pooling operation control module, wherein the operand acquisition module is coupled to the pooling operation control module and the register group; and The feature map input control module of the pooling control circuit provides multiple feature points of the first receptive field of the feature map value to the first floating-point operation unit, wherein the feature map input control module is coupled to the operand acquisition module to receive the feature map value.

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