An acceleration device and method for calculating a Gamma correction algorithm

Abstract

An acceleration device and method for calculating a gamma correction algorithm can significantly improve the execution speed of the gamma correction algorithm, effectively resolving bottlenecks in processing efficiency in traditional general-purpose processors. The device comprises a value acquisition unit, a decoding unit, an execution unit, a memory access unit, and a write-back unit. The value acquisition unit includes an instruction memory, a program counter, an instruction prefetch unit, a branch prediction unit, and a pre-decoding unit. The execution unit includes a branch instruction module, an ALU module, a MUL module, a DIV module, an FPU module, and a gamma unit that shares some logical resources with the ALU and FPU modules. The memory access unit includes a data memory. The write-back unit includes an integer register file (GPR) and a floating-point register file (FPR).

Description

Technical Field

[0001] The present invention relates to the technical field of computer image preprocessing, and in particular to an acceleration device for calculating a Gamma correction algorithm, and an acceleration method for calculating a Gamma correction algorithm. Background Art

[0002] Gamma correction, as an important image preprocessing technique, plays a crucial role in improving image display quality. Due to the nonlinear electro-optical conversion characteristics of display devices in the image acquisition, processing, and display chain, without gamma correction, image brightness and color reproduction will be severely distorted, failing to meet the requirements of a high-quality visual experience. Traditional gamma correction algorithms, when implemented on general-purpose processors, often suffer from low processing efficiency due to their high algorithmic complexity, making them difficult to meet the demands of speed-critical applications such as high-definition video processing and real-time image rendering.

[0003] As an emerging open-source instruction set architecture, the RISC-V architecture boasts significant advantages such as simplicity, strong customizability, and modular design. It has emerged as a leader in a wide range of fields, including embedded systems, the Internet of Things, and high-performance computing. Exploiting the advantages of the RISC-V architecture to deeply optimize and accelerate gamma correction algorithms is a pressing challenge in image preprocessing technology. Summary of the Invention

[0004] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide an acceleration device for calculating the Gamma correction algorithm, which can significantly improve the execution speed of the Gamma correction algorithm and effectively solve the bottleneck problem of traditional general-purpose processors in processing efficiency.

[0005] The technical solution of the present invention is: this acceleration device for calculating the gamma correction algorithm includes: a value acquisition unit, a decoding unit, an execution unit, a memory access unit and a write-back unit; the value acquisition unit includes an instruction memory, a program counter, an instruction pre-fetch unit, a branch prediction unit and a pre-decoding unit; the execution unit includes a branch instruction module, an ALU module, a MUL module, a DIV module, an FPU module, and a GAMMA unit that shares some logic resources with the ALU module and the FPU module; the memory access unit includes a data memory; the write-back unit includes an integer register file (GPR) and a floating-point register file (FPR);

[0006] The opcode field of the GAMMA unit in the pre-decoding unit is constructed using a custom encoding format, using 7'b0001011 as the opcode. The circuit of the opcode recognition part includes a three-input NAND gate, two three-input AND gates, and a NOT gate.

[0007] The instruction memory stores the machine code converted by the RISC-V program through the assembler and compiler; the program counter stores and updates the current instruction address; the branch prediction unit predicts the direction and target address of the branch instruction; the instruction prefetch unit judges and decodes the compressed instruction set, translating the 16-bit compressed instructions into 32-bit basic instructions; the data memory stores data during program execution and is accessed by load / store instructions; the register stack is located inside the processor and stores operands and intermediate results.

[0008] The beneficial technical effects of the present invention are as follows:

[0009] (1) By utilizing the flexibility and customizability of the RISC-V instruction set and designing a specialized custom instruction set, the number of instructions required for image preprocessing tasks is reduced, and the hardware acceleration features of RISC-V are fully utilized to meet the needs of image processing applications with high real-time requirements.

[0010] (2) A customized instruction set optimized for the gamma correction algorithm is used, sharing some resources with the existing integer and floating-point instruction sets, reducing the large amount of general-purpose computing resources required when running on general-purpose processors. Furthermore, the implementation of the customized instruction set is more efficient in resource utilization than a pure hardware implementation, reducing the hardware resource requirements of the entire system.

[0011] (3) Through a detailed analysis of the Gamma algorithm, an optimal circuit structure that conforms to the algorithm was developed, and instruction design was carried out rationally, which reduced additional resource consumption and lowered the burden of value retrieval and decoding after adding custom instructions.

[0012] A method for accelerating the calculation of a gamma correction algorithm is also provided, comprising the following steps:

[0013] (1) The instruction memory stores the machine code converted by the RISC-V program through the assembler and compiler. The program counter stores and updates the current instruction address. The branch prediction unit predicts the direction and target address of the branch instruction. The instruction prefetch unit judges and decodes the compressed instruction and translates the 16-bit compressed instruction into a 32-bit basic instruction. The data memory stores the data during program execution and is accessed by load / store instructions. The register stack is located inside the processor and stores operands and intermediate results.

[0014] (2) The instruction is loaded into the instruction memory. The value fetching unit fetches the required instruction from the instruction memory according to the program counter and determines whether it is a compressed instruction. If it is a compressed instruction, it enters the instruction prefetching unit and translates the 16-bit compressed instruction into a 32-bit instruction. At the same time, the value fetching unit is paused to determine whether the next 16-bit instruction is a compressed instruction. If not, it is spliced ​​with the lower 16 bits of the 32-bit instruction. If it is, it enters the compressed instruction translation process again.

[0015] (3) The translated 32-bit instruction or the normal 32-bit instruction is first transmitted to the instruction pre-decoding unit, which inputs the 32-bit instruction and outputs the source operand and destination operand registers of the instruction and the control signal for loading non-operation type instructions;

[0016] (4) The 32-bit instruction and pre-decoding unit are sent to the decoding unit. The decoding unit decodes the opcode, funct3, and funct7 in detail to obtain the detailed operation code of the large category of instructions, obtain all the detailed information of a single instruction, and obtain the control signal. The control signal and source operand are then transmitted to the execution unit. The execution unit determines which operation unit the instruction flows to based on the control signal, enters the operation unit to obtain the result, and sends it to the memory access stage.

[0017] (5) If it is a load-store instruction, it enters the load-store unit and interacts with the data memory; if it is an instruction other than load-store, it directly enters the write-back unit and interacts with the integer register file or floating-point register file. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 2 is a schematic structural diagram of an acceleration device for calculating a Gamma correction algorithm according to the present invention.

[0019] Figure 2 A flowchart of a processor front end including a compression-to-zero set decoding unit is shown.

[0020] Figure 3 It is a schematic diagram of the specific structure from the pre-decoding module to the decoding unit.

[0021] Figure 4 Schematic diagram of the GAMMA recognition circuit in the pre-decoding unit.

[0022] Figure 5 Schematic diagram of the funct7 decoding circuit in the decoding unit.

[0023] Figure 6 Schematic diagram of the GAMMA unit in the execution unit.

[0024] Figure 7 Schematic diagram of the structure of the data normalization unit.

[0025] Figure 8 Schematic diagram of the structure of the power function operation unit.

[0026] Figure 9 Schematic diagram of the structure of the data denormalization unit. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0028] To provide a more complete and detailed description of this disclosure, the following illustrative descriptions of embodiments and examples of the present invention are provided; however, these descriptions are not intended to be the only ways to implement or use the embodiments of the present invention. The embodiments cover features of various embodiments, as well as the method steps and sequences for constructing and operating these embodiments. However, other embodiments may be used to achieve the same or equivalent functionality and sequence of steps.

[0029] like Figure 1 As shown, this acceleration device for calculating the gamma correction algorithm includes: a value acquisition unit, a decoding unit, an execution unit, a memory access unit and a write-back unit; the value acquisition unit includes an instruction memory, a program counter, an instruction prefetch unit, a branch prediction unit and a pre-decoding unit; the execution unit includes a branch instruction module, an ALU (Arithmetic Logic Unit) module, a MUL (Multiple) module, a DIV (Division) module, an FPU (Floating-Point Unit) module, and a GAMMA unit that shares some logic resources with the ALU module and the FPU module; the memory access unit includes a data memory; the write-back unit includes an integer register file GPR (General Purpose Register, general / integer register file) and a floating-point register file FPR (Floating-Point Register);

[0030] The opcode field of the GAMMA unit in the pre-decoding unit is constructed using a custom encoding format, using 7'b0001011 as the opcode. The circuit of the opcode recognition part includes a three-input NAND gate, two three-input AND gates, and a NOT gate.

[0031] The instruction memory stores the machine code converted by the RISC-V program through the assembler and compiler; the program counter stores and updates the current instruction address; the branch prediction unit predicts the direction and target address of the branch instruction; the instruction prefetch unit judges and decodes the compressed instruction set, translating the 16-bit compressed instructions into 32-bit basic instructions; the data memory stores data during program execution and is accessed by load / store instructions; the register stack is located inside the processor and stores operands and intermediate results.

[0032] The beneficial technical effects of the present invention are as follows:

[0033] (1) By utilizing the flexibility and customizability of the RISC-V instruction set and designing a specialized custom instruction set, the number of instructions required for image preprocessing tasks is reduced, and the hardware acceleration features of RISC-V are fully utilized to meet the needs of image processing applications with high real-time requirements.

[0034] (2) A customized instruction set optimized for the gamma correction algorithm is used, sharing some resources with the existing integer and floating-point instruction sets, reducing the large amount of general-purpose computing resources required when running on general-purpose processors. Furthermore, the implementation of the customized instruction set is more efficient in resource utilization than a pure hardware implementation, reducing the hardware resource requirements of the entire system.

[0035] (3) Through a detailed analysis of the Gamma algorithm, an optimal circuit structure that conforms to the algorithm was developed, and instruction design was carried out rationally, which reduced additional resource consumption and lowered the burden of value retrieval and decoding after adding custom instructions.

[0036] Preferably, the Gamma correction formula in the GAMMA unit is:

[0037] ,

[0038] In the actual operation process, the specific steps are:

[0039] ,

[0040] ,

[0041] ,

[0042] ,

[0043] in:

[0044] is the input pixel value, the value range is 0≤ ≤255;

[0045] γ is the γ correction value, and its value range is 0<γ<2.5;

[0046] is the output pixel value, the value range is 0≤ ≤255;

[0047] is the normalized pixel value, ranging from 0≤ ≤1;

[0048] The value range is -∞< ≤0;

[0049] The value range is -∞< ≤0;

[0050] The value range is 0< ≤1.

[0051] Preferably, the instruction set of the GAMMA unit is defined as R-type instructions in the floating-point type, with a total of 5 instructions;

[0052] opcode uses custom-0 unit, and identifies the custom instruction in the GAMMA unit according to the opcode code; funct7 is used to distinguish the specific instructions in the GAMMA unit; funct3 is all set to 000; rs2 is all set to 00000; funct7 is encoded using a one-hot code;

[0053] The funct7 decoding circuit in the decoding unit decodes the required instructions through a one-to-one correspondence based on the encoding format of the one-hot code.

[0054] Preferably, the instruction set of the GAMMA unit is defined as CA-type instructions in the compressed instruction type, with a total of 5 items;

[0055] A compressed instruction set using a custom gamma correction algorithm is used in the value-taking unit. The length of the instructions in the compressed instruction set is 16 bits. The compressed instruction format of the custom gamma correction algorithm is distinguished from existing instructions by adjusting the encoding of op and funct2. The funct6 field of the compressed instruction set is encoded using a sequential shift sequence and a one-hot code, and each instruction only verifies and detects one bit of data.

[0056] Preferably, the GAMMA unit performs Gamma correction processing on the input image, and includes a data normalization unit, a lookup table unit, a power operation unit, and a data denormalization unit.

[0057] Preferably, the data normalization unit comprises a serial floating-point adder and a floating-point shifter, which maps the input pixel value in the integer range of 0-255 to a real number range of 0-1.

[0058] Preferably, the lookup table unit stores γ correction values ​​corresponding to different grayscale value regions, and outputs corresponding γ correction values ​​according to the input pixel value I.

[0059] Preferably, the power operation unit includes a floating-point reciprocal operator, a logarithm operator, a floating-point multiplier and an exponential operator, and pre-compensates the normalized pixel value to convert the data from the linear space to a nonlinear space suitable for the display device.

[0060] Preferably, the data denormalization unit includes a serial floating-point shifter and a floating-point subtractor, which maps the result of the power function operation after the gamma correction back to an integer range between 0 and 255.

[0061] A method for accelerating the calculation of a gamma correction algorithm is also provided, comprising the following steps:

[0062] (1) The instruction memory stores the machine code converted by the RISC-V program through the assembler and compiler. The program counter stores and updates the current instruction address. The branch prediction unit predicts the direction and target address of the branch instruction. The instruction prefetch unit judges and decodes the compressed instruction and translates the 16-bit compressed instruction into a 32-bit basic instruction. The data memory stores the data during program execution and is accessed by load / store instructions. The register stack is located inside the processor and stores operands and intermediate results.

[0063] (2) The instruction is loaded into the instruction memory. The value fetching unit fetches the required instruction from the instruction memory according to the program counter and determines whether it is a compressed instruction. If it is a compressed instruction, it enters the instruction prefetching unit and translates the 16-bit compressed instruction into a 32-bit instruction. At the same time, the value fetching unit is paused to determine whether the next 16-bit instruction is a compressed instruction. If not, it is spliced ​​with the lower 16 bits of the 32-bit instruction. If it is, it enters the compressed instruction translation process again.

[0064] (3) The translated 32-bit instruction or the normal 32-bit instruction is first transmitted to the instruction pre-decoding unit, which inputs the 32-bit instruction and outputs the source operand and destination operand registers of the instruction and the control signal for loading non-operation type instructions;

[0065] (4) The 32-bit instruction and pre-decoding unit are sent to the decoding unit. The decoding unit decodes the opcode, funct3, and funct7 in detail to obtain the detailed operation code of the large category of instructions, obtain all the detailed information of a single instruction, and obtain the control signal. The control signal and source operand are then transmitted to the execution unit. The execution unit determines which operation unit the instruction flows to based on the control signal, enters the operation unit to obtain the result, and sends it to the memory access stage.

[0066] (5) If it is a load-store instruction, it enters the load-store unit and interacts with the data memory; if it is an instruction other than load-store, it directly enters the write-back unit and interacts with the integer register file or floating-point register file.

[0067] The specific embodiments of the present invention are described in more detail below.

[0068] like Figure 1 Figure 2 shows the overall circuit structure of the GAMMA correction algorithm accelerator. Based on the RISC-V processor architecture, it includes a value acquisition unit, a decoding unit, an execution unit, a memory access unit, and a write-back unit. The value acquisition unit includes the instruction memory, program counter, instruction prefetch unit, branch prediction unit, and pre-decoding unit. The memory access unit includes the branch instruction module, ALU, MUL, DIV, and FPU modules, as well as the GAMMA unit, which shares some logical resources with the ALU and FPU. The memory access unit includes data memory, and the write-back unit includes the integer register file and floating-point register file.

[0069] The instruction memory is responsible for storing the machine code converted by the RISC-V program through the assembler and compiler; the program counter is responsible for storing and updating the current instruction address to ensure that instructions are executed in sequence or jump; the branch prediction unit predicts the direction and target address of branch instructions, reducing pipeline pauses and improving processor performance; the instruction prefetch unit is responsible for judging and decoding compressed instructions, translating 16-bit compressed instructions into 32-bit basic instructions; the data memory is used to store data during program execution and is accessed by load / store instructions; the register stack is located inside the processor and is used to store operands and intermediate results.

[0070] The instruction is loaded into the instruction memory, and the value fetching unit fetches the required instruction from the instruction memory according to the program counter and determines whether it is a compressed instruction. If it is a compressed instruction, it enters the instruction prefetching unit and translates the 16-bit compressed instruction into a 32-bit instruction. At the same time, the value fetching unit is paused to determine whether the next 16-bit instruction is a compressed instruction. If not, it is spliced ​​with the lower 16 bits of the 32-bit instruction. If it is, it enters the translation process of the compressed instruction again; the translated 32-bit instruction or the normal 32-bit instruction is first transmitted to the instruction pre-decoding unit, which inputs the 32-bit instruction and outputs the source operand and destination operand registers of the instruction as well as the control signals of non-operation type instructions such as load and store instructions. number, thereby reducing the pressure on the decoding stage; the 32-bit instruction and the pre-decoding unit are transmitted to the decoding unit, and the decoding unit decodes the opcode, funct3 and funct7 in detail to obtain the detailed operation code of the large category of instructions, obtain all the detailed information of a single instruction, and obtain the control signal; the control signal and the source operand are then transmitted to the execution unit, and the execution unit determines which operation unit the instruction flows to according to the control signal, enters the operation unit to obtain the result, and transmits it to the memory access stage; if it is a load-store instruction, it enters the load-store unit and interacts with the data memory; if it is an instruction other than load-store, it directly enters the write-back unit to interact with the integer register file or the floating-point register file.

[0071] The gamma correction formula is:

[0072] ,

[0073] in:

[0074] : Input pixel value, the value range is 0≤ ≤255;

[0075] γ: γ correction value, the value range is 0<γ<2.5;

[0076] : Output pixel value, the value range is 0≤ ≤255.

[0077] Gamma correction specific steps:

[0078] Normalization: ,

[0079] Exponentiation: ,

[0080] Denormalization: ,

[0081] in:

[0082] The exponentiation module is converted to: ,

[0083] : is the normalized pixel value, the value range is 0≤ ≤1;

[0084] :The value range is -∞< ≤0;

[0085] :The value range is -∞< ≤0;

[0086] : The value range is 0< ≤1.

[0087] Based on the analysis and decomposition of the algorithm, these instructions belong to the floating-point arithmetic class and involve reciprocal, logarithmic, and exponential operations. Therefore, a total of five custom instructions are defined, encoded using the floating-point R-type instruction encoding format. The custom encoding consists of opcode, funct7, and funct3. The opcode uses the custom-0 unit to distinguish it from existing instructions. Custom instructions in the GAMMA unit can be directly identified based on the opcode encoding. funct7 is used to distinguish specific instructions in the GAMMA unit and is written using a one-hot code. This code utilizes the characteristic of a one-hot code that only contains one valid value at a time, reducing the decoding burden. All funct3 bits are set to 000. Since each instruction has a single operand, rs2 bits are also set to 00000. Table 1 shows the specific encoding format.

[0088] Table 1

[0089]

[0090] The processor features a configurable compressed instruction set module, implemented in the value-access unit. The compressed instruction set is 16 bits long, significantly reducing instruction memory resource consumption compared to standard 32-bit instructions, thereby alleviating the burden on the value-access unit. These 16-bit compressed instructions utilize the CA format of the RISC-V compressed instruction set, consisting of funct6 (6 bits), rd / rs1 (3 bits), funct2 (2 bits), rs2 (3 bits), and op (2 bits). Table 2 shows the specific 16-bit encoding format.

[0091] Table 2

[0092]

[0093] The fnorm instruction performs normalization on the input pixels, performing floating-point addition followed by shifting; the frenorm instruction performs inverse normalization, performing floating-point shift followed by subtraction; the frec instruction performs floating-point reciprocal; the fln instruction performs floating-point logarithm; and the fexp instruction performs floating-point exponentiation.

[0094] Using shift registers in the normalization and denormalization units to multiply or divide by 256 allows the exponent to be directly added or subtracted by 8. However, if the number of exponent bits is insufficient, overflow or underflow may occur. In this case, adjustment for floating-point overflow is required. This can be avoided by checking the range of the input values.

[0095] like Figure 2 As shown, the flowchart of the decoding unit of the processor front end includes a compressed instruction set:

[0096] The 16-bit compressed instruction first passes through the instruction prefetch unit, where it is decoded according to the compressed instruction set specification in the RISC-V official manual. By identifying op, funct6, and funct2, a 32-bit custom Gamma instruction is generated. For example, when op and funct2 are 2'b01 and 2'b10, respectively, the current instruction is an instruction in the Gamma unit. At this time, the 16-bit data is expanded to 32 bits: funct6 is mapped to funct7, op (2'b01) is replaced with opcode (7'b0001011), and funct2 (2'b10) is replaced with funct3 (3'b000). Other source and destination operands are mapped to the 5-bit rd or rs1 / rs2, and the high-order bits are padded with 0s.

[0097] like Figure 3 As shown in FIG, it is a schematic diagram of the specific structure from the pre-decoding module to the decoding unit:

[0098] During the instruction fetch phase, the pre-decode module, leveraging the opcode characteristics of the custom instruction set, can directly identify instructions belonging to the Gamma unit, generating a Gamma-en enable signal and simultaneously decoding the source register (Rs), destination register number (Rd), load / store instruction (Load / Store) signals, and register enable signals. These signals pass through the decode phase. In the decode module, 32-bit instructions are identified as five instructions in the Gamma unit using funct7. Other RISC-V standard instruction sets are identified using funct7 and funct3, generating the ALU-Ctrl, Ld-Ctrl, St-Ctrl, Bru-Ctrl, Gamma-Ctrl, and Imm signals. Instructions ending with Ctrl are control signals, and Imm is an immediate value.

[0099] like Figure 4 As shown, the GAMMA unit opcode recognition circuit in the pre-decoding unit:

[0100] The gamma recognition circuit consists of a three-input NAND gate (numbered 1), two three-input AND gates (numbered 2 and 3), and a NOT gate. opcode[6:4] is input to device 1, resulting in out1. opcode[1:0] and opcode[3] are input to device 2, resulting in out2. opcode[2] is input to the NOT gate, resulting in out3. Out1, out2, and out3 are input to device 3, resulting in the Gamma-en enable signal. If this signal is 1, the instruction is a custom instruction in the Gamma unit. If it is 0, the signal is not a custom instruction in the Gamma unit.

[0101] like Figure 5 As shown, the funct7 decoding circuit in the decoding unit:

[0102] When the result of the opcode recognition circuit in the pre-decoding stage is 1, the decoding stage begins to decode funct7 and recognize the specific custom instruction. funct7 takes bits [31:25] of the 32-bit instruction. The funct7 of the five instructions of the GAMMA unit is designed as a one-hot code format so that each encoding has only one valid value. Figure 3 , funct7 is 7'b0000001 corresponding to the fnorm instruction, funct7 is 7'b0000010 corresponding to the frenorm instruction, funct7 is 7'b0000100 corresponding to the frec instruction, funct7 is 7'b0001000 corresponding to the fln instruction, and funct7 is 7'b0010000 corresponding to the fexp instruction. Through this one-to-one correspondence, the required instructions are decoded.

[0103] like Figure 6 As shown in the figure, when the control unit's signal enters the GAMMA unit in the execution unit, gamma correction first requires data normalization of the input pixel values. It then outputs the corresponding gamma correction value based on the input pixel values. It then performs a power operation, pre-compensation of the normalized data, and finally denormalization. The entire GAMMA unit consists of a data normalization unit, a search unit, a power operation unit, and a data normalization unit.

[0104] According to the formula for data normalization, such as Figure 7As shown, it contains a floating-point adder and a floating-point shifter, which are executed serially. It is used to map the pixel values ​​in the input integer range of 0-255 to the real number range of 0-1, ensuring that the pixel values ​​can be processed smoothly when performing the power function operation of gamma correction.

[0105] According to the core's power unit, such as Figure 8 As shown in the figure, it includes a logarithm operator, a floating-point reciprocal operator, a floating-point multiplier, and an exponential operator. The logarithm operator is used to calculate The floating-point reciprocal unit is used to calculate the result of The floating-point multiplier multiplies the result of the logarithm operation by the result of the reciprocal operation, and the output result is As input to the exponential operator, the exponential operator is used to calculate The result is the pixel value after Gamma correction (0< ≤1).

[0106] Finally, the pixel values ​​need to be remapped back to the integer range of 0-255 so that the corrected brightness values ​​can be converted back to a format that the display device can recognize. Figure 9 As shown, the data denormalization unit includes a floating-point shifter and a floating-point subtractor executed in series.

[0107] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. An acceleration device for calculating a gamma correction algorithm, characterized by: It includes: Value fetch unit, decoding unit, execution unit, memory access unit and write-back unit; The value fetch unit includes an instruction memory, a program counter, an instruction prefetch unit, a branch prediction unit, and a predecoding unit; the execution unit includes a branch instruction module, an ALU module, a MUL module, a DIV module, an FPU module, and a GAMMA unit that shares some logical resources with the ALU module and the FPU module; the memory access unit includes a data memory; the write-back unit includes an integer register file (GPR) and a floating-point register file (FPR); The opcode field of the GAMMA unit in the pre-decoding unit is constructed using a custom encoding format, using 7'b0001011 as the opcode. The circuit of the opcode recognition part includes a three-input NAND gate, two three-input AND gates, and a NOT gate. The instruction memory stores the machine code converted by the RISC-V program through the assembler and compiler; the program counter stores and updates the current instruction address; the branch prediction unit predicts the direction and target address of the branch instruction; the instruction prefetch unit judges and decodes the compressed instruction set, translating the 16-bit compressed instruction into a 32-bit basic instruction; the data memory stores data during program execution and is accessed by load or store instructions; the register stack is located inside the processor and stores operands and intermediate results; A total of 5 instructions are customized. The function of the fnorm instruction is to perform normalization operation on the input pixels, floating-point addition and then shift; the function of the frenorm instruction is to perform anti-normalization operation, floating-point shift and then subtraction; the function of the frec instruction is to perform floating-point reciprocal; the function of the fln instruction is to perform floating-point logarithm; the function of the fexp instruction is to perform floating-point exponentiation.

2. The acceleration device for calculating a gamma correction algorithm according to claim 1, wherein: The Gamma correction formula in the GAMMA unit is: ， ， ， ， ， in: is the input pixel value, the value range is 0≤ ≤255; γ is the γ correction value, and its value range is 0<γ<2.5; is the output pixel value, the value range is 0≤ ≤255; is the normalized pixel value, ranging from 0≤ ≤1; The value range is -∞< ≤0; The value range is -∞< ≤0; The value range is 0< ≤1.

3. The acceleration device for calculating a gamma correction algorithm according to claim 2, wherein: The instruction set of the GAMMA unit is defined as R-type instructions in the floating-point type, with a total of 5 instructions; opcode uses custom-0 unit, and identifies the custom instruction in the GAMMA unit according to the opcode code; funct7 is used to distinguish the specific instructions in the GAMMA unit; funct3 is all set to 000; rs2 is all set to 00000; funct7 is encoded using a one-hot code; The funct7 decoding circuit in the decoding unit decodes the required instructions through a one-to-one correspondence based on the encoding format of the one-hot code.

4. The acceleration device for calculating a gamma correction algorithm according to claim 3, wherein: The instruction set of the GAMMA unit is defined as the CA-type instructions in the compressed instruction type, with a total of 5 items; A compressed instruction set with a custom gamma correction algorithm is used in the value-taking unit. The length of the instructions in the compressed instruction set is 16 bits. The compressed instruction format of the custom gamma correction algorithm is distinguished from existing instructions by adjusting the encoding of op and funct2. The funct6 field of the compressed instruction set is encoded using a sequential shift sequence and a one-hot code, and each instruction only verifies and checks one bit of data.

5. The acceleration device for calculating a gamma correction algorithm according to claim 4, wherein: The GAMMA unit performs Gamma correction on the input image, including a data normalization unit, a lookup table unit, a power operation unit, and a data denormalization unit.

6. The acceleration device for calculating a gamma correction algorithm according to claim 5, wherein: The data normalization unit includes a serial floating-point adder and a floating-point shifter, which maps the input pixel value in the integer range of 0-255 to the real number range between 0-1.

7. The acceleration device for calculating a gamma correction algorithm according to claim 6, wherein: The lookup table unit stores the gamma correction values ​​corresponding to different grayscale value areas, and outputs the corresponding gamma correction value according to the input pixel value I.

8. The acceleration device for calculating a gamma correction algorithm according to claim 7, wherein: The power operation unit includes a floating-point reciprocal operator, a logarithm operator, a floating-point multiplier and an exponent operator, which pre-compensates the normalized pixel value to convert the data from the linear space to a nonlinear space suitable for the display device.

9. The acceleration device for calculating a gamma correction algorithm according to claim 8, wherein: The data denormalization unit includes a serial floating-point shifter and a floating-point subtractor, which maps the result of the power function operation after the gamma correction back to the integer range between 0 and 255.

10. A method for accelerating calculation of a gamma correction algorithm, using the acceleration device for calculating a gamma correction algorithm according to claim 1, characterized in that: It includes the following steps: (1) The instruction memory stores the machine code converted by the RISC-V program through the assembler and compiler. The program counter stores and updates the current instruction address. The branch prediction unit predicts the direction and target address of the branch instruction. The instruction prefetch unit judges and decodes the compressed instruction and translates the 16-bit compressed instruction into a 32-bit basic instruction. The data memory stores the data during program execution and is accessed by load or store instructions. The register stack is located inside the processor and stores operands and intermediate results. (2) The instruction is loaded into the instruction memory. The value fetching unit fetches the required instruction from the instruction memory according to the program counter and determines whether it is a compressed instruction. If it is a compressed instruction, it enters the instruction prefetching unit and translates the 16-bit compressed instruction into a 32-bit instruction. At the same time, the value fetching unit is paused to determine whether the next 16-bit instruction is a compressed instruction. If not, it is spliced ​​with the lower 16 bits of the 32-bit instruction. If it is, it enters the compressed instruction translation process again. There are 5 custom instructions in total. The function of the fnorm instruction is to perform normalization operation on the input pixels, floating-point addition and shift; the function of the frenorm instruction is to perform anti-normalization operation, floating-point shift and subtraction; the function of the frec instruction is to perform floating-point reciprocal operation; the function of the fln instruction is to perform floating-point logarithm; the function of the fexp instruction is to perform floating-point exponentiation; (3) The translated 32-bit instruction or the normal 32-bit instruction is first transmitted to the instruction pre-decoding unit, which inputs the 32-bit instruction and outputs the source operand and destination operand registers of the instruction and the control signal for loading non-operation type instructions; (4) The processing results of the 32-bit instruction and the pre-decoding unit are sent to the decoding unit. The decoding unit decodes the opcode, funct3 and funct7 in detail to obtain the detailed operation code of the large category of instructions, obtain all the detailed information of a single instruction, and obtain the control signal; the control signal and the source operand are then transmitted to the execution unit. The execution unit determines which operation unit the instruction flows to based on the control signal, enters the operation unit to obtain the result, and sends the result to the memory access stage; (5) If it is a load-store instruction, it enters the load-store unit and interacts with the data memory; if it is an instruction other than load-store, it directly enters the write-back unit and interacts with the integer register file or floating-point register file.

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