Chip edge breakage defect detection method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a chip edge breakage defect detection method and device, electronic equipment and a storage medium. The method comprises the following steps: determining an annular edge area of a chip to be detected from an initial image; smoothing the annular edge region to obtain a first image; performing gradient calculation on the first image to obtain a gradient image; and determining an edge breakage defect area of the to-be-detected chip in the initial image according to the gradient value of each pixel in the gradient image. According to the scheme, the detection rate of the edge breakage defect can be relatively high, the defect detection result is relatively accurate, and the defect detection efficiency is relatively high.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a chip edge collapse defect detection method, device, electronic equipment, storage medium and computer program product. Background Art

[0002] During the processing of semiconductor chips, the edges of the semiconductor chips may be damaged or broken due to excessive mechanical stress applied to the chips, improper packaging technology, or physical damage caused by other factors.

[0003] In the related art, chip edge collapse defects are usually detected manually. This detection method has a low level of automation and limited accuracy, and has the problem of low efficiency. Summary of the invention

[0004] The present invention is proposed in view of the above problems. The present invention provides a chip edge collapse defect detection method, device, electronic device, storage medium and computer program product. This solution can make the detection rate of edge collapse defects higher, the defect detection result more accurate, and the defect detection efficiency higher.

[0005] According to one aspect of the present invention, a chip edge collapse defect detection method is provided. The method comprises: determining an annular edge region of a chip to be tested from an initial image; performing smoothing on the annular edge region to obtain a first image; performing gradient calculation on the first image to obtain a gradient image; and determining an edge collapse defect region of the chip to be tested in the initial image according to the gradient value of each pixel in the gradient image.

[0006] Optionally, determining the annular edge area of ​​the chip to be tested from the initial image includes: acquiring a mask image of the chip to be tested based on the initial image; performing morphological corrosion processing on the mask image, and subtracting the pixel values ​​of each pixel point of the mask image subjected to the morphological corrosion processing with the corresponding pixel point of the mask image not subjected to the morphological corrosion processing to obtain an annular edge mask image; and extracting the corresponding annular edge area in the initial image according to the annular edge mask image.

[0007] Optionally, acquiring a mask image of the chip to be tested based on the initial image includes: performing dynamic threshold segmentation on the initial image according to a color value of the initial image in a target color channel to obtain the mask image.

[0008] Optionally, performing smoothing processing on the annular edge region to obtain the first image includes: performing mean filtering processing on the annular edge region to obtain the first image.

[0009] Optionally, before smoothing the annular edge region to obtain the first image, the method further includes: performing a contrast enhancement operation on the annular edge region.

[0010] Optionally, the contrast enhancement operation comprises a logarithmic transformation processing operation.

[0011] Optionally, determining the edge collapse defect area of ​​the chip to be tested in the initial image according to the gradient value of each pixel in the gradient image includes: performing dynamic threshold segmentation processing on the gradient image according to the gradient value of each pixel in the gradient image to obtain a segmentation result image; performing connected domain analysis on the segmentation result image to determine the edge collapse defect area of ​​the chip to be tested in the initial image, wherein the position of the edge collapse defect area in the initial image is consistent with the position of the connected domain determined by the connected domain analysis in the segmentation result image.

[0012] Optionally, dynamic threshold segmentation processing is performed on the gradient image according to the gradient value of each pixel in the gradient image, including: obtaining an initial segmentation threshold; determining a target segmentation threshold based on the initial segmentation threshold and a preset empirical adjustment value; and performing dynamic threshold segmentation processing on the gradient image using the target segmentation threshold according to the gradient value of each pixel in the gradient image.

[0013] Optionally, after determining the edge collapse defect area of ​​the chip to be tested in the initial image according to the gradient value of each pixel in the gradient image, the method further comprises: marking the edge collapse defect area in the initial image in a highlighted manner.

[0014] According to another aspect of the present invention, a chip edge collapse defect detection device is provided, comprising: a determination module for determining the annular edge region of the chip to be tested from the initial image; a smoothing module for smoothing the annular edge region to obtain a first image; a gradient calculation module for performing gradient calculation on the first image to obtain a gradient image; and a segmentation processing module for determining the edge collapse defect region of the chip to be tested in the initial image according to the gradient value of each pixel in the gradient image.

[0015] According to another aspect of the present invention, there is provided an electronic device, comprising: a processor and a memory, wherein the memory stores computer program instructions, and the computer program instructions are used to execute the above-mentioned chip edge collapse defect detection method when the processor is running.

[0016] According to another aspect of the present invention, a storage medium is provided, on which program instructions are stored, and the program instructions are used to execute the above-mentioned chip edge collapse defect detection method when running.

[0017] According to yet another aspect of the present invention, a computer program product is provided, comprising computer program instructions, wherein the computer program instructions are used to execute the chip edge collapse defect detection method as described above when the computer program instructions are run.

[0018] The above technical solution can make the noise amount in the obtained first image lower by smoothing the annular edge area, which is conducive to ensuring the accuracy of the calculation result obtained after the gradient calculation of the first image. On the other hand, the edge collapse defect area is determined based on the gradient value of each pixel in the gradient image, so that the screened edge collapse defect area can be more accurate, and this determination method can make the defect detection rate higher. Compared with manual detection of edge collapse defects, the automation level is higher, the defect detection result accuracy is higher, and the detection time can be effectively saved.

[0019] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other purposes, features and advantages of the present invention will become more apparent by describing the embodiments of the present invention in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0021] Figure 1 A schematic flow chart of a chip edge collapse defect detection method according to an embodiment of the present invention is shown;

[0022] Figure 2 A schematic diagram of an initial image of a chip to be tested according to an embodiment of the present invention is shown;

[0023] Figure 3 A schematic diagram of a ring edge mask image according to an embodiment of the present invention is shown;

[0024] Figure 4 A schematic diagram showing a mask image of a chip to be tested according to an embodiment of the present invention is shown;

[0025] Figure 5 A schematic diagram showing a first image obtained by performing logarithmic transformation and mean filtering on an annular edge region according to an embodiment of the present invention;

[0026] Figure 6 A schematic diagram of a gradient image according to an embodiment of the present invention is shown;

[0027] Figure 7 A flowchart of chip edge collapse defect detection according to an embodiment of the present invention is shown;

[0028] Figure 8A schematic flow chart of a chip edge collapse defect detection device according to an embodiment of the present invention is shown;

[0029] Fig. 9 A schematic block diagram of an electronic device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical scheme and advantages of the present invention more obvious, the exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments of the present invention, and it should be understood that the present invention is not limited to the exemplary embodiments described herein. Based on the embodiments of the present invention described in the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the protection scope of the present invention.

[0031] As described above, in the related art, chip edge collapse defects are usually detected manually, which has limited detection accuracy and low efficiency. In order to at least solve the above technical problems, the embodiments of the present invention provide a chip edge collapse defect detection method, device, electronic device, storage medium and computer program product. By using this solution to detect chip edge collapse, the detection rate of edge collapse defects is high, the defect detection results are more accurate, and the defect detection efficiency is high.

[0032] See also Figure 1 As shown, it is a schematic flow chart of a chip edge collapse defect detection method according to an embodiment of the present invention. According to one aspect of the present invention, a chip edge collapse defect detection method is provided, comprising: step S110, step S120, step S130 and step S140.

[0033] In step S110 , a ring-shaped edge region of the chip to be tested is determined from the initial image.

[0034] Exemplarily, the initial image may be an image obtained by an image acquisition device performing image acquisition on the chip to be tested. The image acquisition device may be, for example, a high-resolution camera, such as a camera based on a charge coupled device (CCD) or a complementary metal oxide conductor (CMOS). The image acquisition device may also be, for example, a linear array camera, a laser scanning confocal microscope, etc. The initial image may be an image with multiple color channels, such as an RGB image and a YCbCr image. The initial image may include an annular edge area of ​​the chip to be tested, and may also include an internal area of ​​the chip surrounded by the annular edge area of ​​the chip to be tested. Specifically, the annular edge area of ​​the chip to be tested may be a strip area with a width, and the surface of the chip to be tested may include the surface of the annular edge area and the surface of the internal area of ​​the chip surrounded by the annular edge area. Please refer to Figure 2As shown, it is a schematic diagram of an initial image of a chip to be tested according to an embodiment of the present invention. The initial image is an RGB image. Figure 2 In the case of the chip under test, the annular edge area is Figure 2 The dark annular area 210 with a smaller gray scale is shown in FIG. Figure 2 220 is shown as a light-colored square area with a larger grayscale. Any edge determination method can be used to determine the annular edge area from the initial image. In some embodiments, after acquiring the initial image, an edge detection algorithm can be used to determine the annular edge area of ​​the chip to be tested in the initial image. The edge detection algorithm can be, for example, an edge detection algorithm based on a Canny operator or a Sobel operator. In other embodiments, a template matching method can be used to determine the annular edge area in the initial image based on the matching result between the template image of the annular edge area and the initial image. In some other embodiments, the annular edge area can also be determined by manual annotation.

[0035] In step S120, the annular edge region is smoothed to obtain a first image.

[0036] Exemplarily, after the annular edge region is determined from the initial image, the annular edge region can be extracted from the initial image. In a specific embodiment, a mask image of the annular edge region can be generated based on the initial image, and the annular edge region can be extracted from the initial image through the generated mask image of the annular edge region to obtain a second image. It can be understood that the second image can only contain the annular edge region of the chip to be tested. It should be noted that the above scheme of extracting the annular edge region based on the mask image of the annular edge region is only an example, that is, other suitable methods can also be used to extract the annular edge region. For example, after the position information of the annular edge region in the initial image can be determined by any edge determination method (such as the above edge detection algorithm, template matching method, manual annotation method, etc.), the annular edge region can be directly extracted from the initial image based on the position information without generating a mask image. The first image can be obtained by smoothing the annular edge region in the second image. In other words, the first image can contain a smoothed annular edge region. Specifically, the smoothing process can be achieved by filtering, and the filtering method can be, for example, mean filtering, Gaussian filtering, median filtering, bilateral filtering, etc. In some embodiments, before smoothing the annular edge region in the second image, an image preprocessing operation, such as a contrast enhancement operation, a morphological operation, etc., may be performed on the annular edge region.

[0037] In step S130, a gradient calculation is performed on the first image to obtain a gradient image.

[0038] Exemplarily, gradient calculation can be used to determine the direction and amplitude of the change in pixel value in the image, wherein the direction may include the horizontal direction and the vertical direction. The method for performing gradient calculation on the first image may be, for example, a gradient calculation method based on the Sobel operator / Scharr operator / Laplacian operator, which is not specifically limited in the embodiment of the present invention. After performing gradient calculation on the first image, each pixel point in the obtained gradient image may have a corresponding gradient value, and the gradient value may include the amplitude and direction of the change in the pixel value at the pixel point. It can be understood that the larger the amplitude, the more drastic the change in the pixel value at the pixel point. The direction can be represented by an angle, and the angle range can be 0-360°.

[0039] In step S140, the edge collapse defect area of ​​the chip to be tested in the initial image is determined according to the gradient value of each pixel in the gradient image.

[0040] Exemplarily, a segmentation threshold may be set according to the gradient value of each pixel in the gradient image. In some embodiments, the gradient value of each pixel in the gradient image may be normalized so that the normalized gradient value is within the range of 0 to 255, and the segmentation threshold may be set according to the normalized gradient value. The gradient image may be segmented based on the segmentation threshold set, and the gradient image may be segmented into multiple connected domains. The segmented connected domain may be used as the target connected domain corresponding to the edge collapse defect area, or the multiple connected domains may be optionally screened according to preset screening rules to determine the target connected domain corresponding to the edge collapse defect area in the gradient image. The preset screening rules may, for example, include the size of the connected domain being within a preset range, and may also include the position of the connected domain being within a preset area of ​​the gradient image, and the preset area may, for example, be an area in the gradient image corresponding to the annular edge area. It can be understood that the position of the target connected domain in the gradient image is consistent with the position of the edge collapse defect area in the initial image, and the edge collapse defect area of ​​the chip to be tested may be determined in the initial image according to the positional relationship.

[0041] The above technical solution can make the noise amount in the obtained first image lower by smoothing the annular edge area, which is conducive to ensuring the accuracy of the calculation result obtained after the gradient calculation of the first image. On the other hand, the edge collapse defect area is determined based on the gradient value of each pixel in the gradient image, so that the screened edge collapse defect area can be more accurate, and this determination method can make the defect detection rate higher. Compared with manual detection of edge collapse defects, the automation level is higher, the defect detection result accuracy is higher, and the detection time can be effectively saved.

[0042] Optionally, determining the annular edge area of ​​the chip to be tested from the initial image includes: acquiring a mask image of the chip to be tested based on the initial image; performing morphological corrosion processing on the mask image, and subtracting the pixel values ​​of each pixel point of the mask image subjected to the morphological corrosion processing with the corresponding pixel point of the mask image not subjected to the morphological corrosion processing to obtain an annular edge mask image; and extracting the corresponding annular edge area in the initial image according to the annular edge mask image.

[0043] Exemplarily, a color threshold may be set based on the color value of each pixel of the initial image to obtain a mask image of the chip to be tested. In a specific embodiment, the initial image may be an RGB image, and the color space of the initial image may be converted from the RGB space to the HSV color space. The area corresponding to the chip to be tested in the initial image may be determined by defining a specific color value range to obtain the mask image of the chip to be tested. In another specific embodiment, the initial image may still be an RGB image, and the area corresponding to the chip to be tested in the initial image may be determined based on the color value of the chip to be tested under the target color channel in the three RGB color channels to obtain the mask image of the chip to be tested. Among them, the target color channel may be selected based on the color value of the chip to be tested under each color channel in the initial image. Exemplarily, a morphological corrosion process may be performed on the obtained mask image, and the morphological corrosion process may include an opening operation and a closing operation. The opening operation may be used to reduce noise in the mask image, and the closing operation may be used to fill holes in the mask image. The corrosion width of the morphological corrosion process may be determined based on the width of the target area that actually needs to be retained. In an embodiment of the present invention, the target area may include an annular edge area. Each pixel of the mask image processed by morphological corrosion corresponds to each pixel of the mask image not processed by morphological corrosion, and the pixel values ​​of the two corresponding pixels can be subtracted to obtain a ring edge mask image. Figure 3 FIG. 1 is a schematic diagram of an annular edge mask image according to an embodiment of the present invention. The annular edge region of the chip to be tested is Figure 3 In the image, it is displayed as a light-colored annular area with a higher grayscale value. After obtaining the annular edge mask image, a template matching method can be used to extract the annular edge area in the initial image based on the matching result between the annular edge mask image and the initial image. Alternatively, an annular connected domain corresponding to the annular edge area of ​​the chip to be tested in the annular edge mask image can be determined. The position of the annular connected domain in the annular edge mask image is consistent with the position of the annular edge area of ​​the chip to be tested in the initial image. Based on the positional relationship, each pixel point belonging to the annular edge area of ​​the chip to be tested can be determined in the initial image to extract the corresponding annular edge area.

[0044] The above technical solution performs morphological corrosion processing on the mask image of the chip to be tested, and obtains an annular edge mask image by subtracting the pixel values ​​of the mask image after morphological corrosion processing and the original mask image. This can effectively remove the noise in the mask image and retain the area in the mask image corresponding to the annular edge area of ​​the chip to be tested, thereby accurately extracting the annular edge area in the initial image and reducing the interference of the noise in the initial image on the extraction of the annular edge area.

[0045] Optionally, acquiring a mask image of the chip to be tested based on the initial image includes: performing dynamic threshold segmentation on the initial image according to a color value of the initial image in a target color channel to obtain the mask image.

[0046] Exemplarily, the segmentation threshold of dynamic threshold segmentation can be determined based on the color information of the image. When determining the target color channel of the initial image, the color value of the initial image under each color channel can be obtained, and the channel with the largest color value is selected as the target color channel. It can be understood that the image features of the initial image under the target color channel are more obvious than the image features under other color channels. For example, a certain initial image is an RGB image, and its color value under the G channel is higher than the color value under the R channel and the B channel. For this initial image, its target color channel can be the G channel. Specifically, for some chips, the corresponding initial image collected is overall greenish. In this case, the G channel can be used as the target color channel. More specifically, the average color value of each pixel of the initial image under each color channel can be obtained, and the average color value corresponding to each color channel can be used as the color value of the initial image under each color channel. Exemplarily, the initial image can be dynamically threshold segmented according to the color value of the initial channel under the target color channel. Specifically, the image processing method based on dynamic threshold segmentation can segment the initial image into multiple sub-regions by setting corresponding segmentation thresholds for pixels at different positions, and perform binarization processing on the initial image based on the segmentation thresholds of each sub-region to obtain a mask image. Figure 4 As shown in FIG. 1 , it is a schematic diagram of a mask image of a chip to be tested according to an embodiment of the present invention. Figure 4 In the illustrated embodiment, the target color channel of the initial image is the G channel. Accordingly, the segmentation threshold used by the dynamic threshold segmentation is determined based on the color value of the initial image under the G channel. Figure 4 The region with non-zero grayscale value in the mask image shown includes an outer annular region corresponding to the surface of the annular edge region and a square region surrounded by the outer annular region, which corresponds to the surface of the chip inner region surrounded by the annular edge region.

[0047] The above technical solution performs dynamic threshold segmentation on the initial image based on the color values ​​under the target color channel, and can use the most significant color information in the image to determine the segmentation threshold. The obtained segmentation threshold can be adapted to the visual features of the initial image, thereby more accurately determining the segmentation threshold of the initial image and obtaining a more accurate segmentation result.

[0048] Optionally, performing smoothing processing on the annular edge region to obtain the first image includes: performing mean filtering processing on the annular edge region to obtain the first image.

[0049] Exemplarily, the annular edge region can be subjected to mean filtering to achieve smoothing of the annular edge region. Specifically, the annular edge region in the initial image can be extracted to obtain the second image. In a specific embodiment, when the annular edge region is subjected to mean filtering, the neighborhood size of the pixel can be first defined, such as a neighborhood of 3*3 size. For each pixel point in the second image, the pixel values ​​of the pixel point and the pixel points in the neighborhood of the pixel point can be summed and averaged, and the obtained average value can be used as the new pixel value of the pixel point. Alternatively, the pixel values ​​of the pixel point and the pixel points in the neighborhood can be summed and averaged only for each pixel point in the second image belonging to the annular edge region, and the obtained average value can be used as the new pixel value of the pixel point.

[0050] The above technical solution can make the edge of the annular edge area smoother by performing mean filtering on the annular edge area, which is beneficial to reducing the interference of noise points in the subsequent gradient calculation of the annular edge area.

[0051] Optionally, before smoothing the annular edge region to obtain the first image, the method further includes: performing a contrast enhancement operation on the annular edge region.

[0052] Exemplarily, the second image can be obtained by extracting the annular edge region in the initial image. Before smoothing the annular edge region in the second image, a contrast enhancement operation can be performed on the annular edge region in the second image. Specifically, the contrast enhancement operation can be implemented by one or more methods such as linear stretching, histogram equalization, and logarithmic transformation. By performing the contrast enhancement operation on the annular edge region, the contrast of the annular edge region in the second image can be improved.

[0053] The above technical solution can enhance the image features of the annular edge area by enhancing the contrast of the annular edge area, which helps to perform targeted smoothing on the annular edge area.

[0054] Optionally, the contrast enhancement operation comprises a logarithmic transformation processing operation.

[0055] For example, for each pixel of at least a portion of the pixels in the second image of the above embodiment, including at least the pixels in the annular edge region, the following logarithmic transformation formula (1) may be used to process the pixel:

[0056] S=c*log(1+R) (1)

[0057] Where R is the initial pixel value of the pixel, S is the pixel value after logarithmic transformation, and c is a constant used to normalize the pixel value, specifically used to control the range of the pixel value S between 0 and 255. Figure 5 As shown, it is a schematic diagram of a first image obtained by performing logarithmic transformation and mean filtering on an annular edge region according to an embodiment of the present invention. Figure 5 In the figure, the annular region with non-zero grayscale value is the region corresponding to the annular edge region in the first image.

[0058] The above technical solution can enhance the low pixel value pixels in the annular edge area through logarithmic transformation processing, compress the dynamic range of the image, and help improve the contrast of the annular edge area. On the other hand, the annular edge area is processed by logarithmic transformation processing and mean filtering to obtain the first image, which can accurately remove the noise in the first image, and the edge collapse defect area in the initial image can be obtained more stably when the gradient of the first image is subsequently calculated.

[0059] Optionally, determining the edge collapse defect area of ​​the chip to be tested in the initial image according to the gradient value of each pixel in the gradient image includes: performing dynamic threshold segmentation processing on the gradient image according to the gradient value of each pixel in the gradient image to obtain a segmentation result image; performing connected domain analysis on the segmentation result image to determine the edge collapse defect area of ​​the chip to be tested in the initial image, wherein the position of the edge collapse defect area in the initial image is consistent with the position of the connected domain determined by the connected domain analysis in the segmentation result image.

[0060] See also Figure 6 As shown, it is a schematic diagram of a gradient image according to an embodiment of the present invention. Figure 6In the gradient image shown, the annular area with non-zero grayscale corresponds to the annular edge area of ​​the chip to be tested. In the gradient image, each pixel point can have a corresponding gradient value. Based on the gradient values ​​of the pixels at different positions in the gradient image, corresponding segmentation thresholds can be set for different areas in the gradient image. Each segmentation threshold can be used to perform dynamic threshold segmentation processing on the gradient image to obtain a segmentation result image that can contain multiple connected domains. By analyzing the multiple connected domains contained in the segmentation result image, the edge collapse defect area of ​​the chip to be tested in the initial image can be determined. Specifically, the connected domains in the segmentation result image can be analyzed by using methods such as Blob analysis method, maximum stable region detection algorithm (MSER), and flood fill algorithm (Flood Fill) to obtain multiple connected domains. By screening the determined multiple connected domains according to preset screening rules, the target connected domain corresponding to the edge collapse defect area can be determined in the segmentation result image. The preset screening rules can be specifically referred to the description of the aforementioned embodiment, which will not be repeated here. The position of the target connected domain in the segmentation result image is consistent with the position of the edge collapse defect area in the initial image. Based on the position of the target connected domain in the segmentation result image, the edge collapse defect area at the corresponding position can be determined in the initial image.

[0061] The above technical solution can dynamically adjust the threshold according to the local characteristics of the gradient image by performing dynamic threshold segmentation processing on the gradient image, which is beneficial to the segmentation accuracy and retains the area corresponding to the annular edge area in the gradient image, so that the obtained connected domain is closer to the surface morphology of the chip to be tested. On the other hand, by determining the edge collapse defect area of ​​the chip to be tested in the initial image based on the connected domain determined in the segmentation result image, the position accuracy of the edge collapse defect area in the obtained initial image can be higher, which is beneficial to the positioning of the defect position of the chip to be tested.

[0062] Optionally, dynamic threshold segmentation processing is performed on the gradient image according to the gradient value of each pixel in the gradient image, including: obtaining an initial segmentation threshold; determining a target segmentation threshold based on the initial segmentation threshold and a preset empirical adjustment value; and performing dynamic threshold segmentation processing on the gradient image using the target segmentation threshold according to the gradient value of each pixel in the gradient image.

[0063] Exemplarily, the segmentation threshold used in the dynamic threshold segmentation process can be determined based on the histogram of the gradient image. In a specific embodiment, the Otsu's Method can be used to obtain the initial segmentation threshold. In the Otsu's Method, the maximum inter-class variance g is defined by the following formula (2):

[0064] g=w0(u0-u)2+w1(u1-u)2 (2)

[0065] Wherein, u is the global average pixel value, u0 is the foreground average pixel value, u1 is the background average pixel value, w0 is the ratio of foreground pixels to all pixels, and w1 is the ratio of background pixels to all pixels. The pixel value of each pixel in the gradient image can be replaced by a normalized gradient value, and the obtained normalized gradient value is in the range of 0 to 255. In the above formula (2), the relationship between u0, u1, w0, and w1 can be expressed by the following formula (3):

[0066] u=w0*u0+w1*u1 (3)

[0067] Based on formula (2) and formula (3), the following formula (4) can be obtained:

[0068] g=w0w1(u0-u1)2 (4)

[0069] Exemplarily, a pixel value threshold T can be preset first, then the pixel points with pixel values ​​less than T are foreground pixels, the ratio of foreground pixels to all pixels of the gradient image is w0, and the average pixel value of foreground pixels is u0. Correspondingly, the pixel points with pixel values ​​greater than or equal to T are background pixels, the ratio of background pixels to all pixels of the gradient image is w1, and the average pixel value of background pixels is u1. It can be understood that w0+w1=1. By traversing and modifying the pixel value threshold T, the maximum inter-class variance g can be calculated, and the pixel value threshold T corresponding to the maximum value of the maximum inter-class variance g can be used as the initial segmentation threshold. After determining the initial segmentation threshold T, an empirical adjustment value δ can be preset based on actual needs, and the target segmentation threshold Tu can be determined based on the initial segmentation threshold T and the empirical adjustment value δ. In a specific embodiment, Tu=T+δ. The target segmentation threshold Tu can be used to perform dynamic threshold segmentation processing on the gradient image. Specifically, the pixel points in the gradient image whose pixel values ​​are less than the target segmentation threshold Tu can be set as foreground pixels, and the pixel points in the gradient image whose pixel values ​​are greater than or equal to the target segmentation threshold Tu can be set as background pixels. The pixel value of the foreground pixel point can be, for example, 0, and the pixel value of the background pixel point can be, for example, 255.

[0070] The above technical solution jointly determines the target segmentation threshold for dynamic threshold segmentation processing of the gradient image based on the initial segmentation threshold and the empirical adjustment value, which can make the segmentation result of the gradient image dynamically adjustable. Therefore, under the premise that the area corresponding to the edge collapse defect area in the gradient image is small, the details of the area can be avoided as much as possible from being lost or mis-segmented, which is beneficial to the accuracy and robustness of the segmentation.

[0071] Optionally, after determining the edge collapse defect area of ​​the chip to be tested in the initial image according to the gradient value of each pixel in the gradient image, the method further comprises: marking the edge collapse defect area in the initial image in a highlighted manner.

[0072] Exemplarily, the edge collapse defect area in the initial image can be highlighted, for example, the edge collapse defect area can be filled with other colors that are different from the non-edge collapse defect area, or the outline of the edge collapse defect area can be depicted with a highlight color. For example, in the initial image, the annular edge area of ​​the chip to be tested is dark green, the chip internal area surrounded by the annular edge area is green, and the background area other than the annular edge area and the chip internal area is blue. The determined edge collapse defect area can be marked with a specific color (such as red) that is different from dark green, green and blue. In this case, the edge collapse defect area can be filled with red, or the outline of the edge collapse defect area can be depicted with red.

[0073] The above technical solution can more intuitively display the position and size of the edge collapse defect area on the surface of the chip to be tested by marking the edge collapse defect area, which is beneficial to the user's observation.

[0074] See also Figure 7 As shown in FIG. 1 , it is a flow chart of chip edge collapse defect detection according to an embodiment of the present invention. Figure 7 In the illustrated embodiment, the initial image is an RGB image, and the color value of the image under the G channel is the largest. Accordingly, its target color channel is the G channel. According to the color value of the initial image under the G channel, the initial image can be segmented by dynamic threshold, and the target area (i.e., the surface area of ​​the chip to be tested) is screened out based on the segmentation result of the dynamic threshold segmentation to obtain the mask image of the chip to be tested. After obtaining the mask image of the chip to be tested, the mask image can be subjected to morphological corrosion processing, and the pixel values ​​of the mask image subjected to morphological corrosion processing and the original mask image not subjected to morphological corrosion processing are subtracted to obtain the annular edge mask image. Based on the annular edge mask image, the corresponding annular edge area can be extracted from the initial image, and the annular edge area is subjected to logarithmic transformation processing and mean filtering processing to obtain the first image. After obtaining the first image, the first image can be subjected to gradient calculation to obtain a gradient image, and the gradient image can be subjected to dynamic threshold segmentation according to the gradient value of each pixel in the gradient image to obtain the segmentation result image. The segmentation result image can include multiple connected domains, and the multiple connected domains can be analyzed to determine the target connected domain that meets the preset screening rules in the multiple connected domains. The edge collapse defect area of ​​the chip to be tested can be determined at the corresponding position in the initial image through the position of the target connected domain in the segmentation result image.

[0075] See also Figure 8As shown, it is a schematic flow chart of a chip edge collapse defect detection device according to an embodiment of the present invention. According to another aspect of the present invention, a chip edge collapse defect detection device 800 is also provided, comprising:

[0076] A determination module 810 is used to determine the annular edge area of ​​the chip to be tested from the initial image;

[0077] A smoothing processing module 820, configured to perform smoothing on the annular edge region to obtain a first image;

[0078] A gradient calculation module 830, configured to perform gradient calculation on the first image to obtain a gradient image;

[0079] The segmentation processing module 840 is used to determine the edge collapse defect area of ​​the chip to be tested in the initial image according to the gradient value of each pixel in the gradient image.

[0080] See also Fig. 9 As shown, it is a schematic block diagram of an electronic device according to an embodiment of the present invention. According to another aspect of the present invention, an electronic device 900 is also provided, including: a processor 910 and a memory 920, wherein the memory 920 stores computer program instructions, and the computer program instructions are used by the processor 1010 to execute the above-mentioned chip edge collapse defect detection method when running.

[0081] According to another aspect of the present invention, a storage medium is also provided, on which program instructions are stored, and when the program instructions are executed by a computer or a processor, the computer or the processor executes the corresponding steps of the chip collapse defect detection method according to the embodiment of the present invention, and is used to implement the corresponding modules in the chip collapse defect detection device according to the embodiment of the present invention or the corresponding modules in the chip collapse defect detection device. The storage medium may include, for example, a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, or any combination of the above storage media. The computer-readable storage medium may be any combination of one or more computer-readable storage media.

[0082] According to yet another aspect of the present invention, a computer program product is provided, comprising computer program instructions, wherein the computer program instructions are used to execute the chip edge collapse defect detection method as described above when the computer program instructions are run.

[0083] A person skilled in the art can understand the specific implementation and beneficial effects of the above-mentioned chip edge collapse defect detection device by reading the above-mentioned detailed description of the chip edge collapse defect detection method, and for the sake of brevity, it will not be repeated here.

[0084] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present invention thereto. Various changes and modifications may be made therein by one of ordinary skill in the art without departing from the scope and spirit of the present invention. All such changes and modifications are intended to be included within the scope of the present invention as required by the appended claims.

[0085] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0086] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0087] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0088] Similarly, it should be understood that in order to streamline the present invention and help understand one or more of the various inventive aspects, in the description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present invention should not be interpreted as reflecting the following intention: the claimed invention requires more features than the features explicitly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby expressly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present invention.

[0089] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0090] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.

[0091] The various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all of the functions of some modules in a chip collapse defect detection device according to an embodiment of the present invention. The present invention may also be implemented as a device program (e.g., a computer program and a computer program product) for executing part or all of the methods described herein. Such a program for implementing the present invention may be stored on a computer-readable medium, or may be in the form of one or more signals. Such a signal may be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0092] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0093] The above is only a specific embodiment or description of a specific embodiment of the present invention, and the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A chip edge collapse defect detection method, characterized in that: include: Determine the annular edge region of the chip to be tested from the initial image; Performing smoothing on the annular edge region to obtain a first image; Performing gradient calculation on the first image to obtain a gradient image; The edge collapse defect area of ​​the chip to be tested in the initial image is determined according to the gradient value of each pixel in the gradient image.

2. The method according to claim 1, characterized in that The step of determining the annular edge region of the chip to be tested from the initial image includes: Acquire a mask image of the chip to be tested based on the initial image; Performing morphological corrosion processing on the mask image, and performing pixel value difference between each pixel point of the mask image subjected to morphological corrosion processing and the corresponding pixel point of the mask image not subjected to morphological corrosion processing, so as to obtain a ring-shaped edge mask image; The annular edge region corresponding to the annular edge is extracted from the initial image according to the annular edge mask image.

3. The method according to claim 2, characterized in that The step of acquiring the mask image of the chip to be tested based on the initial image includes: The initial image is segmented using a dynamic threshold value according to the color value of the initial image in the target color channel to obtain the mask image.

4. The method according to any one of claims 1 to 3, characterized in that: The step of smoothing the annular edge region to obtain a first image includes: Perform mean filtering on the annular edge area to obtain the first image.

5. The method according to any one of claims 1 to 3, characterized in that: Before the smoothing process is performed on the annular edge region to obtain the first image, the method further includes: A contrast enhancement operation is performed on the annular edge region.

6. The method according to claim 5, characterized in that The contrast enhancement operation includes a logarithmic transformation processing operation.

7. The method according to any one of claims 1 to 3, characterized in that: The step of determining the edge collapse defect area of ​​the chip to be tested in the initial image according to the gradient value of each pixel in the gradient image comprises: According to the gradient value of each pixel in the gradient image, the gradient image is subjected to dynamic threshold segmentation processing to obtain a segmentation result image; A connected domain analysis is performed on the segmentation result image to determine the edge collapse defect area of ​​the chip to be tested in the initial image, wherein the position of the edge collapse defect area in the initial image is consistent with the position of the connected domain determined by the connected domain analysis in the segmentation result image.

8. The method according to claim 7, characterized in that The step of performing dynamic threshold segmentation processing on the gradient image according to the gradient value of each pixel in the gradient image comprises: Get the initial segmentation threshold; Determine a target segmentation threshold based on the initial segmentation threshold and a preset empirical adjustment value; According to the gradient value of each pixel in the gradient image, the target segmentation threshold is used to perform dynamic threshold segmentation processing on the gradient image.

9. The method according to any one of claims 1 to 3, characterized in that: After determining the edge collapse defect area of ​​the chip to be tested in the initial image according to the gradient value of each pixel in the gradient image, the method further includes: The edge chipping defect area is marked in a highlighted manner in the initial image.

10. A chip edge collapse defect detection device, characterized in that: include: A determination module, used for determining the annular edge area of ​​the chip to be tested from the initial image; A smoothing processing module, used for performing a smoothing process on the annular edge area to obtain a first image; A gradient calculation module, used for performing gradient calculation on the first image to obtain a gradient image; The segmentation processing module is used to determine the edge collapse defect area of ​​the chip to be tested in the initial image according to the gradient value of each pixel in the gradient image.

11. An electronic device comprising a processor and a memory, characterized in that: The memory stores computer program instructions, and the computer program instructions are used by the processor to execute the chip edge collapse defect detection method according to any one of claims 1 to 9 when the processor is running.

12. A storage medium having program instructions stored thereon, characterized in that: The program instructions are used to execute the chip edge collapse defect detection method as described in any one of claims 1 to 9 when running.

13. A computer program product comprising computer program instructions, characterized in that The computer program instructions are used to execute the chip edge collapse defect detection method according to any one of claims 1 to 9 when running.

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