Display module and display device

Abstract

The invention provides a display module and a display device, the display module comprises a display panel and a circuit board, and the circuit board is electrically connected with the display panel. The display panel comprises a substrate, a driving circuit and a pixel circuit, the driving circuit and the pixel circuit are located on the substrate, the driving circuit provides control signals for the pixel circuit, and the display panel further comprises a signal line set and a plurality of connecting bonding pads; the first signal line group comprises M signal lines for providing signals for the first driving circuit, the second signal line group comprises N signal lines for providing signals for the second driving circuit, M is greater than or equal to 1, and N is greater than or equal to 1. A first pin on the circuit board is connected with the signal line through a connection bonding pad. A first signal line in the M signal lines and a second signal line in the N signal lines are signal lines for transmitting signals with the same function; the first signal line and the second signal line are electrically connected with the same first pin. According to the scheme, the number of the first pins occupied on the circuit board can be reduced, and the utilization efficiency of the first pins can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display module and a display device. Background Art

[0002] With the continuous development of display technology, display panels usually need to transmit multiple scanning signals to pixel circuits when they are working, so as to adjust the working state of the pixel circuits. It should be noted that the above scanning signals can be generated by multiple scanning circuits on the display panel, and the scanning circuits need to rely on multiple electrical signals supplied by the circuit board to generate the above scanning signals.

[0003] Generally, a scanning circuit can receive the required electrical signal through a path formed by connecting signal lines, pads, and pins on a circuit board, and the same scanning circuit often needs to receive electrical signals transmitted by multiple signal lines. In the prior art, different scanning circuits often need to receive the same functional signal, but the paths corresponding to the above different scanning circuits often correspond to different pins, resulting in unnecessary occupation of pins on the circuit board, which is not conducive to the rationality of circuit structure design. Summary of the invention

[0004] In view of this, the present application provides a display module and a display device to solve the problem of unnecessary occupation of the above-mentioned pins.

[0005] In a first aspect, an embodiment of the present application provides a display module, including a display panel and a circuit board, wherein the circuit board is electrically connected to the display panel; the display panel includes: substrate substrate; A driving circuit and a pixel circuit, wherein the driving circuit and the pixel circuit are located on a substrate, and the driving circuit provides a control signal for the pixel circuit; Signal line, which provides signals for the driving circuit; The driving circuit includes a first driving circuit and a second driving circuit; A signal line group, the signal line group includes a first signal line group and a second signal line group, the first signal line group includes M signal lines providing signals for the first driving circuit, the second signal line group includes N signal lines providing signals for the second driving circuit, M ≥ 1, N ≥ 1; The display panel further comprises a plurality of connection pads; the circuit board comprises a plurality of first pins, and the first pins are connected to the signal lines through the connection pads; The first signal line among the M signal lines and the second signal line among the N signal lines are signal lines that transmit signals with the same function; the first signal line and the second signal line are electrically connected to the same first pin.

[0006] In a second aspect, an embodiment of the present application provides a display device, comprising the display panel provided in the first aspect.

[0007] The configuration method of the embodiment of the present application can reduce the number of occupied first pins on the circuit board, which is beneficial to improving the utilization efficiency of the first pins and helps to enhance the rationality of the circuit connection method. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0009] Figure 1 A schematic diagram of the connection relationship between partial structures of a display module related to the present application; Figure 2 A schematic diagram of a partial structure of a display module provided in the present application; Figure 3 A schematic diagram of a partial structure of a display module provided in the present application; Figure 4 An equivalent circuit diagram of a pixel circuit provided in this application; Figure 5 An equivalent circuit diagram of a gate drive circuit provided in this application; Figure 6 An equivalent circuit diagram of another gate drive circuit provided in the present application; Figure 7 An equivalent circuit diagram of another gate drive circuit provided in the present application; Figure 8 A schematic diagram of a partial structure of a display module provided in the present application; Fig. 9 A schematic diagram of a partial structure of a display module provided in the present application; Fig.10 A schematic diagram of a partial structure of a partial gate drive circuit group provided in the present application; Fig.11 A schematic diagram of a partial structure of a display module provided in the present application; Fig.12 The figure is a schematic diagram showing the change of the potential of the electric signal transmitted by the first type of signal line in one working cycle of the driving circuit; Fig.13 A schematic diagram of a partial structure of a display panel provided in the present application; Fig.14 for Fig.13A bottom view schematic diagram of a partial structure of a display panel shown; Fig.15 A schematic diagram of a display device provided in the present application. DETAILED DESCRIPTION

[0010] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0011] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0012] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0013] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0014] With the continuous development of display technology, the application scenarios of display devices are becoming more and more abundant, and the working modes of light-emitting devices in display devices are becoming more and more diversified. The main schemes for adjusting the working mode of light-emitting devices at present may include: adjusting the light-emitting state of the light-emitting device by adjusting the light-emitting driving current characteristics (such as amplitude, pulse width, etc.) provided by the pixel circuit to the light-emitting device.

[0015] It should be noted that adjusting the scanning signal transmitted to the pixel circuit to change the working state of the pixel circuit is a common practice for adjusting the above characteristics of the light-emitting drive current. The scanning signal received by the pixel circuit is usually provided by the scanning circuit on the display panel, and the scanning circuit often needs to receive an electrical signal (which can be called a circuit board signal) supplied by the circuit board to generate the above scanning signal.

[0016] Figure 1 The figure is a schematic diagram of the connection relationship between some structures of a display module related to the present application.

[0017] like Figure 1As shown, the existing display panel 10' may include multiple scanning circuits 01', including a first scanning circuit 01a' and a second scanning circuit 01b'. The scanning signal provided by the first scanning circuit 01a' to the pixel circuit 02' and the scanning signal provided by the second scanning circuit 01b' to the pixel circuit can act on different functional modules in the pixel circuit 02' respectively.

[0018] The scanning circuit 01' can be electrically connected to the pin 11a' of the circuit board 11' through the path 02' located on the display panel 10', and the circuit board 11' can transmit the circuit board signal required by it to the scanning circuit 01' through the path 02', wherein the circuit board 11' can be a flexible circuit board. Generally, the path 02' can be electrically connected to the pin 11a' in a one-to-one correspondence, and different scanning circuits 01' correspond to different pins 11a'. For example, Figure 1 As shown, the first scanning circuit 01a' is electrically connected to the first pin 11a1' through the first path 021', and the second scanning circuit 01b' is electrically connected to the second pin 11a2' through the second path 022'. At this time, it can be considered that the first scanning circuit 01a' and the second scanning circuit 01b' occupy two pins 11a' in total.

[0019] It should be noted that there are often different scanning circuits 01' that need to receive circuit board signals with the same function. For example, when the circuit board signal that the first scanning circuit 01a' needs to receive through the first path 021' and the circuit board signal that the second scanning circuit 01b' needs to receive through the second path 022' are mutually identical functional signals, the electrical signal output by the circuit board 11' through the first pin 11a1' and the electrical signal output through the second pin 11a2' can be identical. For two circuit board signals that are mutually identical functional signals, the circuit board 11' can output the two circuit board signals through the same pin 11a1'. However, the existing design scheme is that the first scanning circuit 01a' and the second scanning circuit 01b' occupy two pins 11a', that is, the circuit board 11' outputs circuit board signals that are mutually identical functional signals through the two pins 11a', which results in a waste of the number of pins 11a' of the circuit board 11', which is not conducive to the reasonable occupation of the pins 11a'.

[0020] Figure 2 This is a schematic diagram of a partial structure of a display module provided in this application. For ease of understanding, Figure 2 Only the connection relationship between some structures on the display panel and between some structures on the display panel and the pins of the circuit board is shown, and the specific structure of each circuit structure is not shown in detail.

[0021] In response to the above problems, Figure 2As shown, the present application provides a display module 20 , including a display panel 10 and a circuit board 11 , wherein the circuit board 11 is electrically connected to the display panel 10 .

[0022] The display panel 10 includes a base substrate 01, a driving circuit 02 and a pixel circuit 03. The driving circuit 02 and the pixel circuit 03 are located on the base substrate 01. The driving circuit 02 provides a control signal for the pixel circuit 03. The control signals provided by different driving circuits 02 can act on different functional modules in the pixel circuit 03 respectively.

[0023] The display panel 10 further includes a signal line 04 , which provides a signal to the driving circuit 02 . The signal provided by the signal line 04 to the driving circuit 02 may come from the circuit board 11 .

[0024] The driving circuit 02 includes a first driving circuit 021 and a second driving circuit 022. The control signal output by the first driving circuit 021 and the control signal output by the second driving circuit 022 can act on different structures on the pixel circuit 03 respectively. The influence of the control signal output by the first driving circuit 021 on the working state of the pixel circuit 03 can be different from the influence of the control signal output by the second driving circuit 022 on the working state of the pixel circuit 03.

[0025] The display panel 10 may further include a signal line group 040 , the signal line group 040 includes a first signal line group 0401 and a second signal line group 0402 , the first signal line group 0401 includes M signal lines 04 providing signals to the first driving circuit 021 , the second signal line group 0402 includes N signal lines 04 providing signals to the second driving circuit 022 , M≥1, N≥1.

[0026] The display panel 10 further includes a plurality of connection pads 05, which can be electrically connected to the signal line 04, that is, the drive circuit 02 can receive the circuit board signal transmitted by the circuit board 11 through the connection pads 05 electrically connected to the signal line 04. It should be noted that there can be a one-to-one electrical connection between the signal line 04 and the connection pads 05, or there can be multiple signal lines 04 electrically connected to the same connection pad 05 (this situation is not described in detail). Figure 2 ).

[0027] The circuit board 11 includes a plurality of first pins 111 , and the first pins 111 are connected to the signal line 04 through the connection pads 05 . In this case, the circuit board 11 may be a flexible circuit board. The connection pads 05 may be electrically connected to the first pins 111 to achieve electrical connection between the circuit board 11 and the display panel 10 .

[0028] The first signal line 041 among the M signal lines 04 and the second signal line 042 among the N signal lines 04 are signal lines that transmit signals of the same function. For example, the first signal line 041 and the second signal line 042 can both transmit clock signals or power supply voltage signals.

[0029] The first signal line 041 and the second signal line 042 are both electrically connected to the same first pin 111. Since the signals transmitted by the first signal line 041 and the second signal line 042 are signals of the same function, the circuit board 11 can transmit the required electrical signals to the first signal line 041 and the second signal line 042 through the same first pin 111.

[0030] Compared with the first signal line 041 and the second signal line 042 receiving the required electrical signals through different first pins 111 respectively, the setting method of the embodiment of the present application can reduce the number of occupied first pins 111 on the circuit board 11, which is beneficial to improving the utilization efficiency of the first pins 111 and helping to enhance the rationality of the circuit connection method.

[0031] Figure 3 This is a schematic diagram of a partial structure of a display module provided in this application. For ease of understanding, Figure 3 Only the connection relationship between some structures on the display panel and between some structures on the display panel and the pins of the circuit board is shown, and the specific structure of each circuit structure is not shown in detail.

[0032] In one embodiment of the present application, Figure 3 As shown, the circuit board 11 also includes a second pin 112, and the connection pad 05 is connected to the second pin 112 correspondingly. At this time, the circuit board 11 can be a flexible printed circuit (Flexible Printed Circuit), and the circuit board 11 can include a receiving side 11a and an output side 11b. The first pin 111 can be located in an area close to the receiving side 11a on the circuit board 11, and the second pin 112 can be located in an area close to the output side 11b on the circuit board 11. The first pin 111 can be used to receive an electrical signal, and can transmit the received electrical signal to the second pin 112, and the second pin 112 can transmit the electrical signal received from the first pin 111 to the connection pad 05. On the circuit board 11, there may be a situation where some of the first pins 111 are connected to the second pins 112 correspondingly, and there may also be a situation where multiple second pins 112 are electrically connected to the same first pin 111.

[0033] The connection pad 05 may include a first pad 051 and a second pad 052. The first pad 051 is electrically connected to the first signal line 041, and the second pad 052 is electrically connected to the second signal line 042. Since the connection pad 05 is correspondingly connected to the second pin 112, the first signal line 041 and the second signal line 042 can receive the required electrical signals through different second pins 112.

[0034] The second pin 112 corresponding to the first pad 051 and the second pin 112 corresponding to the second pad 052 are electrically connected to the same first pin 111. In the circuit board 11, the second pin 112 corresponding to the first pad 051 (which can be called the first type of pin) and the second pin 112 corresponding to the second pad 052 (which can be called the second type of pin) can be electrically connected to the same first pin 111 through two routing structures L respectively. Among them, the above-mentioned connection method of connecting the same structure (such as the first pin 111) through two routing structures L can be called a branch line connection method. Under this branch line connection method, there are multiple routing structures L that all transmit the same electrical signal, and the routing distribution range for transmitting the same electrical signal is relatively wide. It should be noted that the wider the distribution range of the routing that transmits the same electrical signal, the higher the risk of the electrical signal being interfered by the outside world. Therefore, when implementing the above-mentioned branch line connection method, corresponding measures can be considered to reduce interference with the electrical signal.

[0035] In the embodiment of the present application, by setting the above-mentioned first type of pins and the above-mentioned second type of pins to be electrically connected to the same first pin 111, it is helpful to realize that the first signal line 041 and the second signal line 042 correspond to the same first pin 111, which is helpful to reduce the number of occupied first pins 111 and help rationalize the connection method. In addition, compared with the display panel 10, the film layer structure of the circuit board 11 (when used as a flexible circuit board) is simpler, and the degree of external interference to the electrical signal transmitted by the wiring on the circuit board 11 is weaker. Therefore, the present application can reduce the number of occupied first pins 111 by implementing the above-mentioned branch line connection method on the circuit board 11, and at the same time minimize the interference of the environment on the electrical signal transmitted in the above-mentioned wiring structure L.

[0036] In one embodiment of the present application, the first signal line 041 and the second signal line 042 are both clock signal lines.

[0037] In the embodiment of the present application, the electrical signal transmitted by the clock signal line may be a clock signal, and the potential of the clock signal is volatile. Compared with the constant potential electrical signal, the clock signal is more susceptible to external interference. Considering that the first signal line 041 and the second signal line 042 can be connected to the same first pin 111 on the circuit board 11 in the above-mentioned branch line connection method, the setting method of this embodiment can reduce the degree of environmental interference with the above-mentioned clock signal while reducing the number of occupied first pins 111.

[0038] Figure 4 An equivalent circuit diagram of a pixel circuit provided in this application.

[0039] In one embodiment of the present application, Figure 4 As shown, the pixel circuit 03 includes an amplitude modulation subcircuit 031 and a pulse width modulation subcircuit 032, and the amplitude modulation subcircuit 031 can be connected to the pulse width modulation subcircuit 032. The pixel circuit 03 generates a driving current under the control of the amplitude modulation subcircuit 031 and the pulse width modulation subcircuit 032. The amplitude modulation subcircuit 031 can be used to control the amplitude of the driving current, and the pulse width modulation subcircuit 032 can be used to adjust the pulse width of the voltage applied to the light emitting device 033.

[0040] like Figure 4 As shown, the amplitude modulation subcircuit 031 includes a first driving transistor T11, a first data writing transistor T12, a first regulating transistor T13, a first voltage writing transistor T14, a first voltage transmission transistor T15, a first reset transistor T16, a first modulation transistor T17, a first output transistor T18, a second reset transistor T19, a second voltage transmission transistor T20 and a third voltage transmission transistor T10.

[0041] Among them, the control end of the first voltage transmission transistor T15 can receive the scan signal transmitted by the third scan line S3, and the scan signal transmitted by the third scan line S3 can control the power supply voltage signal transmitted by the first power supply voltage signal line VDD1 to be written into the input end of the first driving transistor T11. The control end of the second reset transistor T19 can receive the scan signal transmitted by the fourth scan line S4, and the scan signal transmitted by the fourth scan line S4 can control the electric signal (which can be called the first reset signal) transmitted by the reset signal line Vset to be written into the control end of the first modulation transistor T17. The input end of the first reset transistor T16 can receive the scan signal (which can be called the second reset signal) transmitted by the fifth scan line S5. When the first reset transistor T16 is turned on, the scan signal transmitted by the fifth scan line S5 can be written into the control end of the first driving transistor T11 to complete the reset process. The control end of the first output transistor T18 can receive the scan signal transmitted by the second scan line S2, and the scan signal transmitted by the second scan line S2 can control the drive current to be written into the first electrode of the light-emitting device L.

[0042] The pulse width modulation sub-circuit 032 includes a second driving transistor T21, a second data writing transistor T22, a second regulating transistor T23, a second voltage writing transistor T24, a second voltage transmission transistor T25, a third reset transistor T26 and a second output transistor T27.

[0043] like Figure 4As shown, the control end of the first data writing transistor T12, the control end of the first regulating transistor T13, the control end of the second data writing transistor T22, and the control end of the second regulating transistor T23 can all receive the scanning signal transmitted by the sixth scanning line S6, then the scanning signal transmitted by the sixth scanning line S6 can control the data signal transmitted by the second data signal line Vdata2 to be written into the control end of the first driving transistor T11, and can also control the data signal transmitted by the first data signal line Vdata1 to be written into the control end of the second driving transistor T21, thereby completing the data writing process. The first electrode plate of the second capacitor C2 can receive the scanning signal transmitted by the first scanning line S1, and the second electrode plate of the second capacitor C2 can be electrically connected to the control end of the second driving transistor T21, then the scanning signal transmitted by the first scanning line S1 can be used to control the potential size of the control end of the second driving transistor T21.

[0044] It should be noted that all transistors in the pixel circuit 03 may be P-type transistors.

[0045] Figure 5 An equivalent circuit diagram of a gate drive circuit provided in this application, Figure 6 Another equivalent circuit diagram of a gate drive circuit provided in this application, it should be noted that: Figure 5 The circuit diagram shown can illustrate the circuit structure of the first gate driving circuit and the circuit structure of the second gate driving circuit.

[0046] Combination Figure 5 and Figure 6 The display panel 10 further includes a first gate driving circuit 061 , a second gate driving circuit 062 and a third gate driving circuit 063 .

[0047] The electrical signal output by the first gate driving circuit 061 adjusts the gate potential of the second driving transistor T21 in the pulse width modulation sub-circuit 032. The output end of the first gate driving circuit 061 can be electrically connected to the first scanning line S1, and the scanning signal output by the first gate driving circuit 061 can be transmitted to the first electrode plate of the second capacitor C2 via the first scanning line S1, thereby adjusting the gate potential of the second driving transistor T21.

[0048] The electrical signal output by the second gate driving circuit 062 controls the amplitude modulation subcircuit 031 to output the light-emitting driving current. The output end of the second gate driving circuit 062 can be electrically connected to the second scanning line S2, and the scanning signal output by the second gate driving circuit 062 can be transmitted to the control end of the first output transistor T18 via the second scanning line S2, thereby controlling the light-emitting driving current to be output to the light-emitting device L.

[0049] The electrical signal output by the third gate driving circuit 063 controls the power supply voltage signal to be written into the pulse width modulation sub-circuit 032. The output end of the third gate driving circuit 063 can be electrically connected to the third scanning line S3, and the scanning signal output by the third gate driving circuit 063 can be transmitted to the control end of the first voltage transmission transistor T15 via the third scanning line S3, thereby controlling the power supply voltage signal transmitted by the first power supply voltage signal line VDD1 to be written into the input end of the first driving transistor T11.

[0050] The first driving circuit 021 and the second driving circuit 022 are two of the first gate driving circuit 061 , the second gate driving circuit 062 and the third gate driving circuit 063 , respectively.

[0051] For example, Figure 5 As shown, the first driving circuit 021 is a first gate driving circuit 061, and the second driving circuit 022 is a second gate driving circuit 062. The second positive clock signal line CK2 in the first gate driving circuit 061 and the second positive clock signal line CK2 in the second gate driving circuit 062 can be connected to the same first pin 111. The first counter-clock signal line CKB1 in the first gate driving circuit 061 and the first counter-clock signal line CKB1 in the second gate driving circuit 062 can also be connected to the same first pin 111.

[0052] For example, combined with Figure 5 and Figure 6 The first driving circuit 021 is a first gate driving circuit 061, and the second driving circuit 022 is a third gate driving circuit 063. The second positive clock signal line CK2 in the first gate driving circuit 061 and the third positive clock signal line CK3 in the third gate driving circuit 063 can be connected to the same first pin 111. The first counter-clock signal line CKB1 in the first gate driving circuit 061 and the second counter-clock signal line CKB2 in the third gate driving circuit 063 can also be connected to the same first pin 111.

[0053] like Figure 5 As shown, when the first lower output transistor T41 is turned on, the output end of the first gate drive circuit 061 can directly output the electrical signal transmitted by the first positive clock signal line CK1, and all pixel circuits 03 corresponding to the first gate drive circuit 061 can receive the electrical signal transmitted by the first positive clock signal line CK1 at this time. The first positive clock signal line CK1 needs to provide electrical signals to the corresponding number of pixel circuits 03 connected to the output end of the first gate drive circuit 061. In this case, it can be considered that the load of the first positive clock signal line CK1 is relatively large. On the other hand, Figure 5As shown, the output end of the first gate drive circuit 061 cannot directly output the electrical signal transmitted by the second positive clock signal line CK2, then the load of the second positive clock signal line CK2 is smaller than that of the first positive clock signal line CK1. In the present application, the preferred configuration includes connecting the two signal lines with larger loads to different first pins 111, and connecting the two signal lines with smaller loads to the same first pin 111, so as to avoid the electrical signal transmitted by the same first pin 111 being unable to bear the transmission requirements of the two signal lines with larger loads, and at the same time reduce the number of occupied first pins 111.

[0054] In this embodiment, combined with Figure 5 and Figure 6 It can be seen that the first driving circuit 021 and the second driving circuit 022 will not directly output the electrical signals transmitted by the above clock signal lines (the second positive clock signal line CK2, the first reverse clock signal line CKB1, and the third positive clock signal line CK3), so the load corresponding to the above clock signal lines can be relatively small. Therefore, in this embodiment, a plurality of the above clock signal lines can be electrically connected to the same first pin 111, which helps to reduce the number of occupied first pins 111.

[0055] Figure 7 Another equivalent circuit diagram of a gate drive circuit provided in this application, it should be noted that: Figure 7 The circuit diagram shown can illustrate the circuit structure of the fourth gate driving circuit, and can also illustrate the circuit structure of the fifth gate driving circuit.

[0056] Alternatively, the display panel 10 further includes a fourth gate driving circuit 064 and a fifth gate driving circuit 065 .

[0057] like Figure 7 As shown, the electrical signal output by the fourth gate driving circuit 064 controls the first reset signal to be written into the amplitude modulation sub-circuit 031, and the output end of the fourth gate driving circuit 064 can be electrically connected to the fourth scanning line S4, then the scanning signal output by the fourth gate driving circuit 064 can be transmitted to the control end of the second reset transistor T19 via the fourth scanning line S4, and then control the first reset signal transmitted by the reset signal line Vset to be written into the control end of the first modulation transistor T17.

[0058] The fifth gate driving circuit 065 controls the second reset signal to be written into the amplitude modulation sub-circuit 031 and the pulse width modulation sub-circuit 032. The output end of the fifth gate driving circuit 065 can be electrically connected to the fifth scan line S5, and the second reset signal output by the fifth gate driving circuit 065 can be transmitted to the input end of the first reset transistor T16 and the input end of the third reset transistor T26 via the fifth scan line S5.

[0059] The first driving circuit 021 and the second driving circuit 022 are respectively the fourth gate driving circuit 064 and the fifth gate driving circuit 065 .

[0060] For example, Figure 7 As shown, the first driving circuit 021 is the fourth gate driving circuit 064, and the second driving circuit 022 is the fifth gate driving circuit 065. The fourth positive clock signal line CK4 in the fourth gate driving circuit 064 and the fourth positive clock signal line CK4 in the fifth gate driving circuit 065 can be connected to the same first pin 111. The third counter-clock signal line CKB3 in the fourth gate driving circuit 064 and the third counter-clock signal line CKB3 in the fifth gate driving circuit 065 can also be connected to the same first pin 111.

[0061] In this embodiment, if Figure 7 As shown, the first driving circuit 021 and the second driving circuit 022 will not directly output the electrical signal transmitted by the above-mentioned clock signal lines (the fourth positive clock signal line CK4 and the third negative clock signal line CKB3), so the load corresponding to the above-mentioned clock signal lines can be relatively small. Therefore, in this embodiment, a plurality of the above-mentioned clock signal lines can be electrically connected to the same first pin 111, which helps to reduce the number of occupied first pins 111.

[0062] like Figure 4As shown, the connection relationship of the circuit structure in the amplitude modulation sub-circuit 031 is as follows: the input end of the first driving transistor T11 is electrically connected to the output end of the first voltage writing transistor T14, the output end of the first driving transistor T11 is electrically connected to the input end of the first modulation transistor T17, and the control end of the first driving transistor T11 is electrically connected to the output end of the first regulating transistor T13. The input end of the first data writing transistor T12 is electrically connected to the second data signal line Vdata2, the output end of the first data writing transistor T12 is electrically connected to the input end of the first driving transistor T11, and the control end of the first data writing transistor T12 is electrically connected to the sixth scanning line S6. The input end of the first regulating transistor T13 is electrically connected to the output end of the first driving transistor T11, and the control end of the first regulating transistor T13 is electrically connected to the sixth scanning line S6. The input end of the first voltage writing transistor T14 is electrically connected to the first power supply voltage signal line VDD1, the output end of the first voltage writing transistor T14 is electrically connected to the input end of the first driving transistor T11, and the control end of the first voltage writing transistor T14 is electrically connected to the third scanning line S3. The input end of the first voltage transmission transistor T15 is electrically connected to the output end of the first voltage writing transistor T14, the output end of the first voltage transmission transistor T15 is electrically connected to the first plate of the first capacitor C1, and the control end of the first voltage transmission transistor T15 is electrically connected to the third scan line S3. The second plate of the first capacitor C1 is electrically connected to the control end of the first driving transistor T11. The input end of the first reset transistor T16 is electrically connected to the fifth scan line S5, the output end of the first reset transistor T16 is electrically connected to the control end of the first driving transistor T11, and the control end of the first reset transistor T16 is electrically connected to the fifth scan line S5. The output end of the first modulation transistor T17 is electrically connected to the input end of the first output transistor T18, and the control end of the first modulation transistor T17 is electrically connected to the output end of the second reset transistor T19. The output end of the first output transistor T18 is electrically connected to the first pole of the light emitting device L, and the control end of the first output transistor T18 is electrically connected to the second scan line S2. The second pole of the light emitting device L is electrically connected to the third power supply voltage line VSS. The input end of the second reset transistor T19 is electrically connected to the reset signal line Vset, and the control end of the second reset transistor T19 is electrically connected to the fourth scan line S4. The input end of the second voltage transmission transistor T20 is electrically connected to the second power supply voltage signal line VDD2, the output end of the second voltage transmission transistor T20 is electrically connected to the first plate of the first capacitor C1, and the control end of the second voltage transmission transistor T20 is electrically connected to the fifth scan line S5. The input end of the third voltage transmission transistor T10 is electrically connected to the second power supply voltage signal line VDD2, the output end of the third voltage transmission transistor T10 is electrically connected to the first plate of the first capacitor C1, and the control end of the third voltage transmission transistor T10 is electrically connected to the sixth scan line S6.In addition, the amplitude modulation subcircuit 031 further includes a third capacitor C3, a first plate of the third capacitor C3 is electrically connected to the reset signal line Vset, and a second plate of the third capacitor C3 is electrically connected to the control end of the first modulation transistor T17.

[0063] like Figure 4 As shown, the connection relationship of the circuit structure in the pulse width modulation sub-circuit 032 is as follows: The input end of the second driving transistor T21 is electrically connected to the output end of the second voltage writing transistor T24, the output end of the second driving transistor T21 is electrically connected to the input end of the second output transistor T27, and the control end of the second driving transistor T21 is electrically connected to the output end of the second regulating transistor T23. The input end of the second data writing transistor T22 is electrically connected to the first data signal line Vdata1, the output end of the second data writing transistor T22 is electrically connected to the input end of the second driving transistor T21, and the control end of the second data writing transistor T22 is electrically connected to the sixth scanning line S6. The input end of the second regulating transistor T23 is electrically connected to the output end of the second driving transistor T21, and the control end of the second regulating transistor T23 is electrically connected to the sixth scanning line S6. The input end of the second voltage writing transistor T24 is electrically connected to the second power supply voltage signal line VDD2, the output end of the second voltage writing transistor T24 is electrically connected to the input end of the second driving transistor T21, and the control end of the second voltage writing transistor T24 is electrically connected to the third scanning line S3. The input end of the second voltage transmission transistor T25 is electrically connected to the first high level voltage signal line VGH1, the output end of the second voltage transmission transistor T25 is electrically connected to the first electrode plate of the second capacitor C2, and the control end of the second voltage transmission transistor T25 is electrically connected to the sixth scan line S6. The input end and the control end of the third reset transistor T26 are both electrically connected to the fifth scan line S5, and the output end of the third reset transistor T26 is electrically connected to the control end of the second driving transistor T21. The output end of the second output transistor T27 is electrically connected to the control end of the first modulation transistor T17, and the control end of the second output transistor T27 is electrically connected to the third scan line S3.

[0064] like Figure 5 As shown, the connection relationship of the circuit structure in the first gate driving circuit 061 and the connection relationship of the circuit structure in the second gate driving circuit 062 are as follows: The input end of the first upper output transistor T31 is electrically connected to the second high level voltage signal line VGH2, the output end of the first upper output transistor T31 is electrically connected to the first scan line S1 or the second scan line S2, and the control end of the first upper output transistor T31 is electrically connected to the output end of the third upper transistor T33. The input end of the second upper transistor T32 is electrically connected to the second high level voltage signal line VGH2, the output end of the second upper transistor T32 is electrically connected to the control end of the first upper output transistor T31, the control end of the second upper transistor T32 is electrically connected to the second plate of the fourth capacitor C4, and the first plate of the fourth capacitor C4 is electrically connected to the second positive clock signal line CK2. The input end of the third upper transistor T33 is electrically connected to the output end of the fourth upper transistor T34, and the control end of the third upper transistor T33 is electrically connected to the second positive clock signal line CK2. The input end of the fourth upper transistor T34 is electrically connected to the second positive clock signal line CK2, the output end of the fourth upper transistor T34 is also electrically connected to the second plate of the sixth capacitor C6, and the control end of the fourth upper transistor T34 is electrically connected to the output end of the fifth lower transistor T45. The first plate of the sixth capacitor C6 is electrically connected to the output end of the fifth lower transistor T45. The input end of the fifth upper transistor T35 is electrically connected to the output end of the sixth upper transistor T36, the output end of the fifth upper transistor T35 is electrically connected to the control end of the third lower transistor T43, and the control end of the fifth upper transistor T35 is electrically connected to the second positive clock signal line CK2. The input end of the sixth upper transistor T36 is electrically connected to the second high level voltage signal line VGH2, and the control end of the sixth upper transistor T36 is electrically connected to the output end of the fifth lower transistor T45. The input end of the seventh upper transistor T37 is electrically connected to the second high level voltage signal line VGH2, the output end of the seventh upper transistor T37 is electrically connected to the control end of the first lower output transistor T41, the control end of the seventh upper transistor T37 is electrically connected to the second plate of the fifth capacitor C5, and the first plate of the fifth capacitor C5 is electrically connected to the second high level voltage signal line VGH2. The input end of the eighth upper transistor T38 is electrically connected to the second high level voltage signal line VGH2, the output end of the eighth upper transistor T38 is electrically connected to the control end of the third lower transistor T43, and the control end of the eighth upper transistor T38 is electrically connected to the output end of the second upper transistor T32. The input end of the ninth upper transistor T39 is electrically connected to the third high level voltage signal line VGH3, the output end of the ninth upper transistor T39 is electrically connected to the control end of the eighth upper transistor T38, the control end of the seventh upper transistor T37, and the control end of the first upper output transistor T31, and the control end of the ninth upper transistor T39 is electrically connected to the first control line L01.

[0065] In addition, the input end of the first lower transistor T41 is electrically connected to the first positive clock signal line CK1, and the output end of the first lower transistor T41 is electrically connected to the first scan line S1 or the second scan line S2. The input end of the second lower transistor T42 is electrically connected to the first low-level voltage signal line VGL1, the output end of the second lower transistor T42 is electrically connected to the control end of the first lower transistor T41, and the control end of the second lower transistor T42 is electrically connected to the output end of the third lower transistor T43. The input end of the third lower transistor T43 is electrically connected to the first low-level voltage signal line VGL1, and the control end of the third lower transistor T43 is electrically connected to the output end of the fifth upper transistor T35. The input end of the fourth lower transistor T44 is electrically connected to the first reverse clock signal line CKB1, the output end of the fourth lower transistor T44 is electrically connected to the control end of the fourth upper transistor T34, the control end of the sixth upper transistor T36 and the first plate of the sixth capacitor C6, and the control end of the fourth lower transistor T44 is electrically connected to the output end of the fifth upper transistor T35. The input terminal of the fifth lower transistor T45 is electrically connected to the first low level voltage signal line VGL1, the output terminal of the fifth lower transistor T45 is electrically connected to the control terminal of the fourth upper transistor T34, and the control terminal of the fifth lower transistor T45 is electrically connected to the first counter clock signal line CKB1. The input terminal of the sixth lower transistor T46 is electrically connected to the first upper drive line A(n-1), the output terminal of the sixth lower transistor T46 is electrically connected to the input terminal of the seventh lower transistor T47, and the control terminal of the sixth lower transistor T46 is electrically connected to the first counter clock signal line CKB1. The above-mentioned first upper drive line A(n-1) can transmit the electrical signal output by the n-1th gate drive circuit cascaded with the first gate drive circuit 061, the first gate drive circuit 061 can be the nth gate drive circuit, and the first lower drive line A(n+1) can transmit the electrical signal output by the n+1th gate drive circuit cascaded with the first gate drive circuit 061. The output terminal of the seventh lower transistor T47 is electrically connected to the control terminal of the second upper transistor T32, and the control terminal of the seventh lower transistor T47 is electrically connected to the first signal line L1. The input terminal of the eighth lower transistor T48 is electrically connected to the output terminal of the ninth lower transistor T49, the output terminal of the eighth lower transistor T48 is electrically connected to the control terminal of the third lower transistor T43, and the control terminal of the eighth lower transistor T48 is electrically connected to the second signal line L2. The input terminal of the ninth lower transistor T49 is electrically connected to the first lower-level driving line A(n+1), and the control terminal of the ninth lower transistor T49 is electrically connected to the first counter-clock signal line CKB1.

[0066] like Figure 6 As shown, the connection relationship of the circuit structure in the third gate driving circuit 063 is as follows: The input end of the first output transistor T51 is electrically connected to the fourth high level voltage signal line VGH4, the output end of the first output transistor T51 is electrically connected to the third scan line S3, and the control end of the first output transistor T51 is electrically connected to the output end of the second transistor T52. The input end of the second transistor T52 is electrically connected to the fourth high level voltage signal line VGH4, and the control end of the second transistor T52 is electrically connected to the third positive clock signal line CK3. The input end of the third transistor T53 is electrically connected to the output end of the fourth transistor T54, and the control end of the third transistor T53 is electrically connected to the third positive clock signal line CK3. The input end of the fourth transistor T54 is electrically connected to the third positive clock signal line CK3, and the output end of the fourth transistor T54 is also electrically connected to the second plate of the eighth capacitor C8, and the control end of the fourth transistor T54 is electrically connected to the output end of the second transistor T62. The first plate of the eighth capacitor C8 is electrically connected to the output end of the second transistor T62. The input end of the fifth transistor T55 is electrically connected to the output end of the sixth transistor T56, the output end of the fifth transistor T55 is electrically connected to the control end of the first output transistor T61, and the control end of the fifth transistor T55 is electrically connected to the third positive clock signal line CK3. The input end of the sixth transistor T56 is electrically connected to the fourth high level voltage signal line VGH4, and the control end of the sixth transistor T56 is electrically connected to the output end of the second transistor T62. The input end of the seventh transistor T57 is electrically connected to the fifth high level voltage signal line VGH5, the output end of the seventh transistor T57 is electrically connected to the control end of the first output transistor T51, and the control end of the seventh transistor T57 is electrically connected to the second control line L02.

[0067] In addition, the input end of the first down-down output transistor T61 is electrically connected to the second low-level voltage signal line VGL2, and the output end of the first down-down output transistor T61 is electrically connected to the third scan line S3. The input end of the second down-down transistor T62 is electrically connected to the second low-level voltage signal line VGL2, and the control end of the second down-down transistor T62 is electrically connected to the second counter-clock signal line CKB2. The input end of the third down-down transistor T63 is electrically connected to the second counter-clock signal line CKB2, the output end of the third down-down transistor T63 is electrically connected to the control end of the fourth up-up transistor T54, and the control end of the third down-down transistor T63 is electrically connected to the output end of the fifth up-up transistor T55. The input end of the fourth down-down transistor T64 is electrically connected to the output end of the fifth down-down transistor T65, the output end of the fourth down-down transistor T64 is electrically connected to the control end of the first down-down output transistor T61 and the control end of the second up-up transistor T52, and the control end of the fourth down-down transistor T64 is electrically connected to the third signal line L3. The input end of the fifth lower transistor T65 is electrically connected to the second upper drive line W(n-1), and the control end of the fifth lower transistor T65 is electrically connected to the second counter clock signal line CKB2. The above-mentioned second upper drive line W(n-1) can transmit the electrical signal output by the n-1th gate drive circuit cascaded with the third gate drive circuit 063, the third gate drive circuit 063 can be the nth gate drive circuit, and the second lower drive line W(n+1) can transmit the electrical signal output by the n+1th gate drive circuit cascaded with the third gate drive circuit 063. The input end of the sixth lower transistor T66 is electrically connected to the output end of the seventh lower transistor T67, the output end of the sixth lower transistor T66 is electrically connected to the input end of the first lower output transistor T61, and the control end of the sixth lower transistor T66 is electrically connected to the fourth signal line L4. An input terminal of the seventh lower transistor T67 is electrically connected to the second lower driving line W(n+1), and a control terminal of the seventh lower transistor T67 is electrically connected to the second counter-clock signal line CKB2.

[0068] like Figure 7 As shown, the connection relationship of the circuit structures in the fourth gate driving circuit 064 and the fifth gate driving circuit 065 is as follows: The input end of the first output transistor T71 is electrically connected to the sixth high-level voltage signal line VGH6, the output end of the first output transistor T71 is electrically connected to the fourth scan line S4 or the fifth scan line S5 or the sixth scan line S6, and the control end of the first output transistor T71 is electrically connected to the output end of the fourth transistor T74. The input end of the second transistor T72 is electrically connected to the sixth high-level voltage signal line VGH6, the output end of the second transistor T72 is electrically connected to the input end of the third transistor T73, and the control end of the second transistor T72 is electrically connected to the output end of the fourth transistor T74. The output end of the third transistor T73 is electrically connected to the input end of the second transistor T82, and the control end of the third transistor T73 is electrically connected to the fourth positive clock signal line CK4. An input terminal of the fourth up-up-up transistor T74 is electrically connected to the third counter-clock signal line CKB3 , and a control terminal of the fourth up-up-up transistor T74 is electrically connected to an output terminal of the sixth down-down-down transistor T86 .

[0069] In addition, the input end of the first down-down-down output transistor T81 is electrically connected to the fifth positive clock signal line CK5, the output end of the first down-down-down output transistor T81 is electrically connected to the fourth scan line S4 or the fifth scan line S5 or the sixth scan line S6, and the control end of the first down-down-down output transistor T81 is electrically connected to the output end of the second down-down-down transistor T82. The control end of the second down-down-down transistor T82 is electrically connected to the third low-level voltage signal line VGL3. The input end of the third down-down-down transistor T83 is electrically connected to the third low-level voltage signal line VGL3, the output end of the third down-down-down transistor T83 is electrically connected to the control end of the second up-up-up transistor T72, and the control end of the third down-down-down transistor T83 is electrically connected to the third counter-clock signal line CKB3. The input end of the fourth lower-lower-lower transistor T84 is electrically connected to the third upper drive line S(n-1), the output end of the fourth lower-lower-lower transistor T84 is electrically connected to the input end of the fifth lower-lower-lower transistor T85, and the control end of the fourth lower-lower-lower transistor T84 is electrically connected to the third counter-clock signal line CKB3. The third upper drive line S(n-1) can transmit the electrical signal output by the n-1th level gate drive circuit cascaded with the fourth gate drive circuit 064, the fourth gate drive circuit 064 can be the nth level gate drive circuit, and the third lower drive line S(n+1) can transmit the electrical signal output by the n+1th level gate drive circuit cascaded with the fourth gate drive circuit 064. The output end of the fifth lower-lower-lower transistor T85 is electrically connected to the control end of the fourth upper-upper transistor T74, and the control end of the fifth lower-lower-lower transistor T85 is electrically connected to the sixth signal line L6. An input terminal of the sixth lower-lower-lower transistor T86 is electrically connected to the third lower-stage driving line S(n+1), and a control terminal of the sixth lower-lower-lower transistor T86 is electrically connected to the fifth signal line L5.

[0070] Figure 8 This is a schematic diagram of a partial structure of a display module provided in this application. For ease of understanding, Figure 8 Only the connection relationship between some structures on the display panel and between some structures on the display panel and the pins of the circuit board is shown, and the specific structure of each circuit structure is not shown in detail.

[0071] In one embodiment of the present application, Figure 8 As shown, the driving circuit 02 further includes a third driving circuit 023. The scanning signal output by the third driving circuit 023 can participate in the data writing process of the pixel circuit 03. To ensure the normal progress of the data writing process, the timing accuracy of the scanning signal output by the third driving circuit 023 needs to be expected, that is, the corresponding up and down edge durations of the scanning signal when the potential changes need to be less than the threshold.

[0072] The signal line 04 also includes a third signal line 043, which provides a clock signal for the third driving circuit 023, and the third signal line 043 and the first signal line 041 are signal lines 04 that transmit the same functional signal. The electrical signal transmitted by the third signal line 043 can participate in the process of the third driving circuit 023 generating a scanning signal. It should be noted that the duration of the upper and lower edges of the electrical signal transmitted by the third signal line 043 can affect the duration of the upper and lower edges of the scanning signal generated by the third driving circuit 023.

[0073] The third signal line 043 and the first signal line 041 are electrically connected to different first pins 111 respectively.

[0074] In the embodiment of the present application, although the third signal line 043 and the first signal line 041 are signal lines 04 that transmit the same functional signal, in order to avoid the increase of the up and down edge duration of the electrical signal transmitted by the third signal line 043, it is necessary to set the third signal line 043 and the first signal line 041 to be electrically connected to different first pins 111 respectively. The reason is that if the third signal line 043, the first signal line 041, and the second signal line 042 are electrically connected to the same first pin 111, the electrical signal transmitted by the first pin 111 is supplied to the above three signal lines at the same time. Compared with the case where the electrical signal is only supplied to one signal line, in this case, the timing accuracy of the electrical signal transmitted by the first pin 111 is lower, and the corresponding up and down edge duration is longer. Therefore, in this embodiment, by setting the third signal line 043 and the first signal line 041 to be electrically connected to different first pins 111 respectively, it is helpful to ensure that the timing accuracy of the third signal line 043 reaches the expected level and avoid adverse effects on the data writing process of the pixel circuit 03.

[0075] In one embodiment of the present application, Figure 4As shown, the pixel circuit 03 includes an amplitude modulation sub-circuit 031 and a pulse width modulation sub-circuit 032 .

[0076] The display panel 10 further includes a sixth gate driving circuit 066, such as Figure 7 As shown, the circuit structure of the sixth gate driving circuit 066 may be the same as the circuit structure of the fifth gate driving circuit 065 and the fourth gate driving circuit 054 .

[0077] Combination Figure 4 and Figure 7 The electric signal output by the sixth gate driving circuit 066 controls the data signal to be written into the amplitude modulation sub-circuit 031 and the pulse width modulation sub-circuit 032. The output end of the sixth gate driving circuit 066 can be electrically connected to the control end of the first data writing transistor T12, the control end of the first regulating transistor T13, the control end of the second data writing transistor T22, and the control end of the second regulating transistor T23 through the sixth scanning line S6.

[0078] The third driving circuit 023 is the sixth gate driving circuit 066 .

[0079] In the embodiment of the present application, the third signal line 043 providing the electrical signal to the third driving circuit 023 can be connected to the first pin 111 in a one-to-one correspondence, so as to avoid the third signal line 043 and other signal lines 02 corresponding to the same first pin 111, thereby preventing the third signal line 043 and other signal lines 02 from corresponding to the same first pin 111, thereby reducing the timing accuracy of the electrical signal transmitted by the third signal line 043. The arrangement of this embodiment helps to reduce the impact on the data writing process of the pixel circuit 03 while saving the number of first pins 111.

[0080] Fig. 9 A schematic diagram of a partial structure of a display module provided in the present application.

[0081] In one embodiment of the present application, Fig. 9 As shown, the circuit board 11 also includes a second pin 112, and the connection pad 05 is correspondingly connected to the second pin 112. At this time, the circuit board 11 can be a flexible circuit board, and the circuit board 11 can include a receiving side 11a and an output side 11b. The first pin 111 can be located in an area close to the receiving side 11a on the circuit board 11, and the second pin 112 can be located in an area close to the output side 11b on the circuit board 11. The first pin 111 can be used to receive an electrical signal, and can transmit the received electrical signal to the second pin 112, and the second pin 112 can transmit the electrical signal received from the first pin 111 to the connection pad 05.

[0082] The connection pad 05 may include a first pad 051, the first signal line 041 and the second signal line 042 are both electrically connected to the first pad 051, and the second pin 112 connected to the first pad 051 is correspondingly connected to the first pin 111. Therefore, the first signal line 041 and the second signal line 042 may receive an electrical signal through the same second pin 112, and the connection between the first signal line 041, the second signal line 042 and the corresponding second pin 112 may constitute the above-mentioned branch line connection method, and the branch line connection method is located on the display panel 10.

[0083] The arrangement of the embodiment of the present application enables different signal lines 04 (first signal line 041 and second signal line 042) to receive electrical signals through the same first pad 051, thereby reducing the number of required first pads 051. Since the first pad 051 and the second pin 112 can be connected correspondingly, the arrangement of the embodiment helps to reduce the number of occupied second pins 112 on the circuit board 11, which is conducive to the rationalization of the connection method.

[0084] In one embodiment of the present application, the first signal line 041 and the second signal line 042 are both high-level voltage signal lines or low-level voltage signal lines.

[0085] In the above-mentioned branch line connection mode, the transmission process of the electrical signal on the first signal line 041 and the second signal line 042 is easily interfered by the outside world. Considering that the branch line setting mode is located on the display panel 10 with a relatively complex film layer structure, the preferred type of the electrical signal transmitted by the first signal line 041 and the second signal line 042 can be a constant voltage electrical signal, such as a high-level voltage signal or a low-level voltage signal. Therefore, the setting mode of the present application can reduce the degree of external interference of the electrical signal during transmission while reducing the number of occupied pins on the circuit board 11.

[0086] For example, see Figure 5 The first signal line 041 and the second signal line 042 may be a first low level voltage signal line VGL1 connected to the first gate driving circuit 061 and a first low level voltage signal line VGL1 connected to the second gate driving circuit 062 , respectively.

[0087] For example, see Figure 7 The first signal line 041 and the second signal line 042 may be the sixth high level voltage signal line VGH6 connected to the fourth gate driving circuit 064 and the sixth high level voltage signal line VGH6 connected to the fifth gate driving circuit 065 , respectively.

[0088] In one embodiment of the present application, the first signal line 041 and the second signal line 042 are both low-level voltage signal lines.

[0089] The pixel circuit 03 includes an amplitude modulation sub-circuit 031 and a pulse width modulation sub-circuit 032 .

[0090] The display panel 10 also includes a first gate driving circuit 061 and a second gate driving circuit 062. The electrical signal output by the first gate driving circuit 061 adjusts the gate potential of the second driving transistor T21 in the pulse width modulation subcircuit 032; the electrical signal output by the second gate driving circuit 062 controls the amplitude modulation circuit 031 to output a light-emitting driving current.

[0091] The first driving circuit 021 and the second driving circuit 022 are two of the fourth gate driving circuit 064 , the fifth gate driving circuit 065 , and the sixth gate driving circuit 066 , respectively.

[0092] For example, see Figure 7 The first signal line 041 and the second signal line 042 may be any two of the third low-level voltage signal lines VGL3 to which the fourth gate driving circuit 064 , the fifth gate driving circuit 065 , and the sixth gate driving circuit 066 are respectively connected.

[0093] In the embodiment of the present application, since the first driving circuit 021 and the second driving circuit 022 may not directly output the electrical signal transmitted by the third low-level voltage signal line VGL3, the third low-level voltage signal line VGL3 connected to the first driving circuit 021 and the third low-level voltage signal line VGL3 connected to the second driving circuit 022 may correspond to the same first pin 111, which helps to reduce the number of occupied first pins 111.

[0094] Fig.10 This is a schematic diagram of a partial structure of a portion of the gate drive circuit group provided in this application. For ease of understanding, Fig.10 The figure only abstractly illustrates the connection relationship between each gate driving circuit and some signal lines in the gate driving circuit group.

[0095] In one embodiment of the present application, the display panel 10 may include a first gate driving circuit group 0601 and a second gate driving circuit group 0602, the first gate driving circuit group 0601 includes a plurality of cascaded first gate driving circuits 061, and the second gate driving circuit group 0602 includes a plurality of cascaded second gate driving circuits 062.

[0096] At this time, the first signal line 041 can transmit a start signal to the first-stage first gate driving circuit 061 in the first gate driving circuit group 0601; the second signal line 042 can transmit a start signal to the first-stage second gate driving circuit 062 in the second gate driving circuit group 0602. When the first-stage first (second) gate driving circuit 061 (062) receives the above start signal, the first-stage first (second) gate driving circuit 061 (062) starts to enter the working state, and then outputs an electrical signal to the next-stage gate driving circuit.

[0097] Combination Figure 2 and Fig.10 The first signal line 041 and the second signal line 042 correspond to the same first pin 111 .

[0098] In the embodiment of the present application, both the first signal line 041 and the second signal line 042 can transmit the start signal, and the electrical signals transmitted by the two respectively have the same function; in addition, referring to Figure 5 It can be seen that the first gate driving circuit 061 and the second gate driving circuit 062 can have the same circuit structure, and the start-up signals transmitted by the first signal line 041 and the second signal line 042 can be the same. Therefore, the same first pin 111 can be used to transmit the above start-up signal to the first signal line 041 and the second signal line 042, respectively, which helps to reduce the number of occupied first pins 111.

[0099] In one embodiment of the present application, the pixel circuit 03 includes an amplitude modulation subcircuit 031 and a pulse width modulation subcircuit 032 .

[0100] The display panel 10 further includes a fourth gate driving circuit 064, a fifth gate driving circuit 065 and a sixth gate driving circuit 066. The fourth gate driving circuit 064 controls the first reset signal to be written into the amplitude modulation subcircuit 031; the fifth gate driving circuit 065 controls the second reset signal to be written into the amplitude modulation subcircuit 031 and the pulse width modulation subcircuit 032; and the sixth gate driving circuit 066 controls the data signal to be written into the amplitude modulation subcircuit 031 and the pulse width modulation subcircuit 032.

[0101] The first driving circuit 021 and the second driving circuit 022 are two of the fourth gate driving circuit 064 , the fifth gate driving circuit 065 , and the sixth gate driving circuit 066 , respectively.

[0102] For example, the first driving circuit 021 and the second driving circuit 022 may be the fourth gate driving circuit 064 and the fifth gate driving circuit 065 respectively.

[0103] For example, the first driving circuit 021 and the second driving circuit 022 may be the fourth gate driving circuit 064 and the sixth gate driving circuit 066 respectively.

[0104] For example, the first driving circuit 021 and the second driving circuit 022 may be the fifth gate driving circuit 065 and the sixth gate driving circuit 066 respectively.

[0105] In the embodiment of the present application, the first driving circuit 021 and the second driving circuit 022 can be two of the fourth gate driving circuit 064, the fifth gate driving circuit 065, and the sixth gate driving circuit 066, which means that some signal lines 04 (for example, the sixth high-level voltage signal line VGH6 or the third low-level voltage signal line VGL3) respectively connected to the fourth gate driving circuit 064, the fifth gate driving circuit 065, and the sixth gate driving circuit 066 can correspond to the same first pin 111, which helps to rationalize the connection relationship between the structures in the display module 20.

[0106] Fig.11 A schematic diagram of a partial structure of a display module provided in the present application.

[0107] In one embodiment of the present application, Fig.11 As shown, the driving circuit 02 further includes a fourth driving circuit 024 , and the circuit structure of the fourth driving circuit 024 may be different from the circuit structure of the first driving circuit 021 and the circuit structure of the second driving circuit 022 .

[0108] The signal line 04 also includes a fourth signal line 044, which provides a high-level voltage signal or a low-level voltage signal to the fourth driving circuit 024, and the fourth signal line 044 and the first signal line 041 are signal lines that transmit the same functional signal. It should be noted that the output end of the first driving circuit 021 will not directly output the electrical signal provided by the first signal line 041, while the fourth driving circuit 024 can directly output the electrical signal provided by the fourth signal line 044.

[0109] The fourth signal line 044 and the first signal line 041 are connected to different first pins 111 respectively.

[0110] In the embodiment of the present application, since the fourth driving circuit 024 can directly output the electric signal provided by the fourth signal line 044, the load of the fourth signal line 044 is larger than that of the first signal line 041. For the signal line 04 with a larger load, in order to make the voltage of the electric signal provided by the signal line 04 meet the working requirements of the circuit structure connected to the signal line 04, the signal line 04 can be set to be connected to the first pin 111 in a one-to-one correspondence. The setting method of this embodiment can ensure that the electric signal transmitted by the fourth signal line 044 meets the requirements, and avoid the voltage of the electric signal transmitted by the fourth signal line 044 being unable to meet the requirements of the pixel circuit 03 due to being connected to the same first pin 111 as the first signal line 041.

[0111] In one embodiment of the present application, Figure 4 , Figure 6 and Fig.11 The pixel circuit 03 includes an amplitude modulation sub-circuit 031 and a pulse width modulation sub-circuit 032.

[0112] The display panel 10 further includes a third gate driving circuit 063 , and the electrical signal output by the third gate driving circuit 063 controls the power supply voltage signal to be written into the pulse width modulation sub-circuit 032 .

[0113] The fourth driving circuit 024 is the third gate driving circuit 063 .

[0114] Please refer to Figure 6 , the fourth signal line 044 may correspond to the fourth high level voltage signal line VGH4, and when the first upper output transistor T51 is turned on, the electrical signal transmitted by the fourth signal line 044 may be transmitted to the pixel circuit 03 through the third signal line S3. The fourth signal line 044 may also correspond to the second low level voltage signal line VGL2, and when the first lower output transistor T61 is turned on, the electrical signal transmitted by the fourth signal line 044 may be transmitted to the pixel circuit 03 through the third signal line S3.

[0115] In the embodiment of the present application, the electrical signal transmitted by the fourth signal line 044 can be directly output by the fourth driving circuit 024. In order to avoid the situation where the electrical signal output by the fourth driving circuit 024 cannot meet the working requirements of the pixel circuit 03, the fourth high-level voltage signal line VGH4 or the second low-level voltage signal line VGL2 can be set to correspond to different first pins 111 of the first signal line 041 respectively.

[0116] Fig.12 This is a schematic diagram showing the change in the potential of the electrical signal transmitted by the first type of signal line during a working cycle of the driving circuit.

[0117] In one embodiment of the present application, Fig. 9 and Fig.12 The first signal line 041 and the second signal line 042 are both first-type signal lines X. The first-type signal line X transmits a high-level voltage signal in the first period T1 and the high-level voltage signal maintains a constant potential in the first period T1. The electrical signal transmitted by the first-type signal line X becomes a low-level voltage signal in the second period T2.

[0118] In one working cycle T of the driving circuit 02 , the duration of the first time period T1 is greater than the duration of the second time period T2 .

[0119] In the embodiment of the present application, the electrical signal transmitted by the first type of signal line X is a non-constant potential signal. However, in a working cycle T of the driving circuit 02, the electrical signal transmitted by the first type of signal line X maintains a constant potential (corresponding to being at a high level potential) for a long time. Therefore, compared with other non-constant potential signals (such as clock signals), the electrical signal transmitted by the first type of signal line X has a stronger ability to resist external interference. At this time, the first signal line 041 and the second signal line 042 belonging to the first type of signal line X can be set to be connected to the same first pad 051, that is, the first signal line 041, the second signal line 042 and the first pad 051 on the display panel 10 constitute the above-mentioned branch line connection mode. Under the premise of considering the ability of the first type of signal line to resist external interference, the number of occupied first pins 111 is reduced as much as possible.

[0120] In one embodiment of the present application, Figure 4 As shown, the pixel circuit 03 includes an amplitude modulation sub-circuit 031 and a pulse width modulation sub-circuit 032 .

[0121] Combination Figure 5 and Figure 6 The display panel 10 further includes a first gate driving circuit 061, a second gate driving circuit 062 and a third gate driving circuit 063. The electrical signal output by the first gate driving circuit 061 adjusts the gate potential of the second driving transistor T21 in the pulse width modulation sub-circuit 032. The electrical signal output by the second gate driving circuit 062 controls the amplitude modulation circuit 031 to output the light-emitting driving current. The electrical signal output by the third gate driving circuit 063 controls the power supply voltage signal to be written into the pulse width modulation sub-circuit 032.

[0122] The first driving circuit 021 and the second driving circuit 022 are two of the first gate driving circuit 061 , the second gate driving circuit 062 , and the third gate driving circuit 063 , respectively.

[0123] For example, the first drive circuit 021 can be a first gate drive circuit 061, and the first signal line 041 can be a first control line L01 electrically connected to the ninth upper transistor T39 in the first gate drive circuit 061; the second drive circuit 022 can be a second gate drive circuit 062, and the second signal line 042 can be a first control line L01 electrically connected to the ninth upper transistor T39 in the second gate drive circuit 062.

[0124] For example, the first drive circuit 021 can be a first gate drive circuit 061, and the first signal line 041 can be a first control line L01 electrically connected to the ninth upper transistor T39 in the first gate drive circuit 061; the second drive circuit 022 can be a third gate drive circuit 063, and the second signal line 042 can be a second control line L02 electrically connected to the seventh upper transistor T57 in the third gate drive circuit 063.

[0125] In the embodiment of the present application, for the electrical signals respectively transmitted by the first control line L01 and the second control line L02, in one working cycle of the driving circuit, the duration corresponding to the constant potential of the electrical signal is greater than the duration corresponding to the change in potential, then relative to other non-constant potential electrical signals (such as clock signals), the electrical signals respectively transmitted by the first control line L01 and the second control line L02 have stronger anti-interference capabilities. Therefore, in this embodiment, the first control line L01 and the second control line L02 can be set to be connected to the same first pin 111, and the first control lines L01 corresponding to different driving circuits can be connected to the same first pin 111, and the corresponding above-mentioned branch line connection method can be implemented on the display panel 10, which helps to reduce the number of first pins 111 occupied by the first control line L01 and the second control line L02 while ensuring the quality of the electrical signals transmitted by the first control line L01 and the second control line L02.

[0126] Fig.13 A schematic diagram of a partial structure of a display panel provided in the present application, Fig.14 for Fig.13 The bottom view of the partial structure of the display panel shown in the figure is for easy understanding. Fig.14 Only Fig.13 The partial structure of the display panel located on the second surface is shown.

[0127] In one embodiment of the present application, Fig.13 and Fig.14 The base substrate 01 includes a first surface 01a and a second surface 01b opposite to each other and a third surface 01c connecting the first surface 01a and the second surface 01b.

[0128] The signal line 04 includes a first portion 04a located on the first surface 01a and a second portion 04b located on the second surface 01b. The first portion 04a is electrically connected to the second portion 04b via a side trace 04c located on the third surface 01c. The side trace 04c is electrically connected to the first portion 01a and the second portion 04b via a transfer pad m. In addition, the drive circuit 02 can receive the required electrical signal via the first portion 04a, and the second portion 04b can receive the electrical signal provided by the circuit board 11 via the connecting pad 05.

[0129] The first signal line 041 and the second signal line 042 correspond to different side routing lines 04c respectively, and the first signal line 041 and the second signal line 042 can be electrically connected to different side routing lines 04c through different transfer pads m respectively.

[0130] Fig.15 A schematic diagram of a display device provided in the present application.

[0131] The present application provides a display device 30, such as Fig.15 As shown, the display device 30 includes the above-mentioned display module 20. The display device 30 can be a mobile phone, in addition, the display device 30 can also be an electronic device such as a computer, a television, etc.

[0132] The rationality of the connection relationship between the display panel 10 and the circuit board 11 in the display device 30 provided in the embodiment of the present application is greatly improved.

[0133] In this specification, the same or similar parts between the various embodiments can be referred to each other. In particular, for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

Claims

1. A display module, characterized in that: The device comprises a display panel and a circuit board, wherein the circuit board is electrically connected to the display panel; the display panel comprises: substrate substrate; A driving circuit and a pixel circuit, wherein the driving circuit and the pixel circuit are located on the substrate, and the driving circuit provides a control signal for the pixel circuit; A signal line, wherein the signal line provides a signal to the driving circuit; The driving circuit includes a first driving circuit and a second driving circuit; a signal line group, the signal line group comprising a first signal line group and a second signal line group, the first signal line group comprising M signal lines providing signals to the first drive circuit, the second signal line group comprising N signal lines providing signals to the second drive circuit, M ≥ 1, N ≥ 1; The display panel further comprises a plurality of connection pads; the circuit board comprises a plurality of first pins, and the first pins are connected to the signal lines through the connection pads; The first signal line among the M signal lines and the second signal line among the N signal lines are signal lines that transmit signals with the same function; the first signal line and the second signal line are both electrically connected to the same first pin.

2. The display module according to claim 1, characterized in that: The circuit board also includes a second pin, and the connecting pad is correspondingly connected to the second pin; The connecting pad includes a first pad and a second pad, the first pad is electrically connected to the first signal line, and the second pad is electrically connected to the second signal line; The second pin corresponding to the first pad and the second pin corresponding to the second pad are electrically connected to the same first pin.

3. The display module according to claim 2, characterized in that: The first signal line and the second signal line are both clock signal lines.

4. The display module according to claim 3, characterized in that: The pixel circuit includes an amplitude modulation subcircuit and a pulse width modulation subcircuit; The display panel further includes a first gate driving circuit, a second gate driving circuit and a third gate driving circuit; the electric signal output by the first gate driving circuit adjusts the gate potential of the second driving transistor in the pulse width modulation subcircuit; the electric signal output by the second gate driving circuit controls the amplitude modulation subcircuit to output a light-emitting driving current; the electric signal output by the third gate driving circuit controls the power supply voltage signal to be written into the pulse width modulation subcircuit; the first driving circuit and the second driving circuit are respectively two of the first gate driving circuit, the second gate driving circuit and the third gate driving circuit; Alternatively, the display panel further includes a fourth gate driving circuit and a fifth gate driving circuit, and the electrical signal output by the fourth gate driving circuit controls the first reset signal to be written into the amplitude modulation sub-circuit; The fifth gate driving circuit controls the second reset signal to be written into the amplitude modulation sub-circuit and the pulse width modulation sub-circuit; the first driving circuit and the second driving circuit are the fourth gate driving circuit and the fifth gate driving circuit respectively.

5. The display module according to claim 3, characterized in that: The driving circuit further includes a third driving circuit; The signal line further includes a third signal line, the third signal line provides a clock signal for the third driving circuit, and the third signal line and the first signal line are signal lines that transmit signals of the same function; The third signal line and the first signal line are electrically connected to different first pins respectively.

6. The display module according to claim 5, characterized in that: The pixel circuit includes an amplitude modulation subcircuit and a pulse width modulation subcircuit; The display panel further comprises a sixth gate driving circuit, wherein the electrical signal output by the sixth gate driving circuit controls the data signal to be written into the amplitude modulation sub-circuit and the pulse width modulation sub-circuit; Wherein, the third driving circuit is the sixth gate driving circuit.

7. The display module according to claim 1, characterized in that: The circuit board also includes a second pin, and the connecting pad is correspondingly connected to the second pin; The connecting pad includes a first pad, the first signal line and the second signal line are both electrically connected to the first pad, and the second pin connected to the first pad is correspondingly connected to the first pin.

8. The display module according to claim 7, characterized in that: The first signal line and the second signal line are both high-level voltage signal lines or low-level voltage signal lines.

9. The display module according to claim 8, characterized in that: The first signal line and the second signal line are both low level voltage signal lines; The pixel circuit includes an amplitude modulation subcircuit and a pulse width modulation subcircuit; The display panel further includes a first gate driving circuit and a second gate driving circuit; the electrical signal output by the first gate driving circuit adjusts the gate potential of the second driving transistor in the pulse width modulation subcircuit; the electrical signal output by the second gate driving circuit controls the amplitude modulation circuit to output a light-emitting driving current; The first driving circuit and the second driving circuit are respectively the first gate driving circuit and the second gate driving circuit.

10. The display module according to claim 8, characterized in that: The pixel circuit includes an amplitude modulation subcircuit and a pulse width modulation subcircuit; The display panel further includes a fourth gate driving circuit, a fifth gate driving circuit and a sixth gate driving circuit; the fourth gate driving circuit controls the first reset signal to be written into the amplitude modulation subcircuit; the fifth gate driving circuit controls the second reset signal to be written into the amplitude modulation subcircuit and the pulse width modulation subcircuit; the sixth gate driving circuit controls the data signal to be written into the amplitude modulation subcircuit and the pulse width modulation subcircuit; The first driving circuit and the second driving circuit are respectively two of the fourth gate driving circuit, the fifth gate driving circuit, and the sixth gate driving circuit.

11. The display module according to claim 8, characterized in that: The driving circuit further includes a fourth driving circuit; The signal line further includes a fourth signal line, the fourth signal line provides a high level voltage signal or a low level voltage signal for the fourth driving circuit, and the fourth signal line and the first signal line are signal lines that transmit signals with the same function; The fourth signal line and the first signal line are electrically connected to different first pins respectively.

12. The display module according to claim 11, characterized in that: The pixel circuit includes an amplitude modulation subcircuit and a pulse width modulation subcircuit; The display panel further comprises a third gate driving circuit, wherein the electrical signal output by the third gate driving circuit controls the power supply voltage signal to be written into the pulse width modulation sub-circuit; Wherein, the fourth driving circuit is the third gate driving circuit.

13. The display module according to claim 7, characterized in that: The first signal line and the second signal line are both first-type signal lines; the first-type signal line transmits a high-level voltage signal in a first period and the high-level voltage signal maintains a constant potential in the first period; the electrical signal transmitted by the first-type signal line becomes a low-level voltage signal in the second period; Wherein, in one working cycle of the driving circuit, the duration of the first time period is greater than the duration of the second time period.

14. The display module according to claim 13, characterized in that: The pixel circuit includes an amplitude modulation subcircuit and a pulse width modulation subcircuit; The display panel further comprises a first gate driving circuit, a second gate driving circuit and a third gate driving circuit; the electric signal output by the first gate driving circuit adjusts the gate potential of the second driving transistor in the pulse width modulation subcircuit; the electric signal output by the second gate driving circuit controls the amplitude modulation circuit to output a light-emitting driving current; the electric signal output by the third gate driving circuit controls the power supply voltage signal to be written into the pulse width modulation subcircuit; The first driving circuit and the second driving circuit are two of the first gate driving circuit, the second gate driving circuit, and the third gate driving circuit, respectively.

15. The display module according to claim 1, characterized in that: The substrate includes a first surface and a second surface opposite to each other and a third surface connecting the first surface and the second surface; The signal line includes a first portion located on the first surface and a second portion located on the second surface; the first portion is electrically connected to the second portion via a side wiring located on the third surface; the side wiring is electrically connected to the first portion and the second portion via a transfer pad; The first signal line and the second signal line correspond to different side routing lines respectively.

16. A display device, characterized in that: Comprising a display module as described in any one of claims 1-15.

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