Digital filter, audio coding and decoding chip and device

Abstract

The invention discloses a digital filter, an audio coding and decoding chip and an audio coding and decoding device, comprising a rate control device, an arithmetic device and a storage device, so that when the audio coding and decoding chip is in a coding or decoding working state, a coding or decoding control signal is output through the rate control device; and driving a plurality of signal processing units in the arithmetic device to perform multi-stage coding or decoding filtering processing on the audio signal according to the corresponding working time sequence, and storing the filtered audio signal by using a storage device according to the storage time sequence. According to the technical scheme, different functions are executed in the encoding process and the decoding process based on the multiple signal processing units in the arithmetic device, compared with an audio encoding and decoding scheme of the related technology, use of multipliers and adders in a multi-stage decimation filter and an interpolation filter is reduced, the overall circuit area is smaller, power consumption is lower, and the cost is lower. The method is suitable for low-power-consumption scenes and compact design.

Description

Technical Field

[0001] The present invention relates to the technical field of audio coding and decoding, and in particular to a digital filter, an audio coding and decoding chip and a device. Background Art

[0002] In modern multimedia technology, audio codec technology, as a key basic technology, is widely used in communications, music, movies and other fields. Its performance directly affects audio quality and user experience. From the early PCM (Pulse Code Modulation) and ADPCM (Adaptive Differential Pulse Code Modulation) technologies to the more advanced AAC (Advanced Audio Coding) and Opus technologies in recent years, audio codec technology has undergone significant development and iterative updates.

[0003] In the process of audio signal processing, filters, as an important component, play an irreplaceable role. Specifically, filters can improve the quality of audio signals in the following ways: Noise reduction: Filters can effectively remove noise from audio signals and improve the purity and clarity of signals. Spectral shaping: By adjusting the filter parameters, the spectral characteristics of the audio signal can be changed to achieve specific sound effect optimization. Dynamic range compression: Filters help adjust the dynamic range of audio signals to make them more balanced and suitable for different playback scenarios. Echo cancellation: In audio communications, filters can significantly eliminate echoes and reverberations, improving communication quality.

[0004] However, although most audio codecs and digital filters have made great progress in performance, there are still obvious deficiencies in practical applications. For example, the codec algorithms and filter devices in the relevant technologies are usually highly complex and have low computational efficiency, resulting in high system power consumption. This high power consumption characteristic and large circuit integration area limit its promotion and use in low-power scenarios such as mobile devices. In addition, when processing high-resolution audio, real-time performance and stability need to be further optimized. Summary of the invention

[0005] The main purpose of the present invention is to provide a digital filter, an audio codec chip and a device, aiming to at least solve the technical problems of large circuit integration area and large system power consumption in the related technology.

[0006] In a first aspect of the present invention, a digital filter is provided, which is applied to an audio codec chip, wherein the digital filter comprises a rate control device, a computing device and a storage device, wherein a first output end of the rate control device is electrically connected to an input end of the computing device, an output end of the computing device is electrically connected to a first input end of the storage device, and a second output end of the rate control device is electrically connected to a second input end of the storage device;

[0007] When the audio codec chip is in an audio coding working state, the rate control device is used to output a coding control signal according to a preset first oversampling ratio, the multiple signal processing units in the computing device are used to start according to the coding control signal in a corresponding working sequence, and output a first audio output signal after performing multi-stage coding and filtering processing on the first audio input signal, and the storage device is used to store the first audio output signal according to the coding control signal in a corresponding storage sequence;

[0008] When the audio codec chip is in the audio decoding working state, the rate control device is used to output a decoding control signal according to a preset second oversampling ratio, the multiple signal processing units in the computing device are used to start according to the decoding control signal according to the corresponding working timing, and output a second audio output signal after multi-stage decoding and filtering processing on the second audio input signal, and the storage device is used to store the second audio output signal according to the corresponding storage timing according to the decoding control signal.

[0009] A second aspect of the present invention provides an audio codec chip, comprising a chip body and a digital filter as described in the first aspect integrated in the chip body.

[0010] According to a third aspect of the present invention, there is provided an audio codec device, wherein the audio codec device has a built-in digital filter as described in the first aspect.

[0011] The digital filter, audio codec chip and device of the present invention outputs a coding or decoding control signal through a rate control device, drives multiple signal processing units in a computing device to perform multi-stage coding or decoding filtering processing on the audio signal according to a corresponding working sequence, and uses a storage device to store the filtered audio signal according to a storage sequence. This technical solution is based on the fact that multiple signal processing units in a computing device perform different functions in the coding process and the decoding process respectively. Compared with the audio coding and decoding solutions of related technologies, the use of multipliers and adders in multi-stage extraction filters and interpolation filters is reduced, the overall circuit area is smaller and the power consumption is lower, and it is suitable for low-power scenarios and compact designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0013] Figure 1 A schematic diagram of the internal structure of the digital filter provided in the embodiment of the present application;

[0014] Figure 2 This is a schematic diagram of the internal structure of the rate control device in the embodiment of the present application;

[0015] Figure 3 This is a schematic diagram of the internal structure of the computing device in the embodiment of the present application;

[0016] Figure 4 A schematic diagram of the internal structure of a decimation filter used to work in an audio data encoding working state in an embodiment of the present application;

[0017] Figure 5 Schematic diagram of the internal structure of an interpolation filter used to work in an audio data decoding working state in an embodiment of the present application;

[0018] Figure 6 This is a schematic diagram of the internal structure of the compensation filter in the embodiment of the present application:

[0019] Figure 7 This is a schematic diagram of the internal structure of a half-band filter in an embodiment of the present application;

[0020] Figure 8 Schematic diagram of the internal structure of the storage device in the embodiment of the present application.

[0021] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0022] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0023] It should be noted that related terms such as "first", "second", etc. can be used to describe various components, but these terms do not limit the components. These terms are only used to distinguish one component from another component. For example, without departing from the scope of the present invention, a first component can be referred to as a second component, and the second component can also be referred to as a first component similarly. The term "and / or" refers to any one or more combinations of related items and description items.

[0024] See also Figure 1 This embodiment provides a digital filter, which is applied to an audio codec chip and at least includes a rate control device 10, a computing device 20 and a storage device 30.

[0025] Among them, the first output end of the rate control device 10 is electrically connected to the input end of the computing device 20, the output end of the computing device 20 is electrically connected to the first input end of the storage device 30, and the second output end of the rate control device 10 is electrically connected to the second input end of the storage device 30, so that the entire digital filter can complete signal processing according to the preset oversampling ratio under the audio encoding and audio decoding working states.

[0026] When the audio codec chip is in the audio encoding working state, the rate control device 10 is used to output a coding control signal according to a preset first oversampling ratio, and the multiple signal processing units in the computing device 20 are used to start according to the corresponding working sequence according to the coding control signal, and output the first audio output signal after performing multi-stage coding filtering on the first audio input signal, and the storage device 30 is used to store the first audio output signal according to the corresponding storage sequence according to the coding control signal.

[0027] When the audio codec chip is in the audio decoding working state, the rate control device 10 is used to output a decoding control signal according to a preset second oversampling ratio, and the multiple signal processing units in the computing device 20 are used to start according to the corresponding working sequence according to the decoding control signal, and output a second audio output signal after multi-stage decoding and filtering processing on the second audio input signal, and the storage device 30 is used to store the second audio output signal according to the corresponding storage sequence according to the decoding control signal.

[0028] The digital filter of the embodiment of the present application outputs corresponding encoding or decoding control signals based on different oversampling ratios set in different working states through the rate control device 10, dynamically adjusts the signal processing flow and storage timing in the audio encoding and decoding working states, and coordinates and controls the working time, working timing and storage device of multiple signal processing units in the computing device 20, thereby completing the encoding and decoding of audio signals. That is, the present technical solution adopts the dynamic first and second oversampling ratios to adapt to the encoding and decoding states respectively, and the multiple signal processing units in the computing device 20 respectively perform different functions in the encoding process and the decoding process (some signal processing units participate in both the encoding process and the decoding process). Compared with the audio encoding and decoding scheme of the related art, the use of multipliers and adders in the multi-stage decimation filter and the interpolation filter is reduced, the overall circuit area is smaller and the power consumption is lower, and it is suitable for low-power scenarios and compact designs.

[0029] In an optional implementation of the present embodiment, the rate control device 10 includes a counter 101 and a control logic module 102, the input end of the counter 101 is used to receive an external clock signal, the output end of the counter 101 is electrically connected to the input end of the control logic module 102, and the output end of the control logic module 102 is electrically connected to the computing device 20 and the storage device 30 at the same time.

[0030] The counter 101 is used to generate a count value according to a clock signal, and the control logic module 102 is used to divide a plurality of encoding time periods according to a preset first oversampling ratio, and output a coding control signal when the count value is in each encoding time period. And the counter 101 is used to generate a count value according to a clock signal, and the control logic module 102 is used to divide a plurality of decoding time periods according to a preset second oversampling ratio, and output a decoding control signal when the count value is in each decoding time period. The coding control signal generated in each coding time period controls one of the plurality of signal processing units, and the coding control signal generated in each decoding time period controls one of the plurality of signal processing units.

[0031] Specifically, during the audio encoding process, when the first oversampling ratio corresponding to the audio encoding working state is set to 256, the counter 101 generates a count value according to the working clock frequency and the audio data input frequency (the maximum count value is equal to the clock frequency divided by the input frequency). For example, when the counter working frequency is 12.288MHz and the input frequency is 48kHz, the counting range of the counter is 0-255. Based on the fact that the working frequency of the integrator in the multiple signal processing units in the computing device 20 is the same as the input data, the working frequency of the differentiator is the input data frequency divided by the decimation ratio, and the corresponding decimation ratio is 64. Therefore, the control logic module 102 outputs the corresponding encoding control signal to control the operation of a specific signal processing unit (e.g., differentiator) when the counter counts to 63, 127, 191, 255 (the multiple encoding time periods divided). After the differentiator is finished working, the encoding control signal output by the control logic module 102 controls the storage device 30 to store the calculated data or the final audio output signal.

[0032] In an optional implementation manner of the present embodiment, multiple signal processing units in the computing device are started according to the encoding control signal in a corresponding working sequence to form an extraction filter, the extraction filter performs multi-stage encoding filtering processing on the first audio input signal to reduce the sampling rate, and then outputs the first audio output signal; and, multiple signal processing units in the computing device are started according to the decoding control signal in a corresponding working sequence to form an interpolation filter, the interpolation filter performs multi-stage decoding filtering processing on the second audio input signal to increase the sampling rate, and then outputs the second audio output signal.

[0033] Specifically, the signal processing unit in the computing device 20 coordinates work through the precise timing of the encoding or decoding control signal. The encoding timing control signal triggers the signal processing unit to perform extraction and filtering operations in sequence. The start and end of each level of operation are managed by the control logic module 120. The decoding timing control signal triggers the signal processing unit to perform interpolation filtering operations in sequence according to the interpolation ratio to ensure that the frequency enhancement process of the low-frequency signal is seamless. That is, the audio input signal is received by the computing device 20, and after being processed by the extraction or interpolation filter, an audio output signal that meets the target sampling rate requirements is generated and transmitted to the subsequent storage device or audio interface module. Through the above design, the multiple signal processing units in the computing device 20 can execute different working timings and working times based on different control signals, thereby realizing the multi-stage filtering function of data downsampling during audio encoding and data upsampling during decoding, meeting the high quality and high efficiency requirements of audio signal processing.

[0034] See also Figure 3 , Figure 4 and Figure 5 The multiple signal processing units of the computing device include a multiplier, an integrator, a differentiator and a delay device, the extraction filter includes a comb filter, a compensation filter and a half-band filter, and the interpolation filter includes multiple half-band filters.

[0035] Among them, the multiplier, integrator, differentiator and delay device in the operation device are started according to the corresponding working sequence according to the coding control signal to form a comb filter, a compensation filter and a half-band filter, and the first audio input signal is sequentially subjected to the first-stage downsampling processing, the frequency compensation processing and the second-stage downsampling processing, and then the first audio output signal is output; and the delay device, multiplier and adder in the operation device are started according to the corresponding working sequence according to the coding control signal to form multiple half-band filters, and the second audio input signal is subjected to multi-stage interpolation processing to increase the sampling rate, and then the second audio output signal is output.

[0036] Specifically, the extraction filter includes a comb filter, a compensation filter and a half-band filter, which realizes the downsampling of the first audio input signal through multi-stage coding and filtering processing. The specific process is as follows: the comb filter is composed of an integrator, a differentiator and a delay device, and completes the first-stage downsampling processing of the first audio input signal. The comb filter eliminates high-frequency components by integrating and differentiating the signal, providing a processing basis for subsequent filtering. The compensation filter is composed of a multiplier and a delay device, which is used to perform frequency compensation on the comb filter output signal to correct the spectrum distortion caused by downsampling. The half-band filter is formed by a signal processing unit in the computing device, which is used to perform a second-stage downsampling processing, further reduce the sampling rate of the signal and output the first audio output signal. The above process realizes multi-stage coding and filtering processing of the first audio input signal, ensuring the signal quality while improving the downsampling efficiency.

[0037] Specifically, the interpolation filter includes a plurality of half-band filters, which realize upsampling of the second audio input signal through multi-stage decoding filtering processing. The specific process is as follows: the delay device, multiplier and adder in the operation device are started according to the corresponding working sequence according to the decoding control signal, and a plurality of half-band filters are formed in sequence. Each half-band filter gradually increases the sampling rate of the second audio input signal through interpolation calculation. The number of stages and specific parameters of the half-band filter can be adjusted according to the requirement of increasing the target sampling rate. After the multi-stage interpolation filter processing is completed, the generated second audio output signal has a higher sampling rate to meet the requirements of audio decoding.

[0038] Based on the above audio encoding and audio decoding processes, each signal processing unit in the computing device is started at different working timings based on the corresponding control signal in different working states to form filters with different functions and different types. For example, in the audio encoding working state, a comb filter, a compensation filter and a half-band filter are formed by a multiplier, an integrator, a differentiator and a delay device to perform audio encoding. In the audio decoding working state, multiple half-band filters are formed by a delay device, a multiplier and an adder to perform audio decoding. In addition, the result of the audio signal processing by the computing device is directly output to the storage device. In the storage device, the audio data is stored in order according to the calculation results of the filter. When the storage space reaches the upper limit, the data is overwritten from the beginning to ensure the cyclicity and continuity of the storage operation. The above implementation method meets the dual requirements of filtering accuracy and efficiency in the audio encoding and decoding process through the flexible configuration of the computing device and the coordinated work of multiple signal processing units. In addition, based on the fact that multiple signal processing units in the computing device 20 respectively perform different functions in the encoding process and the decoding process (some signal processing units participate in both the encoding process and the decoding process), compared with the audio coding and decoding scheme of the related technology, the use of multipliers and adders in the multi-stage extraction filter and the interpolation filter is reduced, the overall circuit area is smaller and the power consumption is lower, which is suitable for low-power scenarios and compact designs.

[0039] Please return and refer to Figure 3 A comb filter includes five integrators and five differentiators. The five integrators are connected in sequence to form a five-level integration cascade relationship. The five differentiators are connected in sequence to form a five-level differentiation cascade relationship. The last integrator in the five-level integration cascade relationship is electrically connected to the first differentiator in the five-level differentiation cascade relationship.

[0040] Specifically, the working principle of the comb filter is as follows: the integrator part forming a five-level integral cascade relationship performs step-by-step integration processing on the first audio input signal, and the output of each integrator is the cumulative sum of the current input signal and the historical signal. The five-level cascade design expands the scope of the integral operation, smoothes the signal in the time domain, and suppresses high-frequency noise. In addition, the differentiator part forming a five-level differential cascade relationship performs step-by-step differentiation processing on the integrator output signal, and the output of each differentiator is the difference between the current signal and the previous signal, which restores the signal change information and reduces the interference of the low-frequency component on subsequent filtering. Thus, a full-pass filter characteristic is formed by combining the integration and differentiation operations through the comb filter. Through the multi-stage cascade design, the filter effectively retains the low-frequency part of the signal during the downsampling process, while suppressing the interference of the high-frequency part, providing an optimized input signal for the subsequent compensation filter and half-band filter.

[0041] Among them, the working timing of each stage of integrator and differentiator in the comb filter is controlled by the encoding control signal provided by the rate control device. The control logic module triggers the start of each stage according to the count value of the counter, and adjusts the working frequency of the differentiator according to the decimation ratio. For example, when the decimation ratio is 64, the differentiator operates at 1 / 64 of the input signal frequency and works once every 64 input signal cycles. It can be seen that the comb filter is a key component in the decimation filter and is suitable for the first stage downsampling processing of oversampled data. Its five-stage integration-differentiation design optimizes the time smoothness and frequency selectivity of the signal, ensuring high-quality audio signal processing effects. Therefore, through the above design, the comb filter effectively reduces the sampling rate in the audio encoding process and provides a high-quality signal basis for subsequent filtering operations.

[0042] See also Figure 6 A compensation filter includes N compensation filter components connected in series in sequence, each compensation filter component includes a delay device, two multipliers and an adder, and the output end of each delay device is electrically connected to the input end of each delay device through a multiplier, an adder, and a multiplier in sequence to form a closed-loop compensation filter component.

[0043] Specifically, the compensation filter, as a key component of the decimation filter, is suitable for down-sampling signal processing in the audio encoding process. Its design can ensure the integrity of the signal in the passband while avoiding spectral distortion caused by the filter characteristics. Among them, the value of N determines the accuracy and complexity of the compensation filter. When N is 100, the compensation filter contains 100 delays, 200 multipliers and 100 adders, which can achieve high-precision passband compensation effect. Through the multi-stage processing of the compensation filter, the signal attenuation in the passband of the comb filter is corrected, so that the signal maintains a high fidelity when passing through the decimation filter. That is, the compensation filter is used to compensate for the attenuation in the passband of the first-stage comb filter. Through the written matlab program, the relevant parameters such as passband cutoff frequency, stopband cutoff frequency, passband ripple and stopband ripple can be input to obtain the coefficients of the compensation filter. Among them, a delay of each compensation filter component is used to store and delay the input signal to support the feedback and feedforward operation of the filter. One of the two multipliers is used to multiply the output signal of the delay device by the compensation coefficient, and the other multiplier is used to correct the coefficient of the output signal of the adder. An adder is used to add the input signal and the signal of the delay device output adjusted by the multiplier to generate a compensated output signal.

[0044] It should be noted that the signal passes through N compensation filter components in sequence from the input end of the compensation filter, and each component delays, weights and superimposes the signal, gradually realizing the correction of the signal attenuation in the passband of the comb filter. In addition, the compensation coefficient of each multiplier is generated by the design program and determined according to parameters such as the passband cutoff frequency, the stopband cutoff frequency, the passband ripple and the stopband ripple. Through the precise design of these coefficients, the compensation filter amplifies the signal in the passband while maintaining the signal attenuation in the stopband, ensuring the frequency response of the overall filter is flat. In addition, the coefficients of the compensation filter can be designed by the matlab program. After inputting the required parameters (such as the passband cutoff frequency, the stopband cutoff frequency, the passband ripple and the stopband ripple), the matlab program calculates and outputs the multiplier coefficients of each compensation filter component.

[0045] See also Figure 7 A half-band filter includes a plurality of half-band filter components connected in series in sequence, each half-band filter component includes a delay device, two multipliers and an adder, and the output end of each delay device is electrically connected to the input end of each delay device via a multiplier, an adder, and a multiplier in sequence to form a closed-loop half-band filter component.

[0046] Specifically, the first two stages of the interpolation filter are composed of half-band filters, and a half-band filter is composed of M half-band filter components, which are used to interpolate the audio decoding data. Similarly, the value of M determines the accuracy and complexity of the interpolation filter. When M is 100, a half-band filter contains 100 delays, 200 multipliers and 100 adders. The two-stage half-band filter interpolation design is suitable for audio decoding scenarios, and can achieve high-quality interpolation of low-frequency audio data and adapt to higher sampling rate requirements.

[0047] Among them, when the control logic module detects that the count value output by the counter is in the time period of 1 / 2-3 / 4, the first-stage half-band filter is started, and the first-stage half-band filter completes the preliminary interpolation processing of the input signal through the cascaded half-band filter components, multiplies the sampling rate and maintains the flatness of the frequency response. And, when the control logic module detects that the count value of the counter is in the time period of 3 / 4-1, the second-stage half-band filter is started, and the second-stage half-band filter further interpolates the data output by the first-stage filter, continues to multiply the sampling rate and optimizes the frequency characteristics. Thus, after being processed by two stages of half-band filters, the original audio data is interpolated to generate 4 audio data. At the same time, when the counter value is 0, the control logic module writes the audio decoding data into the preset audio data storage space in the storage device to ensure that the input data of the interpolation process is complete.

[0048] It should be noted that the oversampling ratio defines the multiple by which the sampling rate of the input audio data is increased before processing. For example, when the oversampling ratio is 256, each sampling point of the input signal is expanded to 256 sampling points for processing. Assuming that the counting cycle of the counter is 0 to 255, there are exactly 256 count values, each of which corresponds to an oversampling point, so a complete counting cycle can cover the complete number of oversampling data points. For the case where the oversampling ratio is 256, the counting range of the counter from 0 to 255 can be accurately allocated to each oversampling point (that is, each point corresponds to a value of the counter). That is, the control logic module divides a complete counting cycle into 4 parts (0-63, 64-127, 128-191, 192 to 255) through the counter, corresponding to the 4 generated data respectively, and the 4 data are latched in sequence by the sample holder to ensure that each data is stably transmitted to the storage device. In addition, the design principle of the half-band filter is consistent with the compensation filter, and the component coefficients (for example, passband cutoff frequency, stopband ripple) are generated according to the filtering requirements through the matlab tool. The parameters of the two-stage half-band filters can be configured independently to meet different interpolation ratio and frequency characteristic requirements.

[0049] Specifically, when the audio codec chip is in the audio coding working state, the corresponding functions and signal processing contents of each filter in different time periods in a complete counting cycle are shown in Table 1 below:

[0050] Table 1

[0051]

[0052] Specifically, when the audio codec chip is in the audio decoding working state, the corresponding functions and signal processing contents of each filter in different time periods in a complete counting cycle are shown in Table 2 below:

[0053] Table 2

[0054]

[0055] See also Figure 8 The storage device 30 includes a dynamic random access memory 301 and a programmable memory 302. The dynamic random access memory 301 is used to store the first audio output signal, the second audio output signal and the intermediate calculation data of the filter, and the programmable memory is used to store the filter coefficients. The intermediate calculation data of the filter includes the intermediate data of the comb, compensation and half-band filter calculations.

[0056] Specifically, during the operation of the system, the dynamic random access memory 301 and the programmable memory 302 work in coordination through the control signal transmitted by the control logic module. In the filter operation stage: the coefficients required by the filter are loaded into the filter hardware by the programmable memory 302, and the intermediate calculation data is written into the dynamic random access memory 301 in real time. In the data storage stage: the first audio output signal or the second audio output signal processed by the filter is written into the dynamic random access memory 301, waiting for further processing or output. In the coefficient update stage: when the design requirements of the filter change, the coefficients in the programmable memory 302 are rewritten through the external interface to adapt to the new filtering requirements.

[0057] The embodiment of the present application also provides an audio codec chip, including a chip body and a digital filter integrated in the chip body.

[0058] The embodiment of the present application also provides an audio codec device, which has a built-in digital filter.

[0059] The digital filter, audio codec chip and device of the embodiment of the present application outputs a coding or decoding control signal through a rate control device, drives multiple signal processing units in the computing device to perform multi-stage coding or decoding filtering processing on the audio signal according to the corresponding working sequence, and uses a storage device to store the filtered audio signal according to the storage sequence. This technical solution is based on the multiple signal processing units in the computing device performing different functions in the encoding process and the decoding process respectively. Compared with the audio codec solution of the related art, the use of multipliers and adders in the multi-stage extraction filter and the interpolation filter is reduced, the overall circuit area is smaller and the power consumption is lower, and it is suitable for low-power scenarios and compact designs.

[0060] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0061] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A digital filter, characterized in that: Applied to an audio codec chip, the digital filter comprises a rate control device, a computing device and a storage device, the first output end of the rate control device is electrically connected to the input end of the computing device, the output end of the computing device is electrically connected to the first input end of the storage device, and the second output end of the rate control device is electrically connected to the second input end of the storage device; When the audio codec chip is in an audio coding working state, the rate control device is used to output a coding control signal according to a preset first oversampling ratio, the multiple signal processing units in the computing device are used to start according to the coding control signal in a corresponding working sequence, and output a first audio output signal after performing multi-stage coding and filtering processing on the first audio input signal, and the storage device is used to store the first audio output signal according to the coding control signal in a corresponding storage sequence; When the audio codec chip is in the audio decoding working state, the rate control device is used to output a decoding control signal according to a preset second oversampling ratio, the multiple signal processing units in the computing device are used to start according to the decoding control signal according to the corresponding working timing, and output a second audio output signal after multi-stage decoding and filtering processing on the second audio input signal, and the storage device is used to store the second audio output signal according to the corresponding storage timing according to the decoding control signal.

2. The digital filter according to claim 1, wherein: The rate control device includes a counter and a control logic module, the input end of the counter is used to receive an external clock signal, the output end of the counter is electrically connected to the input end of the control logic module, and the output end of the control logic module is electrically connected to the computing device and the storage device at the same time; The counter is used to generate a count value according to the clock signal, and the control logic module is used to divide a plurality of coding time periods according to a preset first oversampling ratio, and output a coding control signal respectively when the count value is in each coding time period; wherein the coding control signal generated in each coding time period corresponds to controlling one signal processing unit among the plurality of signal processing units; Furthermore, the counter is used to generate a count value according to the clock signal, and the control logic module is used to divide the decoding time periods into multiple decoding time periods according to a preset second oversampling ratio, and output a decoding control signal respectively when the count value is in each decoding time period; wherein the encoding control signal generated in each decoding time period corresponds to controlling one signal processing unit among multiple signal processing units.

3. The digital filter according to claim 2, wherein: The plurality of signal processing units in the computing device are specifically configured to be started according to the coding control signal in a corresponding working sequence to form a decimation filter, wherein the decimation filter is configured to perform multi-stage coding filtering processing on the first audio input signal to reduce the sampling rate, and then output a first audio output signal; The multiple signal processing units in the computing device are specifically used to start according to the decoding control signal in accordance with the corresponding working timing to form an interpolation filter, and the interpolation filter is used to perform multi-stage decoding and filtering processing on the second audio input signal to increase the sampling rate, and then output a second audio output signal.

4. The digital filter according to claim 3, characterized in that The plurality of signal processing units of the computing device include a multiplier, an integrator, a differentiator and a delay device, the decimation filter includes a comb filter, a compensation filter and a half-band filter, and the interpolation filter includes a plurality of half-band filters; The multiplier, integrator, differentiator and delay device in the operation device are used to start according to the coding control signal in a corresponding working sequence to form a comb filter, a compensation filter and a half-band filter, and perform a first-stage downsampling process, a frequency compensation process and a second-stage downsampling process on the first audio input signal in sequence, and then output a first audio output signal; The delay device, multiplier and adder in the operation device are used to start according to the corresponding working timing according to the coding control signal to form multiple half-band filters, and perform multi-level interpolation processing on the second audio input signal to increase the sampling rate and then output a second audio output signal.

5. The digital filter according to claim 4, characterized in that A comb filter includes five integrators and five differentiators, wherein the five integrators are connected in sequence to form a five-level integration cascade relationship, and the five differentiators are connected in sequence to form a five-level differentiation cascade relationship, and the last integrator in the five-level integration cascade relationship is electrically connected to the first differentiator in the five-level differentiation cascade relationship.

6. The digital filter according to claim 4, characterized in that The compensation filter comprises a plurality of compensation filter components connected in series in sequence, each compensation filter component comprises a delay device, two multipliers and an adder, and the output end of each delay device is electrically connected to the input end of each delay device via a multiplier, an adder and a multiplier in sequence to form a compensation filter component.

7. The digital filter according to claim 4, wherein: A half-band filter comprises a plurality of half-band filter components connected in series in sequence, each half-band filter component comprises a delay device, two multipliers and an adder, and the output end of each delay device is electrically connected to the input end of each delay device via a multiplier, an adder and a multiplier in sequence to form a half-band filter component.

8. The digital filter according to claim 1, wherein: The storage device includes a dynamic random access memory and a programmable memory; The dynamic random access memory is used to store the first audio output signal, the second audio output signal and intermediate calculation data of the filter, and the programmable memory is used to store filter coefficients.

9. An audio codec chip, characterized in that: The invention comprises a chip body and a digital filter as claimed in any one of claims 1 to 8 integrated in the chip body.

10. An audio codec device, characterized in that: The audio codec device has a built-in digital filter as described in any one of claims 1 to 8.

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