Memory device, operating method thereof, and memory system

Abstract

The invention provides a memory device, an operation method thereof and a memory system. The memory device comprises a peripheral circuit and a memory array coupled with the peripheral circuit; the memory array comprises at least one memory block, the peripheral circuit comprises at least one row decoder, and one memory block is correspondingly connected with one row decoder; the row decoder comprises a logic circuit and a level conversion circuit; wherein the logic circuit is configured to generate a first control signal, a second control signal and a first output signal based on an address signal and a state signal of the storage block correspondingly connected with the row decoder; the level of the second control signal is higher than that of the first control signal; the level conversion circuit is configured to generate a second output signal based on the first output signal in response to the first control signal and the second control signal, respectively.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory device and an operating method thereof, and a memory system. Background Art

[0002] Memory devices are memory devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) flash memory has become a mainstream product in the storage market due to its high storage density, controllable production cost, suitable programming and erasing speed and retention characteristics.

[0003] As the requirements for memory devices continue to increase, how to extend the service life of memory devices has become one of the technical issues that urgently need to be solved in this field at this stage. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a memory device and an operating method thereof, and a memory system to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a memory device, the memory device comprising a peripheral circuit and a memory array coupled to the peripheral circuit; the memory array comprises at least one memory block, the peripheral circuit comprises at least one row decoder, one memory block is correspondingly connected to one row decoder; the row decoder comprises a logic circuit and a level conversion circuit; wherein,

[0007] The logic circuit is configured to generate a first control signal, a second control signal and a first output signal based on an address signal of the storage block correspondingly connected to the row decoder and a state signal; a level of the second control signal is higher than a level of the first control signal;

[0008] The level conversion circuit is configured to generate a second output signal based on the first output signal in response to the first control signal and the second control signal, respectively.

[0009] In an optional implementation, the logic circuit includes a first processing circuit, a second processing circuit and a third processing circuit; the input end of the second processing circuit and the input end of the third processing circuit are respectively connected to the output end of the first processing circuit; the output end of the second processing circuit is connected to the input end of the level conversion circuit; the output end of the third processing circuit is connected to the control end of the level conversion circuit; wherein,

[0010] The first processing circuit is configured to generate a selection signal based on an address signal and a state signal of the storage block;

[0011] The second processing circuit is configured to generate the first output signal based on the selection signal;

[0012] The third processing circuit is configured to generate the first control signal and the second control signal based on the selection signal.

[0013] In an optional implementation, the third processing circuit includes a first NAND gate and a low-level selection circuit connected to the low-level end of the first NAND gate; the first input end of the first NAND gate is connected to the output end of the first processing circuit; the second input end of the first NAND gate is connected to the selection enable signal; wherein,

[0014] The low level selection circuit is configured to output a first low level to the low level end of the first NAND gate in a first period, and output a second low level to the low level end of the first NAND gate in a second period;

[0015] The first NAND gate is configured to output a first control signal having the first low level in the first period based on the selection signal and the selection enable signal, and to output a second control signal having the second low level in the second period.

[0016] In an optional implementation, the low level selection circuit includes:

[0017] a first transistor, wherein a first end of the first transistor is connected to a low level end of the first NAND gate; a second end of the first transistor is used to receive the second low level; a control end of the first transistor is connected to a first enable signal; in the first period, the first enable signal is a low level signal, and the first transistor is turned off; in the second period, the first enable signal is a high level signal, and the first transistor is turned on;

[0018] A second transistor, wherein the second end of the second transistor is connected to the low level end of the first NAND gate and the first end of the first transistor; the first end of the second transistor is used to receive the first low level; the control end of the second transistor is connected to a second enable signal; in the first time period, the second enable signal is a high level signal, and the second transistor is turned on; in the second time period, the second enable signal is a low level signal, and the second transistor is turned off.

[0019] In an optional implementation, the peripheral circuit further includes control logic; the control logic is configured as follows:

[0020] The selection enable signal, the first enable signal, and the second enable signal are generated based on one of a read enable signal, a program enable signal, and a verify enable signal.

[0021] In an optional implementation, the level conversion circuit includes:

[0022] a third transistor, wherein a control terminal of the third transistor is connected to an output terminal of the third processing circuit;

[0023] a fourth transistor, wherein a first end of the fourth transistor is connected to a first end of the third transistor; and a second end of the fourth transistor is used for receiving a first high level;

[0024] a fifth transistor, wherein a first end of the fifth transistor is connected to the output end of the second processing circuit, and a second end of the fifth transistor is connected to the second end of the third transistor; an end at which the second end of the fifth transistor and the second end of the third transistor are connected to each other serves as the output end of the level conversion circuit and is connected to the control end of the fourth transistor.

[0025] In an optional implementation, the first processing circuit includes:

[0026] a second NAND gate, wherein the second NAND gate is configured to receive an address signal of the storage block correspondingly connected to the row decoder, and generate a first initial selection signal based on the address signal of the storage block;

[0027] a state latch circuit configured to generate a second initial selection signal based on a state signal of the memory block;

[0028] A first NOR gate is configured to receive the first initial selection signal and the second initial selection signal, and generate the selection signal based on the first initial selection signal and the second initial selection signal.

[0029] In an optional implementation, the second processing circuit includes:

[0030] N inverters, the N inverters are connected in sequence, and an input end of a first inverter is connected to an output end of the first processing circuit; N is an even number greater than zero;

[0031] A sixth transistor, wherein a first end of the sixth transistor is connected to the output end of the last inverter, and a second end of the sixth transistor is connected to the input end of the level conversion circuit.

[0032] In an optional embodiment, the peripheral circuit also includes a word line driver and multiple driving transistors; the first end of the driving transistor is connected to the word line driver, and the second end of the driving transistor is connected to the word line in the storage block; the control end of the driving transistor is connected to the output end of the level conversion circuit; the driving transistor is turned on after receiving the second output signal, and couples the word line driver to the word line.

[0033] In a second aspect, an embodiment of the present disclosure provides a memory system, including:

[0034] At least one memory device according to any of the preceding embodiments;

[0035] A memory controller is coupled to the at least one memory device and is configured to control the memory device.

[0036] In a third aspect, an embodiment of the present disclosure provides an operating method of a memory device, the operating method comprising:

[0037] The logic circuit in the row decoder of the memory device generates a first control signal, a second control signal and a first output signal based on an address signal and a state signal of a storage block correspondingly connected to the row decoder; the level of the second control signal is higher than the level of the first control signal;

[0038] The level conversion circuit in the row decoder generates a second output signal based on the first output signal in response to the first control signal and the second control signal respectively.

[0039] In an optional implementation, a logic circuit in a row decoder of the memory device generates a first control signal, a second control signal and a first output signal based on an address signal and a state signal of a storage block correspondingly connected to the row decoder, including:

[0040] The first processing circuit in the logic circuit generates a selection signal based on the address signal and the state signal of the storage block;

[0041] The second processing circuit in the logic circuit generates a first output signal based on the selection signal;

[0042] The third processing circuit in the logic circuit generates the first control signal and the second control signal based on the selection signal.

[0043] In an optional implementation, the third processing circuit in the logic circuit generates the first control signal and the second control signal based on the selection signal, including:

[0044] The low level selection circuit in the third processing circuit outputs a first low level to the low level end of the first NAND gate in the third processing circuit in a first period, and outputs a second low level to the low level end of the first NAND gate in a second period;

[0045] Based on the selection signal and the selection enable signal, the first NAND gate outputs a first control signal with the first low level in the first period, and outputs a second control signal with the second low level in the second period.

[0046] In an optional implementation, the low level selection circuit in the third processing circuit outputs a first low level to a low level end of a first NAND gate in the third processing circuit in a first time period, and outputs a second low level to a low level end of the first NAND gate in a second time period, comprising:

[0047] Applying a first enable signal to a control terminal of a first transistor in the low level selection circuit, and applying a second enable signal to a control terminal of a second transistor in the low level selection circuit;

[0048] In the first period, the first enable signal is a low level signal, and the first transistor is turned off; the second enable signal is a high level signal, and the second transistor is turned on, and outputs the first low level to the low level end of the first NAND gate;

[0049] In the second period, the first enable signal is a high level signal, the first transistor is turned on, and outputs the second low level to the low level end of the first NAND gate; the second enable signal is a low level signal, and the second transistor is turned off.

[0050] In an optional implementation, the operation method further includes:

[0051] The control logic in the memory device generates the selection enable signal, the first enable signal, and the second enable signal based on one of a read enable signal, a program enable signal, and a verification enable signal.

[0052] In an optional implementation, the first time period ranges from 0.5 microseconds to 1 microsecond.

[0053] In the technical solution provided by the present disclosure, the row decoder includes a logic circuit and a level conversion circuit, the logic circuit includes a low-level selection circuit, so that the logic circuit can generate a first control signal with a first low level in a first period, and generate a second control signal with a second low level in a second period, and the second low level is higher than the first low level, and the level conversion circuit can respond to the first control signal and the second control signal to convert the first output signal with a lower level generated by the logic circuit into a second output signal with a higher level. The technical solution provided by the present disclosure can shorten the working time of the transistor in the level conversion circuit under a large negative bias, reduce the degree of degradation of the electrical performance of the transistor, and increase the service life of the level conversion circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A schematic diagram of an exemplary system having a memory system provided for an embodiment of the present disclosure;

[0055] Figure 2 A schematic diagram of an exemplary memory card having a memory system provided for an embodiment of the present disclosure;

[0056] Figure 3 A schematic diagram of an exemplary solid state drive having a memory system provided for an embodiment of the present disclosure;

[0057] Figure 4 A schematic diagram of an exemplary memory device including peripheral circuits provided for an embodiment of the present disclosure;

[0058] Figure 5 A cross-sectional schematic diagram of a memory array including a memory cell string provided in an embodiment of the present disclosure;

[0059] Figure 6 A schematic diagram of an exemplary memory device including a memory array and peripheral circuits provided for an embodiment of the present disclosure;

[0060] Figure 7 A schematic diagram of a memory block and a portion of peripheral circuits connected to the memory block in a memory device provided by an embodiment of the present disclosure;

[0061] Figure 8 A schematic diagram of the structure of a row decoder provided in an embodiment of the present disclosure;

[0062] Fig. 9 A circuit diagram of a first processing circuit provided in an embodiment of the present disclosure;

[0063] Fig.10 A circuit diagram of a second processing circuit provided in an embodiment of the present disclosure;

[0064] Fig.11 A circuit diagram of a third processing circuit provided in an embodiment of the present disclosure;

[0065] Fig.12 A circuit diagram of a level conversion circuit provided in an embodiment of the present disclosure;

[0066] Fig.13 A circuit diagram of a row decoder provided in an embodiment of the present disclosure;

[0067] Fig.14 A voltage curve when performing a read operation provided for a specific example of the present disclosure;

[0068] Fig.15 Simulation results of the row decoder provided by the embodiment of the present disclosure Figure 1 ;

[0069] Fig.16 Simulation results of the row decoder provided by the embodiment of the present disclosure Figure 2 ;

[0070] Fig.17 A flowchart of an operating method of a memory device provided in an embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0071] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0072] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0073] In the drawings, like reference numerals refer to like elements throughout.

[0074] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0075] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0076] The memory system in the embodiments of the present disclosure includes but is not limited to a memory system including a three-dimensional NAND memory. For ease of understanding, the memory system provided by the present disclosure is described by taking the memory system including a three-dimensional NAND memory as an example.

[0077] Figure 1 Schematic diagram of an exemplary system with a memory system provided for an embodiment of the present disclosure. In the embodiment of the present disclosure, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1As shown in , the system 100 may include a host device 101 and a memory system 102, and the memory system 102 may include one or more memory devices 103 and a memory controller 104. The host device 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host device 101 may be configured to send data to the memory system 102 or receive data from the memory system 102.

[0078] In some embodiments, the memory controller 104 is coupled to the memory device 103 and the host device 101, and is configured to control the memory device 103. The memory controller 104 can manage the data stored in the memory device 103 and communicate with the host device 101. In some embodiments, the memory controller 104 is designed to operate in a low duty cycle environment, such as in a secure digital card, a compact flash card (Compact Flash Card, CFC), a universal serial bus (Universal Serial BUS, USB) flash drive, or in other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In other embodiments, the memory controller 104 is designed to operate in a high duty cycle environment, such as a solid state drive or an embedded multimedia card (EmbeddedMulti-MediaCard, eMMC).

[0079] In some embodiments, the memory controller 104 and the one or more memory devices 103 may be integrated into various types of storage devices, that is, the memory system 102 may be implemented and packaged into different types of terminal electronic products.

[0080] In such Figure 2 In one example shown in , the memory controller 104 and the single memory device 103 can be integrated into the memory card 201. The memory card 201 can be a compact flash card, a smart media card (Smart Media Card, SMC), a memory stick (Memory Stick, MS), a multimedia card (Multi-Media Card, MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as Mini SD card, Micro SD card, SDHC card, etc., or a universal flash card. The memory card 201 can also include a device that connects the memory card 201 to a host device (e.g., Figure 1The host device 101 in the embodiment of the present invention is coupled to the memory card connector 202. Figure 3 In another example shown in , the memory controller 104 and the plurality of memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include a processor that connects the SSD 203 to a host device (eg, Figure 1 In some embodiments, the storage capacity and / or operating speed of SSD203 is greater than the storage capacity and / or operating speed of memory card 201.

[0081] Figure 4 A circuit diagram of an exemplary memory device 300 including peripheral circuits provided for an embodiment of the present disclosure. The memory device 300 may be Figure 1 300 is an example of a memory device 103 in FIG. The memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. The memory array 301 is taken as a three-dimensional NAND type memory array for illustration, wherein the memory cells 305 are NAND memory cells, and the memory cells 305 are provided in the form of an array of memory strings 304, each memory string 304 extending vertically above a substrate (not shown). In some embodiments, each memory string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 305. Each memory cell 305 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0082] In some embodiments, each memory cell 305 is a single level cell (SLC) having two possible memory states and thus can store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, for example, a multi-level cell (MLC) storing two bits per cell, a triple level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0083] like Figure 4As shown in , each memory string 304 may include a bottom select transistor (BST) 307 at its source terminal and a top select transistor (TST) 306 at its drain terminal. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory string 304 during read and program operations. In some embodiments, the sources of the memory strings 304 in the same memory block 303 may be coupled through a common source line (CSL) 310. In other words, all memory strings 304 in the same memory block 303 have a common source (Array Common Source, ACS). According to some embodiments, the top select transistor 306 of each memory string 304 is coupled to a corresponding bit line (BL) 311, and data can be read or written from the bit line 311 via an output bus (not shown). In some embodiments, each memory string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the upper selection tube 306) or a deselection voltage (e.g., 0V) to the corresponding upper selection tube 306 through one or more top selection lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the lower selection tube 307) or a deselection voltage (e.g., 0V) to the corresponding lower selection tube 307 through one or more bottom selection lines (BSL) 309.

[0084] like Figure 4 As shown in , the memory string 304 can be organized into a plurality of memory blocks 303, each of which can have a common source line 310. In some embodiments, each memory block 303 is a basic data unit for an erase operation, that is, all memory cells 305 on the same memory block 303 are erased at the same time. In order to erase the memory cells 305 in a selected memory block, a common source line 310 coupled to the selected memory block and the unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage. It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 305 of adjacent memory strings 304 can be coupled by word lines 312, which select which row of memory cells 305 is affected by a read or programming operation.

[0085] Figure 5 A cross-sectional schematic diagram of a memory array including memory strings provided in an embodiment of the present disclosure. Figure 5As shown, the memory array may include a stacked structure 400, which includes a plurality of gate layers 401 and a plurality of insulating layers 402 that are alternately stacked in sequence, and a channel structure 403 that vertically penetrates the gate layers 401 and the insulating layers 402. The gate layers 401 and the insulating layers 402 may be alternately stacked, and two adjacent gate layers 401 are separated by an insulating layer 402. The number of memory cells included in the memory array is mainly related to the number of pairs of gate layers 401 and insulating layers 402 in the stacked structure 400.

[0086] The constituent material of the gate layer 401 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 401 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 401 includes a doped polysilicon layer. Multiple gate layers 401 surround a channel structure 403 to form a memory string. The gate layer 401 at the top of the stacked structure 400 can extend laterally as an upper selection gate line, the gate layer 401 at the bottom of the stacked structure 400 can extend laterally as a lower selection gate line, and the gate layer 401 extending laterally between the upper selection gate line and the lower selection gate line can serve as a word line layer.

[0087] In some embodiments, the stacked structure 400 may be disposed on a substrate 404. The substrate 404 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0088] It should be noted that, in some other embodiments, the memory array may only include the stacked structure 400 but not the substrate, and the present disclosure does not limit whether the memory array includes the substrate.

[0089] In some embodiments, the channel structure 403 includes a functional layer, a channel layer, and an insulating filling layer. In some embodiments, the channel layer includes silicon, for example, polycrystalline silicon. In some embodiments, the functional layer is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge capture / storage layer"), and a barrier layer. The channel structure 403 may have a cylindrical shape (e.g., a column shape). According to some embodiments, the channel layer, the tunneling layer, the storage layer, and the barrier layer are radially arranged in this order from the center of the column toward the outer surface of the column. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the functional layer may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0090] Return to reference Figure 4 , the peripheral circuit 302 may be coupled to the memory array 301 through the bit line 311, the word line 312, the common source line 310, the lower selection line 309, and the upper selection line 308. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for applying a voltage signal and / or a current signal to each target memory cell 305 through the bit line 311, the word line 312, the common source line 310, the lower selection line 309, and the upper selection line 308, and sensing a voltage signal and / or a current signal from each target memory cell 305 to implement the operation of the memory array 301. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor technology. For example, Figure 6 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 501, a column decoder / bit line driver 502, a row decoder / word line driver 503, a voltage generator 504, a control logic 505, a register 506, a flash memory interface 507, and a data bus 508. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 6 Additional peripheral circuits not shown.

[0091] The page buffer / sense amplifier 501 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to a control signal from the control logic 505. In one example, the page buffer / sense amplifier 501 can store a page of programming data (write data) to be programmed into the memory array 301. In another example, the page buffer / sense amplifier 501 can perform a programming verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer / sense amplifier 501 can also sense a low-power signal from a bit line representing a data bit stored in a memory cell, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 502 can be configured to be controlled by the control logic 505, and select one or more memory strings by applying a bit line voltage generated from the voltage generator 504.

[0092] The row decoder / word line driver 503 may be configured to be controlled by the control logic 505 and select / deselect a memory block of the memory array 301 and select / deselect a word line of the memory block. The row decoder / word line driver 508 may also be configured to drive a word line using a word line voltage generated from the voltage generator 504. In some embodiments, the row decoder / word line driver 503 may also select / deselect and drive a lower selection line and an upper selection line. As described in detail below, the row decoder / word line driver 503 is configured to perform a programming operation on a memory cell coupled to (one or more) selected word lines. The voltage generator 504 may be configured to be controlled by the control logic 505 and generate a word line voltage (e.g., a read voltage, a programming voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 301.

[0093] The control logic 505 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The register 506 may be coupled to the control logic 505 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The flash memory interface 507 may be coupled to the control logic 505 and act as a control buffer to buffer control commands received from a host-side device (not shown) and relay them to the control logic 505, as well as buffer status information received from the control logic 505 and relay them to the memory controller. The flash memory interface 507 may also be coupled to the column decoder / bit line driver 502 via the data bus 508 and act as a data I / O interface and a data buffer to buffer data and relay them to the memory array 301 or relay or buffer data from the memory array 301.

[0094] In some embodiments, Figure 7 FIG. 1 is a schematic diagram of a memory block in a memory device and a portion of a peripheral circuit connected to the memory block. Figure 4 , Figure 6 and Figure 7 The memory device 300 includes a peripheral circuit 302 and a memory array 301 . The memory array 301 includes at least one memory block 303 . The peripheral circuit 302 includes at least one row decoder 601 . One memory block 303 is connected to one row decoder 601 .

[0095] In some embodiments, reference Figure 7, the peripheral circuit also includes a word line driver 602 and a plurality of driving transistors 603, a first end of the driving transistor 603 is connected to the word line driver 602, a second end of the driving transistor 603 is connected to the word line in the storage block 303, and a control end of the driving transistor 603 is connected to the output end of the row decoder 601. When it is necessary to operate the storage unit in the storage block 303, the control logic 505 sends the address signal corresponding to the storage block 303 to the row decoder 601, and the row decoder 601 generates an output signal based on the address signal. After receiving the output signal, the driving transistor 603 is turned on and couples the word line driver 602 to the word line in the storage block 303, so that the word line voltage can be provided to the corresponding word line in the storage block 303 through the word line driver 602.

[0096] In some embodiments, when a read operation or a programming operation is required for a storage unit in the storage block 303, a higher word line voltage needs to be applied to the word line, and the output signal applied to the gate of the driving transistor 603 also needs to have a higher voltage to ensure that multiple driving transistors 603 can be turned on. In order to reduce the overall power consumption of the row decoder 601, the operating voltage used by the logic circuit in the row decoder 601 is relatively low. The row decoder 601 also needs to include a level conversion circuit connected to the logic circuit to convert the output signal of the lower level generated by the logic circuit into an output signal of a higher level. The voltage difference borne by the level conversion circuit during operation is large, which can easily lead to the degradation of the electrical performance of the circuit elements. Therefore, how to improve the service life of the level conversion circuit has become a problem that needs to be solved urgently. In this regard, the present disclosure proposes the following implementation methods.

[0097] Figure 8 A schematic diagram of the structure of a row decoder provided in an embodiment of the present disclosure, in conjunction with reference to Figure 7 and Figure 8 The row decoder 601 includes a logic circuit 700 and a level conversion circuit 800, wherein the logic circuit 700 is configured to generate a first control signal, a second control signal and a first output signal based on an address signal and a state signal of a storage block 303 corresponding to the row decoder 601; the level conversion circuit 800 is configured to generate a second output signal based on the first output signal in response to the first control signal and the second control signal, respectively.

[0098] In the embodiment of the present disclosure, based on the address signal and status signal of the storage block 303 corresponding to the row decoder 601, the logic circuit 700 can generate a first control signal and a second control signal in sequence, and the level of the second control signal is higher than the level of the first control signal. In response to the first control signal, the level conversion circuit 800 is turned on and remains in the on state, and generates a second output signal based on the first output signal. When the first control signal is converted into the second control signal, the level conversion circuit 800 can still remain in the on state and generate a second output signal based on the first output signal.

[0099] In some embodiments, the logic circuit 700 includes a first processing circuit 701, a second processing circuit 702, and a third processing circuit 703, the input end of the second processing circuit 702 and the input end of the third processing circuit 703 are respectively connected to the output end of the first processing circuit 701, the output end of the second processing circuit 702 is connected to the input end of the level conversion circuit 800, and the output end of the third processing circuit 703 is connected to the control end of the level conversion circuit 800.

[0100] Figures 9 to 12 Circuit diagrams of a first processing circuit 701 , a second processing circuit 702 , a third processing circuit 703 and a level conversion circuit 800 are provided for some specific examples of the present disclosure.

[0101] In some embodiments, the first processing circuit 701 is configured to generate a selection signal based on an address signal of the memory block 303 and a state signal.

[0102] In some specific examples, such as Fig. 9 As shown, the first processing circuit 701 includes: a second NAND gate 7011, configured to receive an address signal of a storage block 303 corresponding to the row decoder 601, and generate a first initial selection signal based on the address signal of the storage block 303; a state latch circuit 7013, configured to generate a second initial selection signal based on the state signal of the storage block 303; a first NOR gate 7012, configured to receive the first initial selection signal and the second initial selection signal, and generate a selection signal based on the first initial selection signal and the second initial selection signal.

[0103] In a specific example, when the storage block 303 corresponding to the row decoder 601 is selected, the address signals xa, xb, xc, and xd received by the second NAND gate 7011 are all logic high levels, and the second NAND gate 7011 receives the address signal and outputs a first initial selection signal, which is a logic low level.

[0104] The state latch circuit 7013 is configured to latch the state information of the storage block 303 connected to the row decoder 601. Specifically, the control logic 505 can set the output value of the state latch through the control signals set_blat and rst_blat based on the state of the storage block 303 to mark the state of the storage block 303. When the storage block 303 is a good block that can be used, the a1 end of the state latch will output a logic high signal. At this time, if the Blat_bypass signal is a logic high level, it means that the storage block 303 can be selected, and the state latch circuit 7013 outputs a second initial selection signal, and the second initial selection signal is a logic low level.

[0105] When the second NAND gate 7011 outputs the first initial selection signal and the state latch circuit 7013 outputs the second initial selection signal, the first NOR gate 7012 receives the first initial selection signal and the second initial selection signal and outputs a selection signal, and the first initial selection signal and the second initial selection signal are both logic low levels, then the selection signal is a logic high level.

[0106] In some embodiments, the second processing circuit 702 is configured to generate a first output signal based on the selection signal.

[0107] In some specific examples, such as Fig.10 As shown, the second processing circuit 702 includes: N inverters and a sixth transistor Q6, the N inverters are connected in sequence, the input end of the first inverter is connected to the output end of the first processing circuit 701, the first end of the sixth transistor Q6 is connected to the output end of the last inverter, and the second end of the sixth transistor Q6 is connected to the input end of the level conversion circuit 800.

[0108] Here, it is taken that the second processing circuit 702 includes an inverter D1 and an inverter D2, that is, N is 2, but the present disclosure is not limited thereto. In other embodiments, N may also be an even number greater than 2, such as 4, 6 or 8.

[0109] In the case where the first processing circuit 701 outputs a selection signal of a logic high level, the second processing circuit 702 may generate a first output signal based on the selection signal, and the first output signal is a logic high level.

[0110] In some embodiments, the third processing circuit 703 is configured to generate a first control signal and a second control signal based on the selection signal.

[0111] In some specific examples, such as Fig.11As shown, the third processing circuit 703 includes: a first NAND gate 7031 and a low-level selection circuit 7032 connected to the low-level end of the first NAND gate 7031; the first input end of the first NAND gate 7031 is connected to the output end of the first processing circuit 701, and the second input end of the first NAND gate 7032 is connected to the selection enable signal.

[0112] Specifically, the low-level selection circuit 7032 includes: a first transistor Q1, a first end of the first transistor Q1 is connected to the low-level end of the first NAND gate 7031, a second end of the first transistor Q1 is used to receive the second low-level VSS, and a control end of the first transistor Q1 is connected to the first enable signal; a second transistor Q2, a second end of the second transistor Q2 is connected to the low-level end of the first NAND gate 7031 and the first end of the first transistor Q1, a first end of the second transistor Q2 is used to receive the first low-level VSSX, and a control end of the second transistor Q2 is connected to the second enable signal.

[0113] In some specific examples, the first transistor Q1 and the second transistor Q2 are both NMOS transistors, the first end of the first transistor Q1 and the first end of the second transistor Q2 are both source terminals, and the second ends are both drain terminals.

[0114] In the embodiment of the present disclosure, the first enable signal and the second enable signal may be complementary signals, that is, when the first enable signal is at a logic high level, the second enable signal is at a logic low level, and when the first enable signal is at a logic low level, the second enable signal is at a logic high level. When the first enable signal is at a logic low level and the second enable signal is at a logic high level, the first transistor Q1 is turned off and the second transistor Q2 is turned on, and the low level selection circuit 7032 may provide the first low level VSSX received by the first end of the second transistor Q2 to the low level end of the first NAND gate 7031; when the first enable signal is at a logic high level and the second enable signal is at a logic low level, the first transistor Q1 is turned on and the second transistor Q2 is turned off, and the low level selection circuit 7032 may provide the second low level VSS received by the second end of the first transistor Q1 to the low level end of the first NAND gate 7031.

[0115] In some embodiments, the peripheral circuit also includes a low-voltage level converter (not shown in the figure) connected to the logic circuit 700 and the control logic 505, whose function is to convert the initial enable signal with a higher level generated by the control logic 505 into a first enable signal and a second enable signal with a lower level, so that the levels of the first enable signal and the second enable signal fall within the range of the operating voltage of the area where the logic circuit 700 is located.

[0116] In the embodiment of the present disclosure, when the first input terminal of the first NAND gate 7031 receives a selection signal of a logic high level and the second input terminal receives a selection enable signal of a logic high level, the first NAND gate 7031 will output a control signal, which is a logic low level. When the low level selection circuit 7032 provides the first low level VSSX to the low level terminal of the first NAND gate 7031, the first NAND gate 7031 outputs a first control signal with a level of the first low level VSSX; when the low level selection circuit 73032 provides the second low level VSS to the low level terminal of the first NAND gate 7031, the first NAND gate 7031 outputs a second control signal with a level of the second low level VSS.

[0117] In some specific examples, the second low level VSS is higher than the first low level VSSX.

[0118] In a specific example, the first low level VSSX may be -2V, and the second low level VSS may be 0V.

[0119] It should be noted that in the embodiment of the present disclosure, the level values ​​of the first low level VSSX and the second low level VSS are not limited to the level values ​​in the above specific examples. For example, the first low level VSSX can range from -3V to -1.5V, and the second low level VSS can range from -0.5V to 1V.

[0120] In some embodiments, the level conversion circuit 800 is configured to generate a second output signal based on the first output signal in response to the first control signal and the second control signal, respectively.

[0121] In some specific examples, such as Fig.12 As shown, the level conversion circuit 800 includes: a third transistor Q3, the control end of the third transistor Q3 is connected to the output end of the third processing circuit 703; a fourth transistor Q4, the first end of the fourth transistor Q4 is connected to the first end of the third transistor Q3; the second end of the fourth transistor Q4 is used to receive the first high level VH; a fifth transistor Q5, the first end of the fifth transistor Q5 is connected to the output end of the second processing circuit 702, and the second end of the fifth transistor Q5 is connected to the second end of the third transistor Q3; one end of the second end of the fifth transistor Q5 and the second end of the third transistor Q3 are connected to each other as the output end of the level conversion circuit 800 and connected to the control end of the fourth transistor Q4.

[0122] For the level conversion circuit 800, when its input terminal receives the first output signal generated by the second processing circuit 702 and its control terminal receives the first control signal generated by the third processing circuit 703, the fifth transistor Q5 and the fourth transistor Q4 are turned on, and the third transistor Q3 is turned on accordingly, and the level of the output terminal gradually rises to the first high level VH. Here, since the level of the first control signal is the first low level VSSX, a large voltage difference can be formed between the control terminal and the first terminal of the third transistor Q3, so that the level conversion circuit 800 is quickly turned on. After the voltage at the output terminal of the level conversion circuit 800 rises to the first high level VH, the voltage difference between the control terminal of the third transistor Q3 and its first terminal or second terminal is stabilized at VSSX-VH.

[0123] In a specific example, the third transistor Q3 is a P-type DMOS transistor, which has a smaller on-resistance and a higher turn-on speed, and can enable the level conversion circuit 800 to be turned on quickly and cause the level of the output end of the level conversion circuit 800 to rise quickly to the first high level VH.

[0124] Fig.13 A circuit diagram of a row decoder provided in an embodiment of the present disclosure, such as Fig.13 As shown, the row decoder includes Figures 9 to 12 The first processing circuit 701, the second processing circuit 702, the third processing circuit 703 and the level conversion circuit 800 are shown, wherein the output end of the first NOR gate 7012 in the first processing circuit 701 is connected to the input end of the inverter D1 in the second processing circuit 702 and the first input end of the first NAND gate 7031 in the third processing circuit 703; the second end of the sixth transistor Q6 in the second processing circuit 702 is connected to the first end of the fifth transistor Q5 in the level conversion circuit 800; the output end of the first NAND gate 7031 in the third processing circuit 703 is connected to the control end of the third transistor Q3 in the level conversion circuit 800.

[0125] In the embodiment of the present disclosure, the peripheral circuit also includes a control logic 505 coupled to the row decoder 601, and the control logic 505 is configured to generate a selection enable signal, a first enable signal, and a second enable signal in response to one of a read enable signal, a program enable signal, and a verification enable signal.

[0126] Fig.14 A voltage curve when performing a read operation is provided for a specific example of the present disclosure. Fig.13 and Fig.14, when the read enable signal RD_EN changes to a logic high level, the control logic 505 can set the first enable signal to a logic low level and the second enable signal to a logic high level within the first time period T1. In this case, the first transistor Q1 in the low-level selection circuit 7032 is turned off, the second transistor Q2 is turned on, and the first low-level VSSX connected to the first end of the second transistor Q2 can be provided to the low-level end of the first NAND gate 7031. The first NAND gate 7031 receives the selection signal and the selection enable signal and outputs a first control signal with a first low-level VSSX level. In the second time period T2 after the first time period T1, the control logic 505 sets the first enable signal to a logic high level and the second enable signal to a logic low level. In this case, the first transistor Q1 is turned on, the second transistor Q2 is turned off, and the second low-level VSS connected to the first end of the first transistor Q1 can be provided to the low-level end of the first NAND gate 7031. The output signal of the first NAND gate 7031 changes from the first control signal with a first low-level VSSX level to the second control signal with a second low-level VSS level.

[0127] In some specific examples, the first time period T1 ranges from 0.5 microseconds to 1 microsecond. In the first time period T1, the third transistor Q3 in the level conversion circuit 800 can be turned on, and the level of the output signal of the level conversion circuit 800 can gradually rise until the second output signal generated by the level conversion circuit 800 reaches the first high level VH. In the second time period T2, the control terminal of the third transistor Q3 receives the second control signal with a level of the second low level VSS, the third transistor Q3 can still remain in the turned-on state, and the level conversion circuit 800 can still maintain the output of the second output signal with a level of the first high level VH. At this time, the absolute value of the voltage difference between the control terminal and the first terminal or the second terminal of the third transistor Q3 is VH-VSS, which is less than the absolute value of the voltage difference between the control terminal and the first terminal or the second terminal of the third transistor Q3 in the first time period T1. VH-VSSX, that is, relative to the first time period T1, the voltage difference applied to the third transistor Q3 in the second time period T2 is reduced.

[0128] Fig.15 for Fig.13 The simulation results of the row decoder are shown Figure 1 , wherein curve A is a voltage curve of the output end of the level conversion circuit 800, and curve B is a voltage curve of the output end of the third processing circuit 703. Fig.15As shown, in the first time period T1, the third processing circuit 703 outputs a first control signal with a first low level VSSX, the first low level VSSX is -2V, and the voltage at the output end of the level conversion circuit 800 rises until it reaches a first high level VH, the first high level VH is 15V; in the second time period T2, the third processing circuit 703 outputs a second control signal with a second low level VSS, the second low level VSS is 0V, and the output end of the level conversion circuit 800 can still maintain the output of the second output signal with a first high level VH, which can explain that in the second time period T2, the level of the control signal received by the control end of the level conversion circuit 800 is increased from the first low level VSSX to the second low level VSS, and the normal operation of the level conversion circuit 800 is not affected.

[0129] In a specific example, when a read operation is required on the storage block, the first high level VH is 15V, then the voltage difference between the control terminal and the first terminal or the second terminal of the third transistor Q3 in the first time period T1 will reach -17V. If the third transistor Q3 operates under a large negative bias for a long time, the electrical performance may be degraded due to the NBTI (Negative Bias Temperature Instability) effect, causing the threshold voltage of the third transistor Q3 to drift negatively and the subthreshold slope to decrease, thereby causing the turn-on rate of the level conversion circuit 800 to decrease and the service life to be shortened.

[0130] In the embodiment of the present disclosure, the row decoder 601 includes a low-level selection circuit 7032 connected to the low-level end of the first NAND gate 7031. The low-level selection circuit 7032 can provide a first low-level VSSX to the low-level end of the first NAND gate 7031 in the first time period T1, and provide a second low-level VSS to the low-level end of the first NAND gate 7031 in the second time period T2, so that the first NAND gate 7031 outputs a first control signal with a level of the first low-level VSSX in the first time period T1, and outputs a second control signal with a level of the second low-level VSS in the second time period T2, so that the level conversion circuit 800 quickly establishes positive feedback and turns on in the first time period T1, and in the second time period T2, the absolute value of the voltage difference between the control end and the first end or the second end of the third transistor Q3 drops to VH-VSS, thereby shortening the working time of the third transistor Q3 under a large negative bias voltage, improving the NBTI of the third transistor Q3, reducing the degree of degradation of the electrical performance of the third transistor Q3, and increasing the service life of the level conversion circuit 800.

[0131] Fig.16 for Fig.13 The simulation results of the row decoder are shown Figure 2The simulation result is a voltage curve obtained after the simulated row decoder performs a ten-year read cycle, wherein multiple curves C are voltage curves at the output end of the level conversion circuit 800, and curve D is a voltage curve at the output end of the third processing circuit 703. Fig.16 As shown, as the number of reads increases, the voltage rise rate at the output end of the level conversion circuit 800 slows down, but after ten years of read cycles, the circuit can still ensure correct function, that is, the level conversion circuit 800 can still maintain the output of the second output signal with the level of the first high level VH. In addition, according to the simulation results, after ten years of read cycles, the attenuation degree of the linear region drain current of the third transistor Q3 is 15%, and for the third transistor Q3 whose control signal level received at the control end in the first period T1 and the second period T2 is the first low level VSSX, after ten years of read cycles, the attenuation degree of the linear region drain current will reach 40%. This shows that in the second period T2, the level of the control signal received at the control end of the level conversion circuit 800 is increased from the first low level VSSX to the second low level VSS, which can improve the NBTI of the third transistor Q3 and reduce the degradation degree of the electrical performance of the third transistor Q3.

[0132] It should be noted that the above embodiment takes the selection of the storage block 303 to perform a read operation on the storage block 303 as an example. In other embodiments, for example, when the storage block 303 needs to be selected to perform a programming operation on the storage block 303, the control logic 505 can generate a selection enable signal, a first enable signal, and a second enable signal based on the programming enable signal. The difference between the above embodiment and the above embodiment can only be that the second end of the fourth transistor Q4 in the level conversion circuit 800 will receive the second high level, and the level values ​​of the second high level and the first high level VH can be different. Here, the first high level VH and the second high level are much greater than the high level VDDX used in the logic circuit 700.

[0133] Based on the concept similar to the above-mentioned memory device, the present disclosure also provides a memory system, which includes: at least one memory device in any of the above-mentioned embodiments; a memory controller coupled to the at least one memory device and configured to control the memory device. For the specific composition and functional implementation of the memory system, please refer to the above description of Figures 1 to 6 For the sake of brevity, the description is not repeated here.

[0134] The present disclosure also provides an operating method of a memory device. Fig.17 A flowchart of an operating method of a memory device provided by an embodiment of the present disclosure is shown in FIG. Fig.17 As shown, the operating method of the memory device includes:

[0135] Step S10: the logic circuit in the row decoder of the memory device generates a first control signal, a second control signal and a first output signal based on the address signal and the state signal of the storage block correspondingly connected to the row decoder; the level of the second control signal is higher than the level of the first control signal;

[0136] Step S20: the level conversion circuit in the row decoder generates a second output signal based on the first output signal in response to the first control signal and the second control signal respectively.

[0137] In some embodiments, in conjunction with reference Figure 7 and Figure 8 , executing step S10 includes: the first processing circuit 701 in the logic circuit 700 generates a selection signal based on the address signal and the state signal of the storage block 303; the second processing circuit 702 in the logic circuit 700 generates a first output signal based on the selection signal; the third processing circuit 703 in the logic circuit 700 generates a first control signal and a second control signal based on the selection signal. Here, the selection signal is a logic high level.

[0138] In some embodiments, the operating method of the memory device further includes: the control logic 505 in the memory device generates a selection enable signal, a first enable signal, and a second enable signal based on one of the read enable signal, the program enable signal, and the verification enable signal. That is, the operating method of the memory device provided in the embodiment of the present disclosure can be applicable to the case where a read operation, a program operation, or a verification operation is performed on the storage block 303.

[0139] In some embodiments, in conjunction with reference Figure 8 , Fig.13 and Fig.14 , the third processing circuit 703 in the logic circuit 700 generates a first control signal and a second control signal based on the selection signal, including: the low level selection circuit 7032 in the third processing circuit 703 outputs a first low level VSSX to a low level end of a first NAND gate 7031 in the third processing circuit 703 in the first period T1, and outputs a second low level VSS to a low level end of the first NAND gate 7031 in the second period T2; based on the selection signal and the selection enable signal, the first NAND gate 7031 outputs a first control signal with a first low level VSSX in the first period T1, and outputs a second control signal with a second low level VSS in the second period T2. Here, the selection enable signal is a logic high level.

[0140] In some embodiments, in conjunction with reference Fig.13 and Fig.14, the low level selection circuit 7032 in the third processing circuit 703 outputs the first low level VSSX to the low level end of the first NAND gate 7031 in the third processing circuit 703 in the first time period T1, and outputs the second low level VSS to the low level end of the first NAND gate 7031 in the second time period T2, including: applying the first enable signal to the control end of the first transistor Q1 in the low level selection circuit 7032, and applying the second enable signal to the control end of the second transistor Q2 in the low level selection circuit 7032; in the first time period T1, the first enable signal is a low level signal, the first transistor Q1 is turned off, the second enable signal is a high level signal, the second transistor Q2 is turned on, and the first low level VSSX is output to the low level end of the first NAND gate 7031; in the second time period, the first enable signal is a high level signal, the first transistor Q1 is turned on, and the second low level VSS is output to the low level end of the first NAND gate 7031, the second enable signal is a low level signal, and the second transistor Q2 is turned off.

[0141] In some specific examples, the first time period T1 ranges from 0.5 microseconds to 1 microsecond.

[0142] In the embodiment of the present disclosure, when it is necessary to operate the storage block 303 corresponding to the row decoder 601, the low level selection circuit 7032 in the logic circuit 700 can provide the first low level VSSX to the low level end of the first NAND gate 7031 in the first time period T1 and provide the second low level VSS to the low level end of the first NAND gate 7031 in the second time period T2 under the action of the first enable signal and the second enable signal generated by the control logic 505. The first NAND gate 7031 can output a first control signal with a level of the first low level VSSX in the first time period T1 and output a second control signal with a level of the second low level VSS in the second time period T2, and the second low level VSS is higher than the first low level VSS. X, the level conversion circuit 800 can generate a second output signal based on the first output signal generated by the logic circuit 700 in response to the first control signal and the second control signal. In the first time period T1, the absolute value of the voltage difference between the control terminal and the first terminal or the second terminal of the third transistor Q3 in the level conversion circuit 800 will reach VH-VSSX, and in the second time period T2, the absolute value of the voltage difference between the control terminal and the first terminal or the second terminal of the third transistor Q3 will be reduced to VH-VSS, thereby shortening the working time of the third transistor Q3 under a large negative bias voltage, improving the NBTI of the third transistor Q3, reducing the degree of degradation of the electrical performance of the third transistor Q3, and improving the service life of the level conversion circuit 800.

[0143] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0144] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0145] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A memory device, characterized in that: The memory device comprises a peripheral circuit and a memory array coupled to the peripheral circuit; the memory array comprises at least one memory block, the peripheral circuit comprises at least one row decoder, one memory block is correspondingly connected to one row decoder; the row decoder comprises a logic circuit and a level conversion circuit; wherein, The logic circuit is configured to generate a first control signal, a second control signal and a first output signal based on an address signal of the storage block correspondingly connected to the row decoder and a state signal; a level of the second control signal is higher than a level of the first control signal; The level conversion circuit is configured to generate a second output signal based on the first output signal in response to the first control signal and the second control signal, respectively.

2. The memory device according to claim 1, wherein: The logic circuit includes a first processing circuit, a second processing circuit and a third processing circuit; the input end of the second processing circuit and the input end of the third processing circuit are respectively connected to the output end of the first processing circuit; the output end of the second processing circuit is connected to the input end of the level conversion circuit; the output end of the third processing circuit is connected to the control end of the level conversion circuit; wherein, The first processing circuit is configured to generate a selection signal based on an address signal and a state signal of the storage block; The second processing circuit is configured to generate the first output signal based on the selection signal; The third processing circuit is configured to generate the first control signal and the second control signal based on the selection signal.

3. The memory device according to claim 2, wherein: The third processing circuit includes a first NAND gate and a low-level selection circuit connected to the low-level end of the first NAND gate; the first input end of the first NAND gate is connected to the output end of the first processing circuit; the second input end of the first NAND gate is connected to the selection enable signal; wherein, The low level selection circuit is configured to output a first low level to the low level end of the first NAND gate in a first period, and output a second low level to the low level end of the first NAND gate in a second period; The first NAND gate is configured to output a first control signal having the first low level in the first period based on the selection signal and the selection enable signal, and to output a second control signal having the second low level in the second period.

4. The memory device according to claim 3, wherein: The low level selection circuit comprises: a first transistor, wherein a first end of the first transistor is connected to a low level end of the first NAND gate; a second end of the first transistor is used to receive the second low level; a control end of the first transistor is connected to a first enable signal; in the first period, the first enable signal is a low level signal, and the first transistor is turned off; in the second period, the first enable signal is a high level signal, and the first transistor is turned on; A second transistor, wherein the second end of the second transistor is connected to the low level end of the first NAND gate and the first end of the first transistor; the first end of the second transistor is used to receive the first low level; the control end of the second transistor is connected to a second enable signal; in the first time period, the second enable signal is a high level signal, and the second transistor is turned on; in the second time period, the second enable signal is a low level signal, and the second transistor is turned off.

5. The memory device according to claim 4, wherein: The peripheral circuit further includes a control logic; the control logic is configured to: The selection enable signal, the first enable signal, and the second enable signal are generated based on one of a read enable signal, a program enable signal, and a verify enable signal.

6. The memory device according to claim 2, wherein: The level conversion circuit comprises: a third transistor, wherein a control terminal of the third transistor is connected to an output terminal of the third processing circuit; a fourth transistor, wherein a first end of the fourth transistor is connected to a first end of the third transistor; and a second end of the fourth transistor is used for receiving a first high level; a fifth transistor, wherein a first end of the fifth transistor is connected to the output end of the second processing circuit, and a second end of the fifth transistor is connected to the second end of the third transistor; an end at which the second end of the fifth transistor and the second end of the third transistor are connected to each other serves as the output end of the level conversion circuit and is connected to the control end of the fourth transistor.

7. The memory device according to claim 2, wherein: The first processing circuit comprises: a second NAND gate, wherein the second NAND gate is configured to receive an address signal of the storage block correspondingly connected to the row decoder, and generate a first initial selection signal based on the address signal of the storage block; a state latch circuit configured to generate a second initial selection signal based on a state signal of the memory block; A first NOR gate is configured to receive the first initial selection signal and the second initial selection signal, and generate the selection signal based on the first initial selection signal and the second initial selection signal.

8. The memory device according to claim 2, wherein: The second processing circuit comprises: N inverters, the N inverters are connected in sequence, and an input end of a first inverter is connected to an output end of the first processing circuit; N is an even number greater than zero; A sixth transistor, wherein a first end of the sixth transistor is connected to the output end of the last inverter, and a second end of the sixth transistor is connected to the input end of the level conversion circuit.

9. The memory device according to claim 1, wherein: The peripheral circuit also includes a word line driver and a plurality of driving transistors; the first end of the driving transistor is connected to the word line driver, and the second end of the driving transistor is connected to the word line in the storage block; the control end of the driving transistor is connected to the output end of the level conversion circuit; the driving transistor is turned on after receiving the second output signal, and couples the word line driver to the word line.

10. A memory system, characterized in that: include: at least one memory device as claimed in any one of claims 1 to 9; A memory controller is coupled to the at least one memory device and is configured to control the memory device.

11. A method for operating a memory device, characterized in that: The operation method comprises: The logic circuit in the row decoder of the memory device generates a first control signal, a second control signal and a first output signal based on an address signal and a state signal of a storage block correspondingly connected to the row decoder; the level of the second control signal is higher than the level of the first control signal; The level conversion circuit in the row decoder generates a second output signal based on the first output signal in response to the first control signal and the second control signal respectively.

12. The method for operating a memory device according to claim 11, characterized in that: The logic circuit in the row decoder of the memory device generates a first control signal, a second control signal and a first output signal based on an address signal and a state signal of a storage block correspondingly connected to the row decoder, including: The first processing circuit in the logic circuit generates a selection signal based on the address signal and the state signal of the storage block; The second processing circuit in the logic circuit generates a first output signal based on the selection signal; The third processing circuit in the logic circuit generates the first control signal and the second control signal based on the selection signal.

13. The method for operating a memory device according to claim 12, wherein: The third processing circuit in the logic circuit generates the first control signal and the second control signal based on the selection signal, including: The low level selection circuit in the third processing circuit outputs a first low level to the low level end of the first NAND gate in the third processing circuit in a first period, and outputs a second low level to the low level end of the first NAND gate in a second period; Based on the selection signal and the selection enable signal, the first NAND gate outputs a first control signal with the first low level in the first period, and outputs a second control signal with the second low level in the second period.

14. The method for operating a memory device according to claim 13, characterized in that: The low level selection circuit in the third processing circuit outputs a first low level to a low level end of a first NAND gate in the third processing circuit in a first period, and outputs a second low level to a low level end of the first NAND gate in a second period, including: Applying a first enable signal to a control terminal of a first transistor in the low level selection circuit, and applying a second enable signal to a control terminal of a second transistor in the low level selection circuit; In the first period, the first enable signal is a low level signal, and the first transistor is turned off; the second enable signal is a high level signal, and the second transistor is turned on, and outputs the first low level to the low level end of the first NAND gate; In the second period, the first enable signal is a high level signal, the first transistor is turned on, and outputs the second low level to the low level end of the first NAND gate; the second enable signal is a low level signal, and the second transistor is turned off.

15. The method for operating a memory device according to claim 14, characterized in that: The operation method also includes: The control logic in the memory device generates the selection enable signal, the first enable signal, and the second enable signal based on one of a read enable signal, a program enable signal, and a verify enable signal.

16. The method for operating a memory device according to claim 13, wherein: The first time period ranges from 0.5 microseconds to 1 microsecond.

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